ARM: at91/dt: split sam9x5 peripheral definitions

PATCH In review Boris BREZILLON 6 participants 13 messages Aug 7, 2013 – Aug 20, 2013

Subsystems (2)

Device tree bindings Arm/Microchip (AT91) SoC support

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Boris BREZILLON

author

2013-08-07 10:14 UTC #0 lore raw

PATCH 1/1 ARM: at91/dt: split sam9x5 peripheral definitions

This patch splits the sam9x5 peripheral definitions into:
- a common base for all sam9x5 SoCs (at91sam9x5.dtsi)
- several optional peripheral definitions which will be included by specific sam9x5 SoCs (at91sam9x5_'periph name'.dtsi)

This provides a better representation of the real hardware (drop unneeded dt nodes) and avoids future peripheral id conflict (lcdc and isi both use peripheral id 25).

Signed-off-by Boris BREZILLON <[email protected]>

---
 arch/arm/boot/dts/at91sam9g25.dtsi       |    2 +
 arch/arm/boot/dts/at91sam9g35.dtsi       |    1 +
 arch/arm/boot/dts/at91sam9x25.dtsi       |   24 ++---------
 arch/arm/boot/dts/at91sam9x35.dtsi       |    1 +
 arch/arm/boot/dts/at91sam9x5.dtsi        |   67 ------------------------------
 arch/arm/boot/dts/at91sam9x5_macb0.dtsi  |   56 +++++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9x5_macb1.dtsi  |   44 ++++++++++++++++++++
 arch/arm/boot/dts/at91sam9x5_usart3.dtsi |   51 +++++++++++++++++++++++
 8 files changed, 158 insertions(+), 88 deletions(-)
 create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi
 create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi
 create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi

arch/arm/boot/dts/at91sam9g25.dtsi +2 -0

index b4ec6fe..17b8799 100644
@@ -7,6 +7,8 @@
  */
 
 #include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
 / {
 	model = "Atmel AT91SAM9G25 SoC";

arch/arm/boot/dts/at91sam9g35.dtsi +1 -0

index bebf9f5..e35c2fc 100644
@@ -7,6 +7,7 @@
  */
 
 #include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
 / {
 	model = "Atmel AT91SAM9G35 SoC";

arch/arm/boot/dts/at91sam9x25.dtsi +3 ~~-21~~

index 49e94ab..c255421 100644
@@ -7,6 +7,9 @@
  */
 
 #include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_macb1.dtsi"
 
 / {
 	model = "Atmel AT91SAM9X25 SoC";

@@ -22,27 +25,6 @@
 				       0x80000000 0xfffd0000 0xb83fffff  /* pioC */
 				       0x003fffff 0x003f8000 0x00000000  /* pioD */
 				      >;
-
-				macb1 {
-					pinctrl_macb1_rmii: macb1_rmii-0 {
-						atmel,pins =
-							<AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC16 periph B */
-							 AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC18 periph B */
-							 AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC19 periph B */
-							 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC20 periph B */
-							 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC21 periph B */
-							 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC27 periph B */
-							 AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC28 periph B */
-							 AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC29 periph B */
-							 AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC30 periph B */
-							 AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC31 periph B */
-					};
-				};
-			};
-
-			macb1: ethernet at f8030000 {
-				pinctrl-names = "default";
-				pinctrl-0 = <&pinctrl_macb1_rmii>;
 			};
 		};
 	};

arch/arm/boot/dts/at91sam9x35.dtsi +1 -0

index 1a3d525..8eac66c 100644
@@ -7,6 +7,7 @@
  */
 
 #include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
 / {
 	model = "Atmel AT91SAM9X35 SoC";

arch/arm/boot/dts/at91sam9x5.dtsi +0 ~~-67~~

85 lines not on this page · raw message

arch/arm/boot/dts/at91sam9x5_macb0.dtsi new file +56 -0

56 lines not on this page · raw message

arch/arm/boot/dts/at91sam9x5_macb1.dtsi new file +44 -0

44 lines not on this page · raw message

arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file +51 -0

51 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Richard Genoud

2013-08-07 10:38 UTC #1 lore raw

2013/8/7 Boris BREZILLON <[email protected]>:

Quoted 24 lines

This patch splits the sam9x5 peripheral definitions into:
- a common base for all sam9x5 SoCs (at91sam9x5.dtsi)
- several optional peripheral definitions which will be included by specific sam9x5 SoCs (at91sam9x5_'periph name'.dtsi)
This provides a better representation of the real hardware (drop unneeded dt nodes) and avoids future peripheral id conflict (lcdc and isi both use peripheral id 25).
Signed-off-by Boris BREZILLON <[email protected]>
---
 arch/arm/boot/dts/at91sam9g25.dtsi       |    2 +
 arch/arm/boot/dts/at91sam9g35.dtsi       |    1 +
 arch/arm/boot/dts/at91sam9x25.dtsi       |   24 ++---------
 arch/arm/boot/dts/at91sam9x35.dtsi       |    1 +
 arch/arm/boot/dts/at91sam9x5.dtsi        |   67 ------------------------------
 arch/arm/boot/dts/at91sam9x5_macb0.dtsi  |   56 +++++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9x5_macb1.dtsi  |   44 ++++++++++++++++++++
 arch/arm/boot/dts/at91sam9x5_usart3.dtsi |   51 +++++++++++++++++++++++
 8 files changed, 158 insertions(+), 88 deletions(-)
 create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi
 create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi
 create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi

[snip]

arch/arm/boot/dts/at91sam9x5_usart3.dtsi line 3

Quoted 9 lines

arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file +3 -0

new file mode 100644
index 0000000..5589579
@@ -0,0 +1,51 @@
+/*
+ * at91sam9x5_lcdc.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * 4 USART.

One minor comment mistake here !

Quoted 51 lines

arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file +48 -1

+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+       ahb {
+               apb {
+                       pinctrl at fffff400 {
+                               usart3 {
+                                       pinctrl_usart3: usart3-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PC22 periph B with pullup */
+                                                        AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC23 periph B */
+                                       };
+
+                                       pinctrl_usart3_rts: usart3_rts-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC24 periph B */
+                                       };
+
+                                       pinctrl_usart3_cts: usart3_cts-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC25 periph B */
+                                       };
+
+                                       pinctrl_usart3_sck: usart3_sck-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC26 periph B */
+                                       };
+                               };
+                       };
+
+                       usart3: serial at f8028000 {
+                               compatible = "atmel,at91sam9260-usart";
+                               reg = <0xf8028000 0x200>;
+                               interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart3>;
+                               status = "disabled";
+                       };
+               };
+       };
+};
--

1.7.9.5

Signature · 1 line

for me, ck means con kolivas and not calvin klein... does it mean I'm a geek ?

boris brezillon

author

2013-08-07 10:55 UTC #2 lore raw

Hello Richard,

Quoted 26 lines · Richard Genoud

2013/8/7 Boris BREZILLON <[email protected]>:
Quoted 24 lines
This patch splits the sam9x5 peripheral definitions into:
- a common base for all sam9x5 SoCs (at91sam9x5.dtsi)
- several optional peripheral definitions which will be included by specific sam9x5 SoCs (at91sam9x5_'periph name'.dtsi)
This provides a better representation of the real hardware (drop unneeded dt nodes) and avoids future peripheral id conflict (lcdc and isi both use peripheral id 25).
Signed-off-by Boris BREZILLON <[email protected]>
---
  arch/arm/boot/dts/at91sam9g25.dtsi       |    2 +
  arch/arm/boot/dts/at91sam9g35.dtsi       |    1 +
  arch/arm/boot/dts/at91sam9x25.dtsi       |   24 ++---------
  arch/arm/boot/dts/at91sam9x35.dtsi       |    1 +
  arch/arm/boot/dts/at91sam9x5.dtsi        |   67 ------------------------------
  arch/arm/boot/dts/at91sam9x5_macb0.dtsi  |   56 +++++++++++++++++++++++++
  arch/arm/boot/dts/at91sam9x5_macb1.dtsi  |   44 ++++++++++++++++++++
  arch/arm/boot/dts/at91sam9x5_usart3.dtsi |   51 +++++++++++++++++++++++
  8 files changed, 158 insertions(+), 88 deletions(-)
create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi
[snip]

Quoted 10 lines

arch/arm/boot/dts/at91sam9x5_usart3.dtsi line 3
Quoted 9 lines
arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file +3 -0
new file mode 100644
index 0000000..5589579
@@ -0,0 +1,51 @@
+/*
+ * at91sam9x5_lcdc.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * 4 USART.
One minor comment mistake here !

Nice catch!

I'll fix it for the next version.

BTW did you test it (I didn't: I don't have any board with this SoC family) ?

This separation was formerly done in the "at91 common clk" series but I removed it
from the new version (which I will submit soon) to ease the review and tests.

Best Regards,

Boris

Quoted 53 lines

Quoted 51 lines

arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file +48 -1

+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+       ahb {
+               apb {
+                       pinctrl at fffff400 {
+                               usart3 {
+                                       pinctrl_usart3: usart3-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PC22 periph B with pullup */
+                                                        AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC23 periph B */
+                                       };
+
+                                       pinctrl_usart3_rts: usart3_rts-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC24 periph B */
+                                       };
+
+                                       pinctrl_usart3_cts: usart3_cts-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC25 periph B */
+                                       };
+
+                                       pinctrl_usart3_sck: usart3_sck-0 {
+                                               atmel,pins =
+                                                       <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC26 periph B */
+                                       };
+                               };
+                       };
+
+                       usart3: serial at f8028000 {
+                               compatible = "atmel,at91sam9260-usart";
+                               reg = <0xf8028000 0x200>;
+                               interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_usart3>;
+                               status = "disabled";
+                       };
+               };
+       };
+};
--

1.7.9.5

Richard Genoud

2013-08-07 10:59 UTC #3 lore raw

2013/8/7 boris brezillon <[email protected]>:

Quoted 50 lines

Hello Richard,
Quoted 32 lines · Richard Genoud
2013/8/7 Boris BREZILLON <[email protected]>:
Quoted 28 lines
This patch splits the sam9x5 peripheral definitions into:
- a common base for all sam9x5 SoCs (at91sam9x5.dtsi)
- several optional peripheral definitions which will be included by specific
sam9x5 SoCs (at91sam9x5_'periph name'.dtsi)
This provides a better representation of the real hardware (drop unneeded dt nodes) and avoids future peripheral id conflict (lcdc and isi both use peripheral id 25).
Signed-off-by Boris BREZILLON <[email protected]>
---
  arch/arm/boot/dts/at91sam9g25.dtsi       |    2 +
  arch/arm/boot/dts/at91sam9g35.dtsi       |    1 +
  arch/arm/boot/dts/at91sam9x25.dtsi       |   24 ++---------
  arch/arm/boot/dts/at91sam9x35.dtsi       |    1 +
  arch/arm/boot/dts/at91sam9x5.dtsi        |   67
------------------------------
  arch/arm/boot/dts/at91sam9x5_macb0.dtsi  |   56
+++++++++++++++++++++++++
  arch/arm/boot/dts/at91sam9x5_macb1.dtsi  |   44 ++++++++++++++++++++
  arch/arm/boot/dts/at91sam9x5_usart3.dtsi |   51 +++++++++++++++++++++++
  8 files changed, 158 insertions(+), 88 deletions(-)
create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi
[snip]
Quoted 1 line
Quoted 13 lines
Quoted 11 lines
arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file +2 -0
new file mode 100644
index 0000000..5589579
@@ -0,0 +1,51 @@
+/*
+ * at91sam9x5_lcdc.dtsi - Device Tree Include file for AT91SAM9x5 SoC
with
+ * 4 USART.
One minor comment mistake here !

Quoted 6 lines

Nice catch!
I'll fix it for the next version.
BTW did you test it (I didn't: I don't have any board with this SoC family) ?

Not yet, will do it !

Quoted 5 lines

This separation was formerly done in the "at91 common clk" series but I removed it
from the new version (which I will submit soon) to ease the review and tests.

ok !

Thanks,
Richard

Thomas Petazzoni

2013-08-07 16:08 UTC #4 lore raw

In reply to Boris BREZILLON

Dear Boris BREZILLON,

Quoted 10 lines · Boris BREZILLON

This patch splits the sam9x5 peripheral definitions into:
- a common base for all sam9x5 SoCs (at91sam9x5.dtsi)
- several optional peripheral definitions which will be included by specific sam9x5 SoCs (at91sam9x5_'periph name'.dtsi)
This provides a better representation of the real hardware (drop unneeded dt nodes) and avoids future peripheral id conflict (lcdc and isi both use peripheral id 25).
Signed-off-by Boris BREZILLON <[email protected]>

Quoted 13 lines

---
 arch/arm/boot/dts/at91sam9g25.dtsi       |    2 +
 arch/arm/boot/dts/at91sam9g35.dtsi       |    1 +
 arch/arm/boot/dts/at91sam9x25.dtsi       |   24 ++---------
 arch/arm/boot/dts/at91sam9x35.dtsi       |    1 +
 arch/arm/boot/dts/at91sam9x5.dtsi        |   67 ------------------------------
 arch/arm/boot/dts/at91sam9x5_macb0.dtsi  |   56 +++++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9x5_macb1.dtsi  |   44 ++++++++++++++++++++
 arch/arm/boot/dts/at91sam9x5_usart3.dtsi |   51 +++++++++++++++++++++++
 8 files changed, 158 insertions(+), 88 deletions(-)
 create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi
 create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi
 create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi

Hum, do we really want to have .dtsi files per peripheral? I might have overlooked this, but I think it's the first time we would have this in arch/arm/boot/dts.

Thomas

Signature · 4 lines

Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

boris brezillon

author

2013-08-07 17:28 UTC #5 lore raw

Hello Thomas,

Sorry for the noise, this mail was filtered by LKML and LAKML beacause thunderbird
added HTML contents.

Quoted 26 lines · Thomas Petazzoni

Dear Boris BREZILLON,
Quoted 20 lines · Boris BREZILLON
This patch splits the sam9x5 peripheral definitions into:
- a common base for all sam9x5 SoCs (at91sam9x5.dtsi)
- several optional peripheral definitions which will be included by specific sam9x5 SoCs (at91sam9x5_'periph name'.dtsi)
This provides a better representation of the real hardware (drop unneeded dt nodes) and avoids future peripheral id conflict (lcdc and isi both use peripheral id 25).
Signed-off-by Boris BREZILLON<[email protected]>
---
  arch/arm/boot/dts/at91sam9g25.dtsi       |    2 +
  arch/arm/boot/dts/at91sam9g35.dtsi       |    1 +
  arch/arm/boot/dts/at91sam9x25.dtsi       |   24 ++---------
  arch/arm/boot/dts/at91sam9x35.dtsi       |    1 +
  arch/arm/boot/dts/at91sam9x5.dtsi        |   67 ------------------------------
  arch/arm/boot/dts/at91sam9x5_macb0.dtsi  |   56 +++++++++++++++++++++++++
  arch/arm/boot/dts/at91sam9x5_macb1.dtsi  |   44 ++++++++++++++++++++
  arch/arm/boot/dts/at91sam9x5_usart3.dtsi |   51 +++++++++++++++++++++++
  8 files changed, 158 insertions(+), 88 deletions(-)
Quoted 3 lines
create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi

Quoted 3 lines

Hum, do we really want to have .dtsi files per peripheral? I might have overlooked this, but I think it's the first time we would have this in arch/arm/boot/dts.

It's not one .dtsi file for each available peripheral but for each **optional**
peripheral (those which are not available for all sam9x5 SoCs).

For example:

macb0 is available in this SoCs:
- 9g25
- 9g35
- 9x25
- 9x35
and not available in 9g15 SoC.

And we have different combinatory for each of the optional devices.

IMHO, defining the unneeded dt nodes in the common sam9x5.dtsi is a bad idea, because
the dtb footprint will be bigger for SoC which does not have the optional peripherals
and the dt hardware representation will be false.

I see two options to solve this issue:
1) define a .dtsi file describing the optional peripherals and include
these .dtsi in the SoC.dtsi file
(as I proposed, but maybe the names are not appropriate)
2) copy the peripheral definitions in each SoC .dtsi file

I prefer option 1) as it's safer than copying the definition (update of dtsi is easier and there is no
risk to introduce a new bug when copying definitions).

Please, tell me if you see other options, or if you think this "issue" should not be solved.

Best Regards,

Boris

Quoted 1 line

Thomas

Jean-Christophe PLAGNIOL-VILLARD

2013-08-08 14:07 UTC #6 lore raw

In reply to Boris BREZILLON

Quoted 8 lines · Boris BREZILLON

This patch splits the sam9x5 peripheral definitions into:
- a common base for all sam9x5 SoCs (at91sam9x5.dtsi)
- several optional peripheral definitions which will be included by specific sam9x5 SoCs (at91sam9x5_'periph name'.dtsi)
This provides a better representation of the real hardware (drop unneeded dt nodes) and avoids future peripheral id conflict (lcdc and isi both use peripheral id 25).

I really don't like this

the mapping is soc specific (here familly) so I does not see any advantage except move files so NO for me

Best Regards,
J.

Quoted 359 lines

Signed-off-by Boris BREZILLON <[email protected]>

---
 arch/arm/boot/dts/at91sam9g25.dtsi       |    2 +
 arch/arm/boot/dts/at91sam9g35.dtsi       |    1 +
 arch/arm/boot/dts/at91sam9x25.dtsi       |   24 ++---------
 arch/arm/boot/dts/at91sam9x35.dtsi       |    1 +
 arch/arm/boot/dts/at91sam9x5.dtsi        |   67 ------------------------------
 arch/arm/boot/dts/at91sam9x5_macb0.dtsi  |   56 +++++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9x5_macb1.dtsi  |   44 ++++++++++++++++++++
 arch/arm/boot/dts/at91sam9x5_usart3.dtsi |   51 +++++++++++++++++++++++
 8 files changed, 158 insertions(+), 88 deletions(-)
 create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi
 create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi
 create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi

arch/arm/boot/dts/at91sam9g25.dtsi +2 -0

index b4ec6fe..17b8799 100644
@@ -7,6 +7,8 @@
  */
 
 #include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
 / {
 	model = "Atmel AT91SAM9G25 SoC";

arch/arm/boot/dts/at91sam9g35.dtsi +1 -0

index bebf9f5..e35c2fc 100644
@@ -7,6 +7,7 @@
  */
 
 #include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
 / {
 	model = "Atmel AT91SAM9G35 SoC";

arch/arm/boot/dts/at91sam9x25.dtsi +3 ~~-21~~

index 49e94ab..c255421 100644
@@ -7,6 +7,9 @@
  */
 
 #include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_macb1.dtsi"
 
 / {
 	model = "Atmel AT91SAM9X25 SoC";

@@ -22,27 +25,6 @@
 				       0x80000000 0xfffd0000 0xb83fffff  /* pioC */
 				       0x003fffff 0x003f8000 0x00000000  /* pioD */
 				      >;
-
-				macb1 {
-					pinctrl_macb1_rmii: macb1_rmii-0 {
-						atmel,pins =
-							<AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC16 periph B */
-							 AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC18 periph B */
-							 AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC19 periph B */
-							 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC20 periph B */
-							 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC21 periph B */
-							 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC27 periph B */
-							 AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC28 periph B */
-							 AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC29 periph B */
-							 AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC30 periph B */
-							 AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC31 periph B */
-					};
-				};
-			};
-
-			macb1: ethernet at f8030000 {
-				pinctrl-names = "default";
-				pinctrl-0 = <&pinctrl_macb1_rmii>;
 			};
 		};
 	};

arch/arm/boot/dts/at91sam9x35.dtsi +1 -0

index 1a3d525..8eac66c 100644
@@ -7,6 +7,7 @@
  */
 
 #include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
 / {
 	model = "Atmel AT91SAM9X35 SoC";

arch/arm/boot/dts/at91sam9x5.dtsi +0 ~~-67~~

index 57d45f5..05f4c74 100644
@@ -206,29 +206,6 @@
 					};
 				};
 
-				usart3 {
-					pinctrl_usart3: usart3-0 {
-						atmel,pins =
-							<AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PC22 periph B with pullup */
-							 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC23 periph B */
-					};
-
-					pinctrl_usart3_rts: usart3_rts-0 {
-						atmel,pins =
-							<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC24 periph B */
-					};
-
-					pinctrl_usart3_cts: usart3_cts-0 {
-						atmel,pins =
-							<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC25 periph B */
-					};
-
-					pinctrl_usart3_sck: usart3_sck-0 {
-						atmel,pins =
-							<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC26 periph B */
-					};
-				};
-
 				uart0 {
 					pinctrl_uart0: uart0-0 {
 						atmel,pins =

@@ -277,34 +254,6 @@
 					};
 				};
 
-				macb0 {
-					pinctrl_macb0_rmii: macb0_rmii-0 {
-						atmel,pins =
-							<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A */
-							 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A */
-							 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB2 periph A */
-							 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB3 periph A */
-							 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB4 periph A */
-							 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB5 periph A */
-							 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB6 periph A */
-							 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB7 periph A */
-							 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB9 periph A */
-							 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB10 periph A */
-					};
-
-					pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
-						atmel,pins =
-							<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB8 periph A */
-							 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB11 periph A */
-							 AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB12 periph A */
-							 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB13 periph A */
-							 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB14 periph A */
-							 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB15 periph A */
-							 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB16 periph A */
-							 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB17 periph A */
-					};
-				};
-
 				mmc0 {
 					pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
 						atmel,pins =

@@ -605,22 +554,6 @@
 				status = "disabled";
 			};
 
-			macb0: ethernet at f802c000 {
-				compatible = "cdns,at32ap7000-macb", "cdns,macb";
-				reg = <0xf802c000 0x100>;
-				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
-				pinctrl-names = "default";
-				pinctrl-0 = <&pinctrl_macb0_rmii>;
-				status = "disabled";
-			};
-
-			macb1: ethernet at f8030000 {
-				compatible = "cdns,at32ap7000-macb", "cdns,macb";
-				reg = <0xf8030000 0x100>;
-				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
-				status = "disabled";
-			};
-
 			i2c0: i2c at f8010000 {
 				compatible = "atmel,at91sam9x5-i2c";
 				reg = <0xf8010000 0x100>;

arch/arm/boot/dts/at91sam9x5_macb0.dtsi new file +56 -0

new file mode 100644
index 0000000..55731ff
@@ -0,0 +1,56 @@
+/*
+ * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
+ * Ethernet interface.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	ahb {
+		apb {
+			pinctrl at fffff400 {
+				macb0 {
+					pinctrl_macb0_rmii: macb0_rmii-0 {
+						atmel,pins =
+							<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A */
+							 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A */
+							 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB2 periph A */
+							 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB3 periph A */
+							 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB4 periph A */
+							 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB5 periph A */
+							 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB6 periph A */
+							 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB7 periph A */
+							 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB9 periph A */
+							 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB10 periph A */
+					};
+
+					pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
+						atmel,pins =
+							<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB8 periph A */
+							 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB11 periph A */
+							 AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB12 periph A */
+							 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB13 periph A */
+							 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB14 periph A */
+							 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB15 periph A */
+							 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB16 periph A */
+							 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB17 periph A */
+					};
+				};
+			};
+
+			macb0: ethernet at f802c000 {
+				compatible = "cdns,at32ap7000-macb", "cdns,macb";
+				reg = <0xf802c000 0x100>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_macb0_rmii>;
+				status = "disabled";
+			};
+		};
+	};
+};

arch/arm/boot/dts/at91sam9x5_macb1.dtsi new file +44 -0

new file mode 100644
index 0000000..77425a6
@@ -0,0 +1,44 @@
+/*
+ * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2
+ * Ethernet interfaces.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	ahb {
+		apb {
+			pinctrl at fffff400 {
+				macb1 {
+					pinctrl_macb1_rmii: macb1_rmii-0 {
+						atmel,pins =
+							<AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC16 periph B */
+							 AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC18 periph B */
+							 AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC19 periph B */
+							 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC20 periph B */
+							 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC21 periph B */
+							 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC27 periph B */
+							 AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC28 periph B */
+							 AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC29 periph B */
+							 AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC30 periph B */
+							 AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC31 periph B */
+					};
+				};
+			};
+
+			macb1: ethernet at f8030000 {
+				compatible = "cdns,at32ap7000-macb", "cdns,macb";
+				reg = <0xf8030000 0x100>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_macb1_rmii>;
+				status = "disabled";
+			};
+		};
+	};
+};

arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file +51 -0

new file mode 100644
index 0000000..5589579
@@ -0,0 +1,51 @@
+/*
+ * at91sam9x5_lcdc.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * 4 USART.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	ahb {
+		apb {
+			pinctrl at fffff400 {
+				usart3 {
+					pinctrl_usart3: usart3-0 {
+						atmel,pins =
+							<AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PC22 periph B with pullup */
+							 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;		/* PC23 periph B */
+					};
+
+					pinctrl_usart3_rts: usart3_rts-0 {
+						atmel,pins =
+							<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;		/* PC24 periph B */
+					};
+
+					pinctrl_usart3_cts: usart3_cts-0 {
+						atmel,pins =
+							<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;		/* PC25 periph B */
+					};
+
+					pinctrl_usart3_sck: usart3_sck-0 {
+						atmel,pins =
+							<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;		/* PC26 periph B */
+					};
+				};
+			};
+
+			usart3: serial at f8028000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xf8028000 0x200>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usart3>;
+				status = "disabled";
+			};
+		};
+	};
+};

Signature · 1 line

1.7.9.5

boris brezillon

author

2013-08-08 15:23 UTC #7 lore raw

Hello Jean-Christophe,

Quoted 6 lines · Jean-Christophe PLAGNIOL-VILLARD

Quoted 5 lines · Boris BREZILLON
This patch splits the sam9x5 peripheral definitions into:
- a common base for all sam9x5 SoCs (at91sam9x5.dtsi)
- several optional peripheral definitions which will be included by specific sam9x5 SoCs (at91sam9x5_'periph name'.dtsi)

Quoted 7 lines

Quoted 3 lines
This provides a better representation of the real hardware (drop unneeded dt nodes) and avoids future peripheral id conflict (lcdc and isi both use peripheral id 25).
I really don't like this
the mapping is soc specific (here familly) so I does not see any advantage except move files so NO for me

Let me explain in detail why I did that.

This separation was part of the "at91 common clk" series and was here to avoid the
definition of unavailable clocks or definition of clocks with the same id (which may result
in bad clk registration).
If we keep all the definitions in one .dtsi file (even the one which are not really available),
I may need to add a new property to each peripheral (and system) clk node to specify the
availabilty of the clock (something similar to 'status="disabled"' in device nodes).

As explained to Thomas, I thought device tree was here to give a real description of the
hardware parts (in case of sam9x5.dtsi the description of the common parts of sam9x5 SoC
family).
If you define peripherals that are not present in a SoC (lets say macb0 for sam9g15) you break
this rule.

I'm not telling I have the right approach here, I'm just trying to understand what should be done and
what should not.

Finally, I'd like to point that the memory footprint of the dtb file generated after this patch has been
applied is bit smaller (even if it won't make a real difference):

with this patch:

15937 arch/arm/boot/dts/at91-ariag25.dtb
15860 arch/arm/boot/dts/at91sam9g15ek.dtb
16905 arch/arm/boot/dts/at91sam9g25ek.dtb
16473 arch/arm/boot/dts/at91sam9g35ek.dtb
17341 arch/arm/boot/dts/at91sam9x25ek.dtb
16473 arch/arm/boot/dts/at91sam9x35ek.dtb

without this patch:

16077 arch/arm/boot/dts/at91-ariag25.dtb
16824 arch/arm/boot/dts/at91sam9g15ek.dtb
16849 arch/arm/boot/dts/at91sam9g25ek.dtb
16849 arch/arm/boot/dts/at91sam9g35ek.dtb
15017 arch/arm/boot/dts/at91sam9m10g45ek.dtb
17145 arch/arm/boot/dts/at91sam9x25ek.dtb
16849 arch/arm/boot/dts/at91sam9x35ek.dtb

Best Regards,

Boris

Quoted 360 lines

Best Regards,
J.

Quoted 358 lines

Signed-off-by Boris BREZILLON <[email protected]>

---
  arch/arm/boot/dts/at91sam9g25.dtsi       |    2 +
  arch/arm/boot/dts/at91sam9g35.dtsi       |    1 +
  arch/arm/boot/dts/at91sam9x25.dtsi       |   24 ++---------
  arch/arm/boot/dts/at91sam9x35.dtsi       |    1 +
  arch/arm/boot/dts/at91sam9x5.dtsi        |   67 ------------------------------
  arch/arm/boot/dts/at91sam9x5_macb0.dtsi  |   56 +++++++++++++++++++++++++
  arch/arm/boot/dts/at91sam9x5_macb1.dtsi  |   44 ++++++++++++++++++++
  arch/arm/boot/dts/at91sam9x5_usart3.dtsi |   51 +++++++++++++++++++++++
  8 files changed, 158 insertions(+), 88 deletions(-)

create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi

arch/arm/boot/dts/at91sam9g25.dtsi +2 -0

index b4ec6fe..17b8799 100644
@@ -7,6 +7,8 @@
   */
 
  #include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
  / {
  	model = "Atmel AT91SAM9G25 SoC";

arch/arm/boot/dts/at91sam9g35.dtsi +1 -0

index bebf9f5..e35c2fc 100644
@@ -7,6 +7,7 @@
   */
 
  #include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
  / {
  	model = "Atmel AT91SAM9G35 SoC";

arch/arm/boot/dts/at91sam9x25.dtsi +3 ~~-21~~

index 49e94ab..c255421 100644
@@ -7,6 +7,9 @@
   */
 
  #include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_macb1.dtsi"
 
  / {
  	model = "Atmel AT91SAM9X25 SoC";

@@ -22,27 +25,6 @@
  				       0x80000000 0xfffd0000 0xb83fffff  /* pioC */
  				       0x003fffff 0x003f8000 0x00000000  /* pioD */
  				      >;
-
-				macb1 {
-					pinctrl_macb1_rmii: macb1_rmii-0 {
-						atmel,pins =
-							<AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC16 periph B */
-							 AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC18 periph B */
-							 AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC19 periph B */
-							 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC20 periph B */
-							 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC21 periph B */
-							 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC27 periph B */
-							 AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC28 periph B */
-							 AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC29 periph B */
-							 AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC30 periph B */
-							 AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC31 periph B */
-					};
-				};
-			};
-
-			macb1: ethernet at f8030000 {
-				pinctrl-names = "default";
-				pinctrl-0 = <&pinctrl_macb1_rmii>;
  			};
  		};
  	};

arch/arm/boot/dts/at91sam9x35.dtsi +1 -0

index 1a3d525..8eac66c 100644
@@ -7,6 +7,7 @@
   */
 
  #include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
  / {
  	model = "Atmel AT91SAM9X35 SoC";

arch/arm/boot/dts/at91sam9x5.dtsi +0 ~~-67~~

index 57d45f5..05f4c74 100644
@@ -206,29 +206,6 @@
  					};
  				};
 
-				usart3 {
-					pinctrl_usart3: usart3-0 {
-						atmel,pins =
-							<AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PC22 periph B with pullup */
-							 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC23 periph B */
-					};
-
-					pinctrl_usart3_rts: usart3_rts-0 {
-						atmel,pins =
-							<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC24 periph B */
-					};
-
-					pinctrl_usart3_cts: usart3_cts-0 {
-						atmel,pins =
-							<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC25 periph B */
-					};
-
-					pinctrl_usart3_sck: usart3_sck-0 {
-						atmel,pins =
-							<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC26 periph B */
-					};
-				};
-
  				uart0 {
  					pinctrl_uart0: uart0-0 {
  						atmel,pins =

@@ -277,34 +254,6 @@
  					};
  				};
 
-				macb0 {
-					pinctrl_macb0_rmii: macb0_rmii-0 {
-						atmel,pins =
-							<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A */
-							 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A */
-							 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB2 periph A */
-							 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB3 periph A */
-							 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB4 periph A */
-							 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB5 periph A */
-							 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB6 periph A */
-							 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB7 periph A */
-							 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB9 periph A */
-							 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB10 periph A */
-					};
-
-					pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
-						atmel,pins =
-							<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB8 periph A */
-							 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB11 periph A */
-							 AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB12 periph A */
-							 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB13 periph A */
-							 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB14 periph A */
-							 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB15 periph A */
-							 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB16 periph A */
-							 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB17 periph A */
-					};
-				};
-
  				mmc0 {
  					pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  						atmel,pins =

@@ -605,22 +554,6 @@
  				status = "disabled";
  			};
 
-			macb0: ethernet at f802c000 {
-				compatible = "cdns,at32ap7000-macb", "cdns,macb";
-				reg = <0xf802c000 0x100>;
-				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
-				pinctrl-names = "default";
-				pinctrl-0 = <&pinctrl_macb0_rmii>;
-				status = "disabled";
-			};
-
-			macb1: ethernet at f8030000 {
-				compatible = "cdns,at32ap7000-macb", "cdns,macb";
-				reg = <0xf8030000 0x100>;
-				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
-				status = "disabled";
-			};
-
  			i2c0: i2c at f8010000 {
  				compatible = "atmel,at91sam9x5-i2c";
  				reg = <0xf8010000 0x100>;

arch/arm/boot/dts/at91sam9x5_macb0.dtsi new file +56 -0

new file mode 100644
index 0000000..55731ff
@@ -0,0 +1,56 @@
+/*
+ * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
+ * Ethernet interface.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	ahb {
+		apb {
+			pinctrl at fffff400 {
+				macb0 {
+					pinctrl_macb0_rmii: macb0_rmii-0 {
+						atmel,pins =
+							<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A */
+							 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A */
+							 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB2 periph A */
+							 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB3 periph A */
+							 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB4 periph A */
+							 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB5 periph A */
+							 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB6 periph A */
+							 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB7 periph A */
+							 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB9 periph A */
+							 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB10 periph A */
+					};
+
+					pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
+						atmel,pins =
+							<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB8 periph A */
+							 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB11 periph A */
+							 AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB12 periph A */
+							 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB13 periph A */
+							 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB14 periph A */
+							 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB15 periph A */
+							 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB16 periph A */
+							 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB17 periph A */
+					};
+				};
+			};
+
+			macb0: ethernet at f802c000 {
+				compatible = "cdns,at32ap7000-macb", "cdns,macb";
+				reg = <0xf802c000 0x100>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_macb0_rmii>;
+				status = "disabled";
+			};
+		};
+	};
+};

arch/arm/boot/dts/at91sam9x5_macb1.dtsi new file +44 -0

new file mode 100644
index 0000000..77425a6
@@ -0,0 +1,44 @@
+/*
+ * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2
+ * Ethernet interfaces.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	ahb {
+		apb {
+			pinctrl at fffff400 {
+				macb1 {
+					pinctrl_macb1_rmii: macb1_rmii-0 {
+						atmel,pins =
+							<AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC16 periph B */
+							 AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC18 periph B */
+							 AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC19 periph B */
+							 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC20 periph B */
+							 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC21 periph B */
+							 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC27 periph B */
+							 AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC28 periph B */
+							 AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC29 periph B */
+							 AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC30 periph B */
+							 AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC31 periph B */
+					};
+				};
+			};
+
+			macb1: ethernet at f8030000 {
+				compatible = "cdns,at32ap7000-macb", "cdns,macb";
+				reg = <0xf8030000 0x100>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_macb1_rmii>;
+				status = "disabled";
+			};
+		};
+	};
+};

arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file +51 -0

new file mode 100644
index 0000000..5589579
@@ -0,0 +1,51 @@
+/*
+ * at91sam9x5_lcdc.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * 4 USART.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	ahb {
+		apb {
+			pinctrl at fffff400 {
+				usart3 {
+					pinctrl_usart3: usart3-0 {
+						atmel,pins =
+							<AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PC22 periph B with pullup */
+							 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;		/* PC23 periph B */
+					};
+
+					pinctrl_usart3_rts: usart3_rts-0 {
+						atmel,pins =
+							<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;		/* PC24 periph B */
+					};
+
+					pinctrl_usart3_cts: usart3_cts-0 {
+						atmel,pins =
+							<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;		/* PC25 periph B */
+					};
+
+					pinctrl_usart3_sck: usart3_sck-0 {
+						atmel,pins =
+							<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;		/* PC26 periph B */
+					};
+				};
+			};
+
+			usart3: serial at f8028000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xf8028000 0x200>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usart3>;
+				status = "disabled";
+			};
+		};
+	};
+};

Signature · 1 line

1.7.9.5

boris brezillon

author

2013-08-08 15:52 UTC #8 lore raw

Quoted 51 lines · boris brezillon

Hello Jean-Christophe,
Quoted 12 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 11 lines · Boris BREZILLON
This patch splits the sam9x5 peripheral definitions into:
- a common base for all sam9x5 SoCs (at91sam9x5.dtsi)
- several optional peripheral definitions which will be included by specific
sam9x5 SoCs (at91sam9x5_'periph name'.dtsi)
This provides a better representation of the real hardware (drop unneeded
dt nodes) and avoids future peripheral id conflict (lcdc and isi both use
peripheral id 25).
Quoted 5 lines
I really don't like this
the mapping is soc specific (here familly) so I does not see any advantage
except move files so NO for me
Let me explain in detail why I did that.
This separation was part of the "at91 common clk" series and was here to avoid the
definition of unavailable clocks or definition of clocks with the same id (which may result
in bad clk registration).
If we keep all the definitions in one .dtsi file (even the one which are not really available),
I may need to add a new property to each peripheral (and system) clk node to specify the
availabilty of the clock (something similar to 'status="disabled"' in device nodes).
As explained to Thomas, I thought device tree was here to give a real description of the
hardware parts (in case of sam9x5.dtsi the description of the common parts of sam9x5 SoC
family).
If you define peripherals that are not present in a SoC (lets say macb0 for sam9g15) you break
this rule.
I'm not telling I have the right approach here, I'm just trying to understand what should be done and
what should not.
Finally, I'd like to point that the memory footprint of the dtb file generated after this patch has been
applied is bit smaller (even if it won't make a real difference):

Quoted 7 lines

with this patch:
15937 arch/arm/boot/dts/at91-ariag25.dtb
15860 arch/arm/boot/dts/at91sam9g15ek.dtb
16905 arch/arm/boot/dts/at91sam9g25ek.dtb
16473 arch/arm/boot/dts/at91sam9g35ek.dtb
17341 arch/arm/boot/dts/at91sam9x25ek.dtb

This one is bigger because usart3 periph node was not defined in sam9x5.dtsi and is defined
in sam9x5_usart3.dtsi.

Quoted 10 lines

16473 arch/arm/boot/dts/at91sam9x35ek.dtb
without this patch:
16077 arch/arm/boot/dts/at91-ariag25.dtb
16824 arch/arm/boot/dts/at91sam9g15ek.dtb
16849 arch/arm/boot/dts/at91sam9g25ek.dtb
16849 arch/arm/boot/dts/at91sam9g35ek.dtb
15017 arch/arm/boot/dts/at91sam9m10g45ek.dtb

sam9m10g45ek is not part of the sam9x5 family

Quoted 439 lines

17145 arch/arm/boot/dts/at91sam9x25ek.dtb
16849 arch/arm/boot/dts/at91sam9x35ek.dtb
Best Regards,
Boris
Quoted 430 lines
Best Regards,
J.
Quoted 428 lines
Signed-off-by Boris BREZILLON <[email protected]>
---
  arch/arm/boot/dts/at91sam9g25.dtsi       |    2 +
  arch/arm/boot/dts/at91sam9g35.dtsi       |    1 +
  arch/arm/boot/dts/at91sam9x25.dtsi       |   24 ++---------
  arch/arm/boot/dts/at91sam9x35.dtsi       |    1 +
  arch/arm/boot/dts/at91sam9x5.dtsi        |   67 
------------------------------
  arch/arm/boot/dts/at91sam9x5_macb0.dtsi  |   56 
+++++++++++++++++++++++++
  arch/arm/boot/dts/at91sam9x5_macb1.dtsi  |   44 ++++++++++++++++++++
  arch/arm/boot/dts/at91sam9x5_usart3.dtsi |   51 
+++++++++++++++++++++++
  8 files changed, 158 insertions(+), 88 deletions(-)
create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi
arch/arm/boot/dts/at91sam9g25.dtsi +2 -0
index b4ec6fe..17b8799 100644
@@ -7,6 +7,8 @@
   */
    #include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
    / {
      model = "Atmel AT91SAM9G25 SoC";
arch/arm/boot/dts/at91sam9g35.dtsi +1 -0
index bebf9f5..e35c2fc 100644
@@ -7,6 +7,7 @@
   */
    #include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
    / {
      model = "Atmel AT91SAM9G35 SoC";
arch/arm/boot/dts/at91sam9x25.dtsi +3 -5
index 49e94ab..c255421 100644
@@ -7,6 +7,9 @@
   */
    #include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_macb1.dtsi"
    / {
      model = "Atmel AT91SAM9X25 SoC";
@@ -22,27 +25,6 @@
                         0x80000000 0xfffd0000 0xb83fffff  /* pioC */
                         0x003fffff 0x003f8000 0x00000000  /* pioD */
                        >;
-
-                macb1 {
-                    pinctrl_macb1_rmii: macb1_rmii-0 {
-                        atmel,pins =
-                            <AT91_PIOC 16 AT91_PERIPH_B 
AT91_PINCTRL_NONE /* PC16 periph B */
- AT91_PIOC 18 AT91_PERIPH_B
AT91_PINCTRL_NONE /* PC18 periph B */
- AT91_PIOC 19 AT91_PERIPH_B
AT91_PINCTRL_NONE /* PC19 periph B */
- AT91_PIOC 20 AT91_PERIPH_B
AT91_PINCTRL_NONE /* PC20 periph B */
- AT91_PIOC 21 AT91_PERIPH_B
AT91_PINCTRL_NONE /* PC21 periph B */
- AT91_PIOC 27 AT91_PERIPH_B
AT91_PINCTRL_NONE /* PC27 periph B */
- AT91_PIOC 28 AT91_PERIPH_B
AT91_PINCTRL_NONE /* PC28 periph B */
- AT91_PIOC 29 AT91_PERIPH_B
AT91_PINCTRL_NONE /* PC29 periph B */
- AT91_PIOC 30 AT91_PERIPH_B
AT91_PINCTRL_NONE /* PC30 periph B */
- AT91_PIOC 31 AT91_PERIPH_B
AT91_PINCTRL_NONE>; /* PC31 periph B */
arch/arm/boot/dts/at91sam9x25.dtsi +0 -7
-                    };
-                };
-            };
-
-            macb1: ethernet at f8030000 {
-                pinctrl-names = "default";
-                pinctrl-0 = <&pinctrl_macb1_rmii>;
              };
          };
      };
arch/arm/boot/dts/at91sam9x35.dtsi +1 -0
index 1a3d525..8eac66c 100644
@@ -7,6 +7,7 @@
   */
    #include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
    / {
      model = "Atmel AT91SAM9X35 SoC";
arch/arm/boot/dts/at91sam9x5.dtsi +0 -3
index 57d45f5..05f4c74 100644
@@ -206,29 +206,6 @@
                      };
                  };
  -                usart3 {
-                    pinctrl_usart3: usart3-0 {
-                        atmel,pins =
-                            <AT91_PIOC 22 AT91_PERIPH_B 
AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */
- AT91_PIOC 23 AT91_PERIPH_B
AT91_PINCTRL_NONE>; /* PC23 periph B */
arch/arm/boot/dts/at91sam9x5.dtsi +0 -5
-                    };
-
-                    pinctrl_usart3_rts: usart3_rts-0 {
-                        atmel,pins =
-                            <AT91_PIOC 24 AT91_PERIPH_B 
AT91_PINCTRL_NONE>; /* PC24 periph B */
arch/arm/boot/dts/at91sam9x5.dtsi +0 -5
-                    };
-
-                    pinctrl_usart3_cts: usart3_cts-0 {
-                        atmel,pins =
-                            <AT91_PIOC 25 AT91_PERIPH_B 
AT91_PINCTRL_NONE>; /* PC25 periph B */
arch/arm/boot/dts/at91sam9x5.dtsi +0 -5
-                    };
-
-                    pinctrl_usart3_sck: usart3_sck-0 {
-                        atmel,pins =
-                            <AT91_PIOC 26 AT91_PERIPH_B 
AT91_PINCTRL_NONE>; /* PC26 periph B */
arch/arm/boot/dts/at91sam9x5.dtsi +0 -6
-                    };
-                };
-
                  uart0 {
                      pinctrl_uart0: uart0-0 {
                          atmel,pins =
@@ -277,34 +254,6 @@
                      };
                  };
  -                macb0 {
-                    pinctrl_macb0_rmii: macb0_rmii-0 {
-                        atmel,pins =
-                            <AT91_PIOB 0 AT91_PERIPH_A 
AT91_PINCTRL_NONE /* PB0 periph A */
- AT91_PIOB 1 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB1 periph A */
- AT91_PIOB 2 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB2 periph A */
- AT91_PIOB 3 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB3 periph A */
- AT91_PIOB 4 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB4 periph A */
- AT91_PIOB 5 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB5 periph A */
- AT91_PIOB 6 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB6 periph A */
- AT91_PIOB 7 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB7 periph A */
- AT91_PIOB 9 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB9 periph A */
- AT91_PIOB 10 AT91_PERIPH_A
AT91_PINCTRL_NONE>; /* PB10 periph A */
arch/arm/boot/dts/at91sam9x5.dtsi +0 -5
-                    };
-
-                    pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
-                        atmel,pins =
-                            <AT91_PIOB 8 AT91_PERIPH_A 
AT91_PINCTRL_NONE /* PB8 periph A */
- AT91_PIOB 11 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB11 periph A */
- AT91_PIOB 12 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB12 periph A */
- AT91_PIOB 13 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB13 periph A */
- AT91_PIOB 14 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB14 periph A */
- AT91_PIOB 15 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB15 periph A */
- AT91_PIOB 16 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB16 periph A */
- AT91_PIOB 17 AT91_PERIPH_A
AT91_PINCTRL_NONE>; /* PB17 periph A */
arch/arm/boot/dts/at91sam9x5.dtsi +0 -3
-                    };
-                };
-
                  mmc0 {
                      pinctrl_mmc0_slot0_clk_cmd_dat0: 
mmc0_slot0_clk_cmd_dat0-0 {
atmel,pins =
arch/arm/boot/dts/at91sam9x5.dtsi +0 ~~-15~~
@@ -605,22 +554,6 @@
                  status = "disabled";
              };
  -            macb0: ethernet at f802c000 {
-                compatible = "cdns,at32ap7000-macb", "cdns,macb";
-                reg = <0xf802c000 0x100>;
-                interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&pinctrl_macb0_rmii>;
-                status = "disabled";
-            };
-
-            macb1: ethernet at f8030000 {
-                compatible = "cdns,at32ap7000-macb", "cdns,macb";
-                reg = <0xf8030000 0x100>;
-                interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
-                status = "disabled";
-            };
-
              i2c0: i2c at f8010000 {
                  compatible = "atmel,at91sam9x5-i2c";
                  reg = <0xf8010000 0x100>;
arch/arm/boot/dts/at91sam9x5_macb0.dtsi new file +2 -0
new file mode 100644
index 0000000..55731ff
@@ -0,0 +1,56 @@
+/*
+ * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 
SoC with 1
+ * Ethernet interface.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
arch/arm/boot/dts/at91sam9x5_macb0.dtsi new file +12 -0
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+    ahb {
+        apb {
+            pinctrl at fffff400 {
+                macb0 {
+                    pinctrl_macb0_rmii: macb0_rmii-0 {
+                        atmel,pins =
+                            <AT91_PIOB 0 AT91_PERIPH_A 
AT91_PINCTRL_NONE /* PB0 periph A */
+ AT91_PIOB 1 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB1 periph A */
+ AT91_PIOB 2 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB2 periph A */
+ AT91_PIOB 3 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB3 periph A */
+ AT91_PIOB 4 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB4 periph A */
+ AT91_PIOB 5 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB5 periph A */
+ AT91_PIOB 6 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB6 periph A */
+ AT91_PIOB 7 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB7 periph A */
+ AT91_PIOB 9 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB9 periph A */
+ AT91_PIOB 10 AT91_PERIPH_A
AT91_PINCTRL_NONE>; /* PB10 periph A */
arch/arm/boot/dts/at91sam9x5_macb0.dtsi new file +5 -0
+                    };
+
+                    pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
+                        atmel,pins =
+                            <AT91_PIOB 8 AT91_PERIPH_A 
AT91_PINCTRL_NONE /* PB8 periph A */
+ AT91_PIOB 11 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB11 periph A */
+ AT91_PIOB 12 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB12 periph A */
+ AT91_PIOB 13 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB13 periph A */
+ AT91_PIOB 14 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB14 periph A */
+ AT91_PIOB 15 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB15 periph A */
+ AT91_PIOB 16 AT91_PERIPH_A
AT91_PINCTRL_NONE /* PB16 periph A */
+ AT91_PIOB 17 AT91_PERIPH_A
AT91_PINCTRL_NONE>; /* PB17 periph A */
arch/arm/boot/dts/at91sam9x5_macb0.dtsi new file +15 -0
+                    };
+                };
+            };
+
+            macb0: ethernet at f802c000 {
+                compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                reg = <0xf802c000 0x100>;
+                interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_macb0_rmii>;
+                status = "disabled";
+            };
+        };
+    };
+};
arch/arm/boot/dts/at91sam9x5_macb1.dtsi new file +2 -0
new file mode 100644
index 0000000..77425a6
@@ -0,0 +1,44 @@
+/*
+ * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 
SoC with 2
+ * Ethernet interfaces.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
arch/arm/boot/dts/at91sam9x5_macb1.dtsi new file +12 -0
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+    ahb {
+        apb {
+            pinctrl at fffff400 {
+                macb1 {
+                    pinctrl_macb1_rmii: macb1_rmii-0 {
+                        atmel,pins =
+                            <AT91_PIOC 16 AT91_PERIPH_B 
AT91_PINCTRL_NONE /* PC16 periph B */
+ AT91_PIOC 18 AT91_PERIPH_B
AT91_PINCTRL_NONE /* PC18 periph B */
+ AT91_PIOC 19 AT91_PERIPH_B
AT91_PINCTRL_NONE /* PC19 periph B */
+ AT91_PIOC 20 AT91_PERIPH_B
AT91_PINCTRL_NONE /* PC20 periph B */
+ AT91_PIOC 21 AT91_PERIPH_B
AT91_PINCTRL_NONE /* PC21 periph B */
+ AT91_PIOC 27 AT91_PERIPH_B
AT91_PINCTRL_NONE /* PC27 periph B */
+ AT91_PIOC 28 AT91_PERIPH_B
AT91_PINCTRL_NONE /* PC28 periph B */
+ AT91_PIOC 29 AT91_PERIPH_B
AT91_PINCTRL_NONE /* PC29 periph B */
+ AT91_PIOC 30 AT91_PERIPH_B
AT91_PINCTRL_NONE /* PC30 periph B */
+ AT91_PIOC 31 AT91_PERIPH_B
AT91_PINCTRL_NONE>; /* PC31 periph B */
arch/arm/boot/dts/at91sam9x5_macb1.dtsi new file +15 -0
+                    };
+                };
+            };
+
+            macb1: ethernet at f8030000 {
+                compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                reg = <0xf8030000 0x100>;
+                interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_macb1_rmii>;
+                status = "disabled";
+            };
+        };
+    };
+};
arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file +2 -0
new file mode 100644
index 0000000..5589579
@@ -0,0 +1,51 @@
+/*
+ * at91sam9x5_lcdc.dtsi - Device Tree Include file for AT91SAM9x5 
SoC with
+ * 4 USART.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file +12 -0
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+    ahb {
+        apb {
+            pinctrl at fffff400 {
+                usart3 {
+                    pinctrl_usart3: usart3-0 {
+                        atmel,pins =
+                            <AT91_PIOC 22 AT91_PERIPH_B 
AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */
+ AT91_PIOC 23 AT91_PERIPH_B
AT91_PINCTRL_NONE>; /* PC23 periph B */
arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file +5 -0
+                    };
+
+                    pinctrl_usart3_rts: usart3_rts-0 {
+                        atmel,pins =
+                            <AT91_PIOC 24 AT91_PERIPH_B 
AT91_PINCTRL_NONE>; /* PC24 periph B */
arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file +5 -0
+                    };
+
+                    pinctrl_usart3_cts: usart3_cts-0 {
+                        atmel,pins =
+                            <AT91_PIOC 25 AT91_PERIPH_B 
AT91_PINCTRL_NONE>; /* PC25 periph B */
arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file +5 -0
+                    };
+
+                    pinctrl_usart3_sck: usart3_sck-0 {
+                        atmel,pins =
+                            <AT91_PIOC 26 AT91_PERIPH_B 
AT91_PINCTRL_NONE>; /* PC26 periph B */
arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file +15 -0
+                    };
+                };
+            };
+
+            usart3: serial at f8028000 {
+                compatible = "atmel,at91sam9260-usart";
+                reg = <0xf8028000 0x200>;
+                interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_usart3>;
+                status = "disabled";
+            };
+        };
+    };
+};
Signature · 1 line
1.7.9.5

Nicolas Ferre

2013-08-19 16:23 UTC #9 lore raw

In reply to boris brezillon

On 08/08/2013 17:23, boris brezillon :

Quoted 18 lines

Hello Jean-Christophe,
Quoted 6 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 5 lines · Boris BREZILLON
This patch splits the sam9x5 peripheral definitions into:
- a common base for all sam9x5 SoCs (at91sam9x5.dtsi)
- several optional peripheral definitions which will be included by specific
    sam9x5 SoCs (at91sam9x5_'periph name'.dtsi)
Quoted 7 lines
Quoted 3 lines
This provides a better representation of the real hardware (drop unneeded dt nodes) and avoids future peripheral id conflict (lcdc and isi both use peripheral id 25).
I really don't like this
the mapping is soc specific (here familly) so I does not see any advantage except move files so NO for me
Let me explain in detail why I did that.

Quoted 11 lines

This separation was part of the "at91 common clk" series and was here to avoid the
definition of unavailable clocks or definition of clocks with the same id (which may result
in bad clk registration).
If we keep all the definitions in one .dtsi file (even the one which are not really available),
I may need to add a new property to each peripheral (and system) clk node to specify the
availabilty of the clock (something similar to 'status="disabled"' in device nodes).

This is indeed a pretty good argument.
I do think that we have to ask Mike Turquette to see if he already has encountered such a case.

I must say that I was not in favor for this split because of readability and dts/dtsi file organization (you know, the usual question: where the hell this peripheral property is finally setup?).

But, if we really have to implement a new kind of property to tell if a clock is actually present or not, I am in favor for reconsidering this solution as it seems quite simple and self-explanatory...

Quoted 8 lines

As explained to Thomas, I thought device tree was here to give a real description of the
hardware parts (in case of sam9x5.dtsi the description of the common parts of sam9x5 SoC
family).
If you define peripherals that are not present in a SoC (lets say macb0 for sam9g15) you break
this rule.

Well, on the other hand, the status says "disabled", so we can imagine that it has been disabled, from its birth, in hardware...

Quoted 19 lines

I'm not telling I have the right approach here, I'm just trying to understand what should be done and
what should not.
Finally, I'd like to point that the memory footprint of the dtb file generated after this patch has been
applied is bit smaller (even if it won't make a real difference):
with this patch:
15937 arch/arm/boot/dts/at91-ariag25.dtb
15860 arch/arm/boot/dts/at91sam9g15ek.dtb
16905 arch/arm/boot/dts/at91sam9g25ek.dtb
16473 arch/arm/boot/dts/at91sam9g35ek.dtb
17341 arch/arm/boot/dts/at91sam9x25ek.dtb
16473 arch/arm/boot/dts/at91sam9x35ek.dtb
without this patch:

Quoted 7 lines

16077 arch/arm/boot/dts/at91-ariag25.dtb
16824 arch/arm/boot/dts/at91sam9g15ek.dtb
16849 arch/arm/boot/dts/at91sam9g25ek.dtb
16849 arch/arm/boot/dts/at91sam9g35ek.dtb
15017 arch/arm/boot/dts/at91sam9m10g45ek.dtb
17145 arch/arm/boot/dts/at91sam9x25ek.dtb
16849 arch/arm/boot/dts/at91sam9x35ek.dtb

okay, but difference in size are not impressive. But it is true that:
- it can grow a little if we switch LCD to full DT
- each bit saved can have an influence on boot time
but it will not be a decisive factor.

Quoted 362 lines

Quoted 360 lines

Best Regards,
J.

Quoted 358 lines

Signed-off-by Boris BREZILLON <[email protected]>

---
   arch/arm/boot/dts/at91sam9g25.dtsi       |    2 +
   arch/arm/boot/dts/at91sam9g35.dtsi       |    1 +
   arch/arm/boot/dts/at91sam9x25.dtsi       |   24 ++---------
   arch/arm/boot/dts/at91sam9x35.dtsi       |    1 +
   arch/arm/boot/dts/at91sam9x5.dtsi        |   67 ------------------------------
   arch/arm/boot/dts/at91sam9x5_macb0.dtsi  |   56 +++++++++++++++++++++++++
   arch/arm/boot/dts/at91sam9x5_macb1.dtsi  |   44 ++++++++++++++++++++
   arch/arm/boot/dts/at91sam9x5_usart3.dtsi |   51 +++++++++++++++++++++++
   8 files changed, 158 insertions(+), 88 deletions(-)

create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi

arch/arm/boot/dts/at91sam9g25.dtsi +2 -0

index b4ec6fe..17b8799 100644
@@ -7,6 +7,8 @@
    */
 
   #include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
   / {
   	model = "Atmel AT91SAM9G25 SoC";

arch/arm/boot/dts/at91sam9g35.dtsi +1 -0

index bebf9f5..e35c2fc 100644
@@ -7,6 +7,7 @@
    */
 
   #include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
   / {
   	model = "Atmel AT91SAM9G35 SoC";

arch/arm/boot/dts/at91sam9x25.dtsi +3 ~~-21~~

index 49e94ab..c255421 100644
@@ -7,6 +7,9 @@
    */
 
   #include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_macb1.dtsi"
 
   / {
   	model = "Atmel AT91SAM9X25 SoC";

@@ -22,27 +25,6 @@
   				       0x80000000 0xfffd0000 0xb83fffff  /* pioC */
   				       0x003fffff 0x003f8000 0x00000000  /* pioD */
   				      >;
-
-				macb1 {
-					pinctrl_macb1_rmii: macb1_rmii-0 {
-						atmel,pins =
-							<AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC16 periph B */
-							 AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC18 periph B */
-							 AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC19 periph B */
-							 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC20 periph B */
-							 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC21 periph B */
-							 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC27 periph B */
-							 AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC28 periph B */
-							 AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC29 periph B */
-							 AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC30 periph B */
-							 AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC31 periph B */
-					};
-				};
-			};
-
-			macb1: ethernet@f8030000 {
-				pinctrl-names = "default";
-				pinctrl-0 = <&pinctrl_macb1_rmii>;
   			};
   		};
   	};

arch/arm/boot/dts/at91sam9x35.dtsi +1 -0

index 1a3d525..8eac66c 100644
@@ -7,6 +7,7 @@
    */
 
   #include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
   / {
   	model = "Atmel AT91SAM9X35 SoC";

arch/arm/boot/dts/at91sam9x5.dtsi +0 ~~-67~~

index 57d45f5..05f4c74 100644
@@ -206,29 +206,6 @@
   					};
   				};
 
-				usart3 {
-					pinctrl_usart3: usart3-0 {
-						atmel,pins =
-							<AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PC22 periph B with pullup */
-							 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC23 periph B */
-					};
-
-					pinctrl_usart3_rts: usart3_rts-0 {
-						atmel,pins =
-							<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC24 periph B */
-					};
-
-					pinctrl_usart3_cts: usart3_cts-0 {
-						atmel,pins =
-							<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC25 periph B */
-					};
-
-					pinctrl_usart3_sck: usart3_sck-0 {
-						atmel,pins =
-							<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC26 periph B */
-					};
-				};
-
   				uart0 {
   					pinctrl_uart0: uart0-0 {
   						atmel,pins =

@@ -277,34 +254,6 @@
   					};
   				};
 
-				macb0 {
-					pinctrl_macb0_rmii: macb0_rmii-0 {
-						atmel,pins =
-							<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A */
-							 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A */
-							 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB2 periph A */
-							 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB3 periph A */
-							 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB4 periph A */
-							 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB5 periph A */
-							 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB6 periph A */
-							 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB7 periph A */
-							 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB9 periph A */
-							 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB10 periph A */
-					};
-
-					pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
-						atmel,pins =
-							<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB8 periph A */
-							 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB11 periph A */
-							 AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB12 periph A */
-							 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB13 periph A */
-							 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB14 periph A */
-							 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB15 periph A */
-							 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB16 periph A */
-							 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB17 periph A */
-					};
-				};
-
   				mmc0 {
   					pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
   						atmel,pins =

@@ -605,22 +554,6 @@
   				status = "disabled";
   			};
 
-			macb0: ethernet@f802c000 {
-				compatible = "cdns,at32ap7000-macb", "cdns,macb";
-				reg = <0xf802c000 0x100>;
-				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
-				pinctrl-names = "default";
-				pinctrl-0 = <&pinctrl_macb0_rmii>;
-				status = "disabled";
-			};
-
-			macb1: ethernet@f8030000 {
-				compatible = "cdns,at32ap7000-macb", "cdns,macb";
-				reg = <0xf8030000 0x100>;
-				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
-				status = "disabled";
-			};
-
   			i2c0: i2c@f8010000 {
   				compatible = "atmel,at91sam9x5-i2c";
   				reg = <0xf8010000 0x100>;

arch/arm/boot/dts/at91sam9x5_macb0.dtsi new file +56 -0

new file mode 100644
index 0000000..55731ff
@@ -0,0 +1,56 @@
+/*
+ * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
+ * Ethernet interface.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	ahb {
+		apb {
+			pinctrl@fffff400 {
+				macb0 {
+					pinctrl_macb0_rmii: macb0_rmii-0 {
+						atmel,pins =
+							<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A */
+							 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A */
+							 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB2 periph A */
+							 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB3 periph A */
+							 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB4 periph A */
+							 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB5 periph A */
+							 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB6 periph A */
+							 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB7 periph A */
+							 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB9 periph A */
+							 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB10 periph A */
+					};
+
+					pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
+						atmel,pins =
+							<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB8 periph A */
+							 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB11 periph A */
+							 AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB12 periph A */
+							 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB13 periph A */
+							 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB14 periph A */
+							 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB15 periph A */
+							 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB16 periph A */
+							 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB17 periph A */
+					};
+				};
+			};
+
+			macb0: ethernet@f802c000 {
+				compatible = "cdns,at32ap7000-macb", "cdns,macb";
+				reg = <0xf802c000 0x100>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_macb0_rmii>;
+				status = "disabled";
+			};
+		};
+	};
+};

arch/arm/boot/dts/at91sam9x5_macb1.dtsi new file +44 -0

new file mode 100644
index 0000000..77425a6
@@ -0,0 +1,44 @@
+/*
+ * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2
+ * Ethernet interfaces.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	ahb {
+		apb {
+			pinctrl@fffff400 {
+				macb1 {
+					pinctrl_macb1_rmii: macb1_rmii-0 {
+						atmel,pins =
+							<AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC16 periph B */
+							 AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC18 periph B */
+							 AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC19 periph B */
+							 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC20 periph B */
+							 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC21 periph B */
+							 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC27 periph B */
+							 AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC28 periph B */
+							 AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC29 periph B */
+							 AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC30 periph B */
+							 AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC31 periph B */
+					};
+				};
+			};
+
+			macb1: ethernet@f8030000 {
+				compatible = "cdns,at32ap7000-macb", "cdns,macb";
+				reg = <0xf8030000 0x100>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_macb1_rmii>;
+				status = "disabled";
+			};
+		};
+	};
+};

arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file +51 -1

new file mode 100644
index 0000000..5589579
@@ -0,0 +1,51 @@
+/*
+ * at91sam9x5_lcdc.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * 4 USART.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	ahb {
+		apb {
+			pinctrl@fffff400 {
+				usart3 {
+					pinctrl_usart3: usart3-0 {
+						atmel,pins =
+							<AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PC22 periph B with pullup */
+							 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;		/* PC23 periph B */
+					};
+
+					pinctrl_usart3_rts: usart3_rts-0 {
+						atmel,pins =
+							<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;		/* PC24 periph B */
+					};
+
+					pinctrl_usart3_cts: usart3_cts-0 {
+						atmel,pins =
+							<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;		/* PC25 periph B */
+					};
+
+					pinctrl_usart3_sck: usart3_sck-0 {
+						atmel,pins =
+							<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;		/* PC26 periph B */
+					};
+				};
+			};
+
+			usart3: serial@f8028000 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xf8028000 0x200>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_usart3>;
+				status = "disabled";
+			};
+		};
+	};
+};
--

1.7.9.5

Signature · 1 line

Nicolas Ferre

Mike Turquette

2013-08-19 22:37 UTC #10 lore raw

Quoting Nicolas Ferre (2013-08-19 09:23:46)

Quoted 31 lines

On 08/08/2013 17:23, boris brezillon :
Quoted 18 lines
Hello Jean-Christophe,
Quoted 6 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 5 lines · Boris BREZILLON
This patch splits the sam9x5 peripheral definitions into:
- a common base for all sam9x5 SoCs (at91sam9x5.dtsi)
- several optional peripheral definitions which will be included by specific
    sam9x5 SoCs (at91sam9x5_'periph name'.dtsi)
Quoted 7 lines
Quoted 3 lines
This provides a better representation of the real hardware (drop unneeded dt nodes) and avoids future peripheral id conflict (lcdc and isi both use peripheral id 25).
I really don't like this
the mapping is soc specific (here familly) so I does not see any advantage except move files so NO for me
Let me explain in detail why I did that.
Quoted 11 lines
This separation was part of the "at91 common clk" series and was here to avoid the
definition of unavailable clocks or definition of clocks with the same id (which may result
in bad clk registration).
If we keep all the definitions in one .dtsi file (even the one which are not really available),
I may need to add a new property to each peripheral (and system) clk node to specify the
availabilty of the clock (something similar to 'status="disabled"' in device nodes).

Quoted 3 lines

This is indeed a pretty good argument.
I do think that we have to ask Mike Turquette to see if he already has encountered such a case.

It is correct to place chip-specific clocks into a chip-specific dts. Having clocks marked as "disabled" in a big dtsi is not the right way to go.

Regarding naming conflicts, is your issue with string name collisions during calls to __clk_lookup?

Thanks,
Mike

Quoted 420 lines

I must say that I was not in favor for this split because of readability and dts/dtsi file organization (you know, the usual question: where the hell this peripheral property is finally setup?).

Quoted 8 lines

As explained to Thomas, I thought device tree was here to give a real description of the
hardware parts (in case of sam9x5.dtsi the description of the common parts of sam9x5 SoC
family).
If you define peripherals that are not present in a SoC (lets say macb0 for sam9g15) you break
this rule.

Well, on the other hand, the status says "disabled", so we can imagine that it has been disabled, from its birth, in hardware...

Quoted 19 lines

I'm not telling I have the right approach here, I'm just trying to understand what should be done and
what should not.
Finally, I'd like to point that the memory footprint of the dtb file generated after this patch has been
applied is bit smaller (even if it won't make a real difference):
with this patch:
15937 arch/arm/boot/dts/at91-ariag25.dtb
15860 arch/arm/boot/dts/at91sam9g15ek.dtb
16905 arch/arm/boot/dts/at91sam9g25ek.dtb
16473 arch/arm/boot/dts/at91sam9g35ek.dtb
17341 arch/arm/boot/dts/at91sam9x25ek.dtb
16473 arch/arm/boot/dts/at91sam9x35ek.dtb
without this patch:

Quoted 7 lines

16077 arch/arm/boot/dts/at91-ariag25.dtb
16824 arch/arm/boot/dts/at91sam9g15ek.dtb
16849 arch/arm/boot/dts/at91sam9g25ek.dtb
16849 arch/arm/boot/dts/at91sam9g35ek.dtb
15017 arch/arm/boot/dts/at91sam9m10g45ek.dtb
17145 arch/arm/boot/dts/at91sam9x25ek.dtb
16849 arch/arm/boot/dts/at91sam9x35ek.dtb

Quoted 362 lines

Quoted 360 lines

Best Regards,
J.

Quoted 358 lines

Signed-off-by Boris BREZILLON <[email protected]>

---
   arch/arm/boot/dts/at91sam9g25.dtsi       |    2 +
   arch/arm/boot/dts/at91sam9g35.dtsi       |    1 +
   arch/arm/boot/dts/at91sam9x25.dtsi       |   24 ++---------
   arch/arm/boot/dts/at91sam9x35.dtsi       |    1 +
   arch/arm/boot/dts/at91sam9x5.dtsi        |   67 ------------------------------
   arch/arm/boot/dts/at91sam9x5_macb0.dtsi  |   56 +++++++++++++++++++++++++
   arch/arm/boot/dts/at91sam9x5_macb1.dtsi  |   44 ++++++++++++++++++++
   arch/arm/boot/dts/at91sam9x5_usart3.dtsi |   51 +++++++++++++++++++++++
   8 files changed, 158 insertions(+), 88 deletions(-)

create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi

arch/arm/boot/dts/at91sam9g25.dtsi +2 -0

index b4ec6fe..17b8799 100644
@@ -7,6 +7,8 @@
    */
 
   #include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
   / {
    model = "Atmel AT91SAM9G25 SoC";

arch/arm/boot/dts/at91sam9g35.dtsi +1 -0

index bebf9f5..e35c2fc 100644
@@ -7,6 +7,7 @@
    */
 
   #include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
   / {
    model = "Atmel AT91SAM9G35 SoC";

arch/arm/boot/dts/at91sam9x25.dtsi +3 ~~-21~~

index 49e94ab..c255421 100644
@@ -7,6 +7,9 @@
    */
 
   #include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_macb1.dtsi"
 
   / {
    model = "Atmel AT91SAM9X25 SoC";

@@ -22,27 +25,6 @@
                                   0x80000000 0xfffd0000 0xb83fffff  /* pioC */
                                   0x003fffff 0x003f8000 0x00000000  /* pioD */
                                  >;
-
-                           macb1 {
-                                   pinctrl_macb1_rmii: macb1_rmii-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC16 periph B */
-                                                    AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC18 periph B */
-                                                    AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC19 periph B */
-                                                    AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC20 periph B */
-                                                    AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC21 periph B */
-                                                    AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC27 periph B */
-                                                    AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC28 periph B */
-                                                    AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC29 periph B */
-                                                    AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC30 periph B */
-                                                    AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
-                                   };
-                           };
-                   };
-
-                   macb1: ethernet at f8030000 {
-                           pinctrl-names = "default";
-                           pinctrl-0 = <&pinctrl_macb1_rmii>;
                    };
            };
    };

arch/arm/boot/dts/at91sam9x35.dtsi +1 -0

index 1a3d525..8eac66c 100644
@@ -7,6 +7,7 @@
    */
 
   #include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
   / {
    model = "Atmel AT91SAM9X35 SoC";

arch/arm/boot/dts/at91sam9x5.dtsi +0 ~~-67~~

index 57d45f5..05f4c74 100644
@@ -206,29 +206,6 @@
                                    };
                            };
 
-                           usart3 {
-                                   pinctrl_usart3: usart3-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PC22 periph B with pullup */
-                                                    AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
-                                   };
-
-                                   pinctrl_usart3_rts: usart3_rts-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
-                                   };
-
-                                   pinctrl_usart3_cts: usart3_cts-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
-                                   };
-
-                                   pinctrl_usart3_sck: usart3_sck-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
-                                   };
-                           };
-
                            uart0 {
                                    pinctrl_uart0: uart0-0 {
                                            atmel,pins =

@@ -277,34 +254,6 @@
                                    };
                            };
 
-                           macb0 {
-                                   pinctrl_macb0_rmii: macb0_rmii-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A */
-                                                    AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A */
-                                                    AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB2 periph A */
-                                                    AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB3 periph A */
-                                                    AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
-                                                    AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB5 periph A */
-                                                    AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A */
-                                                    AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB7 periph A */
-                                                    AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A */
-                                                    AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
-                                   };
-
-                                   pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB8 periph A */
-                                                    AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB11 periph A */
-                                                    AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB12 periph A */
-                                                    AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB13 periph A */
-                                                    AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB14 periph A */
-                                                    AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB15 periph A */
-                                                    AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB16 periph A */
-                                                    AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
-                                   };
-                           };
-
                            mmc0 {
                                    pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
                                            atmel,pins =

@@ -605,22 +554,6 @@
                            status = "disabled";
                    };
 
-                   macb0: ethernet at f802c000 {
-                           compatible = "cdns,at32ap7000-macb", "cdns,macb";
-                           reg = <0xf802c000 0x100>;
-                           interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
-                           pinctrl-names = "default";
-                           pinctrl-0 = <&pinctrl_macb0_rmii>;
-                           status = "disabled";
-                   };
-
-                   macb1: ethernet at f8030000 {
-                           compatible = "cdns,at32ap7000-macb", "cdns,macb";
-                           reg = <0xf8030000 0x100>;
-                           interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
-                           status = "disabled";
-                   };
-
                    i2c0: i2c at f8010000 {
                            compatible = "atmel,at91sam9x5-i2c";
                            reg = <0xf8010000 0x100>;

arch/arm/boot/dts/at91sam9x5_macb0.dtsi new file +56 -0

new file mode 100644
index 0000000..55731ff
@@ -0,0 +1,56 @@
+/*
+ * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
+ * Ethernet interface.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+   ahb {
+           apb {
+                   pinctrl at fffff400 {
+                           macb0 {
+                                   pinctrl_macb0_rmii: macb0_rmii-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A */
+                                                    AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A */
+                                                    AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB2 periph A */
+                                                    AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB3 periph A */
+                                                    AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
+                                                    AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB5 periph A */
+                                                    AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A */
+                                                    AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB7 periph A */
+                                                    AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A */
+                                                    AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
+                                   };
+
+                                   pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB8 periph A */
+                                                    AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB11 periph A */
+                                                    AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB12 periph A */
+                                                    AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB13 periph A */
+                                                    AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB14 periph A */
+                                                    AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB15 periph A */
+                                                    AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB16 periph A */
+                                                    AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
+                                   };
+                           };
+                   };
+
+                   macb0: ethernet at f802c000 {
+                           compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                           reg = <0xf802c000 0x100>;
+                           interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
+                           pinctrl-names = "default";
+                           pinctrl-0 = <&pinctrl_macb0_rmii>;
+                           status = "disabled";
+                   };
+           };
+   };
+};

arch/arm/boot/dts/at91sam9x5_macb1.dtsi new file +44 -0

new file mode 100644
index 0000000..77425a6
@@ -0,0 +1,44 @@
+/*
+ * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2
+ * Ethernet interfaces.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+   ahb {
+           apb {
+                   pinctrl at fffff400 {
+                           macb1 {
+                                   pinctrl_macb1_rmii: macb1_rmii-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC16 periph B */
+                                                    AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC18 periph B */
+                                                    AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC19 periph B */
+                                                    AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC20 periph B */
+                                                    AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC21 periph B */
+                                                    AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC27 periph B */
+                                                    AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC28 periph B */
+                                                    AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC29 periph B */
+                                                    AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC30 periph B */
+                                                    AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
+                                   };
+                           };
+                   };
+
+                   macb1: ethernet at f8030000 {
+                           compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                           reg = <0xf8030000 0x100>;
+                           interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
+                           pinctrl-names = "default";
+                           pinctrl-0 = <&pinctrl_macb1_rmii>;
+                           status = "disabled";
+                   };
+           };
+   };
+};

arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file +51 -1

new file mode 100644
index 0000000..5589579
@@ -0,0 +1,51 @@
+/*
+ * at91sam9x5_lcdc.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * 4 USART.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+   ahb {
+           apb {
+                   pinctrl at fffff400 {
+                           usart3 {
+                                   pinctrl_usart3: usart3-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PC22 periph B with pullup */
+                                                    AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC23 periph B */
+                                   };
+
+                                   pinctrl_usart3_rts: usart3_rts-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC24 periph B */
+                                   };
+
+                                   pinctrl_usart3_cts: usart3_cts-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC25 periph B */
+                                   };
+
+                                   pinctrl_usart3_sck: usart3_sck-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC26 periph B */
+                                   };
+                           };
+                   };
+
+                   usart3: serial at f8028000 {
+                           compatible = "atmel,at91sam9260-usart";
+                           reg = <0xf8028000 0x200>;
+                           interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+                           pinctrl-names = "default";
+                           pinctrl-0 = <&pinctrl_usart3>;
+                           status = "disabled";
+                   };
+           };
+   };
+};
--

1.7.9.5

Signature · 1 line

Nicolas Ferre

[email protected]

author

2013-08-20 06:00 UTC #11 lore raw

Hello Mike,

Quoted 32 lines · Mike Turquette

Quoting Nicolas Ferre (2013-08-19 09:23:46)
Quoted 31 lines
On 08/08/2013 17:23, boris brezillon :
Quoted 29 lines
Hello Jean-Christophe,
Quoted 6 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 5 lines · Boris BREZILLON
This patch splits the sam9x5 peripheral definitions into:
- a common base for all sam9x5 SoCs (at91sam9x5.dtsi)
- several optional peripheral definitions which will be included by specific
    sam9x5 SoCs (at91sam9x5_'periph name'.dtsi)
Quoted 7 lines
Quoted 3 lines
This provides a better representation of the real hardware (drop unneeded dt nodes) and avoids future peripheral id conflict (lcdc and isi both use peripheral id 25).
I really don't like this
the mapping is soc specific (here familly) so I does not see any advantage except move files so NO for me
Let me explain in detail why I did that.
This separation was part of the "at91 common clk" series and was here to avoid the
definition of unavailable clocks or definition of clocks with the same id (which may result
in bad clk registration).
If we keep all the definitions in one .dtsi file (even the one which are not really available),
I may need to add a new property to each peripheral (and system) clk node to specify the
availabilty of the clock (something similar to 'status="disabled"' in device nodes).

Quoted 8 lines

Quoted 3 lines
This is indeed a pretty good argument.
I do think that we have to ask Mike Turquette to see if he already has encountered such a case.
It is correct to place chip-specific clocks into a chip-specific dts. Having clocks marked as "disabled" in a big dtsi is not the right way to go.

I agree. As I said earlier, I think unavailable peripherals (and associated clocks)
should not be part of the dts definition because it may lead to misinterpretation of
the real hardware parts.
There is a difference between unused IP block (defined with status="disabled") because
external I/Os are not connected on a specific board and unavailable IP block (IP block
not available on a given SoC).

This beeing said, I understand the readability concern, and I won't force this split if
we find a way to declare a clk as "unavailable" or "disabled"

Quoted 3 lines

Regarding naming conflicts, is your issue with string name collisions during calls to __clk_lookup?

No, there is no collision in clk names, because each optional clock has a unique name.
But there may be conflicts on clk ids (peripheral ids):

LCDC (LCD Controller) and ISI (Image Sensor Interface) peripherals have the same id (25)
in sam9x5 SoC family but are never both available in a given SoC.

If you declare LCDC clk before ISI clock, the former will always be returned when you
reference the ISI clk in ISI peripheral node (clocks=<&periph 25>).

This will work, as the method for enabling/disabling periph clk are the same for all clks.
But when you print the clk tree (using debugfs) you will see lcdc_clk with prepare/enable
count incremented and isi_clk always unused, even if the SoC does not have an LCDC block.

Moreover, isi_clk will be allocated for nothing, because it cannot be retrieved.

And what happens if an unavailable clock is referenced (I did not test that, but I guess
the is_enabled callback will always return false)?
This case should not happen if the dts is correctly defined, but still, I think unavailable
clocks should not be registered in the clk framework.

Please, feel free to share your thoughts.

Best Regards,

Boris

Quoted 423 lines

Thanks,
Mike

Quoted 420 lines

I must say that I was not in favor for this split because of readability and dts/dtsi file organization (you know, the usual question: where the hell this peripheral property is finally setup?).

Quoted 8 lines

As explained to Thomas, I thought device tree was here to give a real description of the
hardware parts (in case of sam9x5.dtsi the description of the common parts of sam9x5 SoC
family).
If you define peripherals that are not present in a SoC (lets say macb0 for sam9g15) you break
this rule.

Well, on the other hand, the status says "disabled", so we can imagine that it has been disabled, from its birth, in hardware...

Quoted 19 lines

I'm not telling I have the right approach here, I'm just trying to understand what should be done and
what should not.
Finally, I'd like to point that the memory footprint of the dtb file generated after this patch has been
applied is bit smaller (even if it won't make a real difference):
with this patch:
15937 arch/arm/boot/dts/at91-ariag25.dtb
15860 arch/arm/boot/dts/at91sam9g15ek.dtb
16905 arch/arm/boot/dts/at91sam9g25ek.dtb
16473 arch/arm/boot/dts/at91sam9g35ek.dtb
17341 arch/arm/boot/dts/at91sam9x25ek.dtb
16473 arch/arm/boot/dts/at91sam9x35ek.dtb
without this patch:

Quoted 7 lines

16077 arch/arm/boot/dts/at91-ariag25.dtb
16824 arch/arm/boot/dts/at91sam9g15ek.dtb
16849 arch/arm/boot/dts/at91sam9g25ek.dtb
16849 arch/arm/boot/dts/at91sam9g35ek.dtb
15017 arch/arm/boot/dts/at91sam9m10g45ek.dtb
17145 arch/arm/boot/dts/at91sam9x25ek.dtb
16849 arch/arm/boot/dts/at91sam9x35ek.dtb

Quoted 352 lines

Best Regards,
J.

Quoted 350 lines

Signed-off-by Boris BREZILLON <[email protected]>

---
   arch/arm/boot/dts/at91sam9g25.dtsi       |    2 +
   arch/arm/boot/dts/at91sam9g35.dtsi       |    1 +
   arch/arm/boot/dts/at91sam9x25.dtsi       |   24 ++---------
   arch/arm/boot/dts/at91sam9x35.dtsi       |    1 +
   arch/arm/boot/dts/at91sam9x5.dtsi        |   67 ------------------------------
   arch/arm/boot/dts/at91sam9x5_macb0.dtsi  |   56 +++++++++++++++++++++++++
   arch/arm/boot/dts/at91sam9x5_macb1.dtsi  |   44 ++++++++++++++++++++
   arch/arm/boot/dts/at91sam9x5_usart3.dtsi |   51 +++++++++++++++++++++++
   8 files changed, 158 insertions(+), 88 deletions(-)

create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi

arch/arm/boot/dts/at91sam9g25.dtsi +2 -0

index b4ec6fe..17b8799 100644
@@ -7,6 +7,8 @@
    */
 
   #include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
   / {
    model = "Atmel AT91SAM9G25 SoC";

arch/arm/boot/dts/at91sam9g35.dtsi +1 -0

index bebf9f5..e35c2fc 100644
@@ -7,6 +7,7 @@
    */
 
   #include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
   / {
    model = "Atmel AT91SAM9G35 SoC";

arch/arm/boot/dts/at91sam9x25.dtsi +3 ~~-21~~

index 49e94ab..c255421 100644
@@ -7,6 +7,9 @@
    */
 
   #include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_macb1.dtsi"
 
   / {
    model = "Atmel AT91SAM9X25 SoC";

@@ -22,27 +25,6 @@
                                   0x80000000 0xfffd0000 0xb83fffff  /* pioC */
                                   0x003fffff 0x003f8000 0x00000000  /* pioD */
                                  >;
-
-                           macb1 {
-                                   pinctrl_macb1_rmii: macb1_rmii-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC16 periph B */
-                                                    AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC18 periph B */
-                                                    AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC19 periph B */
-                                                    AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC20 periph B */
-                                                    AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC21 periph B */
-                                                    AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC27 periph B */
-                                                    AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC28 periph B */
-                                                    AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC29 periph B */
-                                                    AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC30 periph B */
-                                                    AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
-                                   };
-                           };
-                   };
-
-                   macb1: ethernet at f8030000 {
-                           pinctrl-names = "default";
-                           pinctrl-0 = <&pinctrl_macb1_rmii>;
                    };
            };
    };

arch/arm/boot/dts/at91sam9x35.dtsi +1 -0

index 1a3d525..8eac66c 100644
@@ -7,6 +7,7 @@
    */
 
   #include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
   / {
    model = "Atmel AT91SAM9X35 SoC";

arch/arm/boot/dts/at91sam9x5.dtsi +0 ~~-67~~

index 57d45f5..05f4c74 100644
@@ -206,29 +206,6 @@
                                    };
                            };
 
-                           usart3 {
-                                   pinctrl_usart3: usart3-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PC22 periph B with pullup */
-                                                    AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
-                                   };
-
-                                   pinctrl_usart3_rts: usart3_rts-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
-                                   };
-
-                                   pinctrl_usart3_cts: usart3_cts-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
-                                   };
-
-                                   pinctrl_usart3_sck: usart3_sck-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
-                                   };
-                           };
-
                            uart0 {
                                    pinctrl_uart0: uart0-0 {
                                            atmel,pins =

@@ -277,34 +254,6 @@
                                    };
                            };
 
-                           macb0 {
-                                   pinctrl_macb0_rmii: macb0_rmii-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A */
-                                                    AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A */
-                                                    AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB2 periph A */
-                                                    AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB3 periph A */
-                                                    AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
-                                                    AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB5 periph A */
-                                                    AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A */
-                                                    AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB7 periph A */
-                                                    AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A */
-                                                    AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
-                                   };
-
-                                   pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB8 periph A */
-                                                    AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB11 periph A */
-                                                    AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB12 periph A */
-                                                    AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB13 periph A */
-                                                    AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB14 periph A */
-                                                    AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB15 periph A */
-                                                    AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB16 periph A */
-                                                    AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
-                                   };
-                           };
-
                            mmc0 {
                                    pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
                                            atmel,pins =

@@ -605,22 +554,6 @@
                            status = "disabled";
                    };
 
-                   macb0: ethernet at f802c000 {
-                           compatible = "cdns,at32ap7000-macb", "cdns,macb";
-                           reg = <0xf802c000 0x100>;
-                           interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
-                           pinctrl-names = "default";
-                           pinctrl-0 = <&pinctrl_macb0_rmii>;
-                           status = "disabled";
-                   };
-
-                   macb1: ethernet at f8030000 {
-                           compatible = "cdns,at32ap7000-macb", "cdns,macb";
-                           reg = <0xf8030000 0x100>;
-                           interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
-                           status = "disabled";
-                   };
-
                    i2c0: i2c at f8010000 {
                            compatible = "atmel,at91sam9x5-i2c";
                            reg = <0xf8010000 0x100>;

arch/arm/boot/dts/at91sam9x5_macb0.dtsi new file +56 -0

new file mode 100644
index 0000000..55731ff
@@ -0,0 +1,56 @@
+/*
+ * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
+ * Ethernet interface.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+   ahb {
+           apb {
+                   pinctrl at fffff400 {
+                           macb0 {
+                                   pinctrl_macb0_rmii: macb0_rmii-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A */
+                                                    AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A */
+                                                    AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB2 periph A */
+                                                    AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB3 periph A */
+                                                    AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
+                                                    AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB5 periph A */
+                                                    AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A */
+                                                    AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB7 periph A */
+                                                    AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A */
+                                                    AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
+                                   };
+
+                                   pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB8 periph A */
+                                                    AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB11 periph A */
+                                                    AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB12 periph A */
+                                                    AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB13 periph A */
+                                                    AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB14 periph A */
+                                                    AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB15 periph A */
+                                                    AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB16 periph A */
+                                                    AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
+                                   };
+                           };
+                   };
+
+                   macb0: ethernet at f802c000 {
+                           compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                           reg = <0xf802c000 0x100>;
+                           interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
+                           pinctrl-names = "default";
+                           pinctrl-0 = <&pinctrl_macb0_rmii>;
+                           status = "disabled";
+                   };
+           };
+   };
+};

arch/arm/boot/dts/at91sam9x5_macb1.dtsi new file +44 -0

new file mode 100644
index 0000000..77425a6
@@ -0,0 +1,44 @@
+/*
+ * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2
+ * Ethernet interfaces.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+   ahb {
+           apb {
+                   pinctrl at fffff400 {
+                           macb1 {
+                                   pinctrl_macb1_rmii: macb1_rmii-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC16 periph B */
+                                                    AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC18 periph B */
+                                                    AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC19 periph B */
+                                                    AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC20 periph B */
+                                                    AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC21 periph B */
+                                                    AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC27 periph B */
+                                                    AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC28 periph B */
+                                                    AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC29 periph B */
+                                                    AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC30 periph B */
+                                                    AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
+                                   };
+                           };
+                   };
+
+                   macb1: ethernet at f8030000 {
+                           compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                           reg = <0xf8030000 0x100>;
+                           interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
+                           pinctrl-names = "default";
+                           pinctrl-0 = <&pinctrl_macb1_rmii>;
+                           status = "disabled";
+                   };
+           };
+   };
+};

arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file +46 -0

new file mode 100644
index 0000000..5589579
@@ -0,0 +1,51 @@
+/*
+ * at91sam9x5_lcdc.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * 4 USART.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+   ahb {
+           apb {
+                   pinctrl at fffff400 {
+                           usart3 {
+                                   pinctrl_usart3: usart3-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PC22 periph B with pullup */
+                                                    AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC23 periph B */
+                                   };
+
+                                   pinctrl_usart3_rts: usart3_rts-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC24 periph B */
+                                   };
+
+                                   pinctrl_usart3_cts: usart3_cts-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC25 periph B */
+                                   };
+
+                                   pinctrl_usart3_sck: usart3_sck-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC26 periph B */
+                                   };
+                           };
+                   };
+
+                   usart3: serial at f8028000 {
+                           compatible = "atmel,at91sam9260-usart";
+                           reg = <0xf8028000 0x200>;
+                           interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+                           pinctrl-names = "default";
+                           pinctrl-0 = <&pinctrl_usart3>;

Quoted 10 lines

Quoted 8 lines
Quoted 8 lines
arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file +5 -1
+                           status = "disabled";
+                   };
+           };
+   };
+};
--
1.7.9.5

--
Nicolas Ferre

Mike Turquette

2013-08-20 22:36 UTC #12 lore raw

PATCH 1/1 ARM: at91/dt: split sam9x5 peripheral definitions

Quoting b.brezillon at overkiz.com (2013-08-19 23:00:32)

Quoted 56 lines

Hello Mike,
Quoted 32 lines · Mike Turquette
Quoting Nicolas Ferre (2013-08-19 09:23:46)
Quoted 31 lines
On 08/08/2013 17:23, boris brezillon :
Quoted 29 lines
Hello Jean-Christophe,
Quoted 6 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 5 lines · Boris BREZILLON
This patch splits the sam9x5 peripheral definitions into:
- a common base for all sam9x5 SoCs (at91sam9x5.dtsi)
- several optional peripheral definitions which will be included by specific
    sam9x5 SoCs (at91sam9x5_'periph name'.dtsi)
Quoted 7 lines
Quoted 3 lines
This provides a better representation of the real hardware (drop unneeded dt nodes) and avoids future peripheral id conflict (lcdc and isi both use peripheral id 25).
I really don't like this
the mapping is soc specific (here familly) so I does not see any advantage except move files so NO for me
Let me explain in detail why I did that.
This separation was part of the "at91 common clk" series and was here to avoid the
definition of unavailable clocks or definition of clocks with the same id (which may result
in bad clk registration).
If we keep all the definitions in one .dtsi file (even the one which are not really available),
I may need to add a new property to each peripheral (and system) clk node to specify the
availabilty of the clock (something similar to 'status="disabled"' in device nodes).
Quoted 8 lines
Quoted 3 lines
This is indeed a pretty good argument.
I do think that we have to ask Mike Turquette to see if he already has encountered such a case.
It is correct to place chip-specific clocks into a chip-specific dts. Having clocks marked as "disabled" in a big dtsi is not the right way to go.
I agree. As I said earlier, I think unavailable peripherals (and associated clocks)
should not be part of the dts definition because it may lead to misinterpretation of
the real hardware parts.
There is a difference between unused IP block (defined with status="disabled") because
external I/Os are not connected on a specific board and unavailable IP block (IP block
not available on a given SoC).

Quoted 3 lines

This beeing said, I understand the readability concern, and I won't force this split if
we find a way to declare a clk as "unavailable" or "disabled"

The readability concern is a small one. Basically you've broken these peripherals out into separate dts and then you reference them from the boards/platforms that have them. That sounds very sane to me. The alternative would be to copy/paste these peripheral nodes into each dts file that needs them, but that isn't a very maintainable idea (e.g. propagating bug fixes across every file, etc).

In short I think the series is good.

Quoted 27 lines

Quoted 4 lines
Regarding naming conflicts, is your issue with string name collisions during calls to __clk_lookup?
No, there is no collision in clk names, because each optional clock has a unique name.
But there may be conflicts on clk ids (peripheral ids):
LCDC (LCD Controller) and ISI (Image Sensor Interface) peripherals have the same id (25)
in sam9x5 SoC family but are never both available in a given SoC.
If you declare LCDC clk before ISI clock, the former will always be returned when you
reference the ISI clk in ISI peripheral node (clocks=<&periph 25>).
This will work, as the method for enabling/disabling periph clk are the same for all clks.
But when you print the clk tree (using debugfs) you will see lcdc_clk with prepare/enable
count incremented and isi_clk always unused, even if the SoC does not have an LCDC block.
Moreover, isi_clk will be allocated for nothing, because it cannot be retrieved.

Quoted 6 lines

And what happens if an unavailable clock is referenced (I did not test that, but I guess
the is_enabled callback will always return false)?
This case should not happen if the dts is correctly defined, but still, I think unavailable
clocks should not be registered in the clk framework.

How do you define an "unavailable" clock? The common clock binding doesn't have any info on interpreting the standard "status" property, if that is what you mean.

I think that we should not define unavailable clocks.

Regards,
Mike

Quoted 430 lines

Please, feel free to share your thoughts.

Best Regards,

Boris

Quoted 423 lines

Thanks,
Mike

Quoted 420 lines

I must say that I was not in favor for this split because of readability and dts/dtsi file organization (you know, the usual question: where the hell this peripheral property is finally setup?).

Quoted 8 lines

As explained to Thomas, I thought device tree was here to give a real description of the
hardware parts (in case of sam9x5.dtsi the description of the common parts of sam9x5 SoC
family).
If you define peripherals that are not present in a SoC (lets say macb0 for sam9g15) you break
this rule.

Well, on the other hand, the status says "disabled", so we can imagine that it has been disabled, from its birth, in hardware...

Quoted 19 lines

I'm not telling I have the right approach here, I'm just trying to understand what should be done and
what should not.
Finally, I'd like to point that the memory footprint of the dtb file generated after this patch has been
applied is bit smaller (even if it won't make a real difference):
with this patch:
15937 arch/arm/boot/dts/at91-ariag25.dtb
15860 arch/arm/boot/dts/at91sam9g15ek.dtb
16905 arch/arm/boot/dts/at91sam9g25ek.dtb
16473 arch/arm/boot/dts/at91sam9g35ek.dtb
17341 arch/arm/boot/dts/at91sam9x25ek.dtb
16473 arch/arm/boot/dts/at91sam9x35ek.dtb
without this patch:

Quoted 7 lines

16077 arch/arm/boot/dts/at91-ariag25.dtb
16824 arch/arm/boot/dts/at91sam9g15ek.dtb
16849 arch/arm/boot/dts/at91sam9g25ek.dtb
16849 arch/arm/boot/dts/at91sam9g35ek.dtb
15017 arch/arm/boot/dts/at91sam9m10g45ek.dtb
17145 arch/arm/boot/dts/at91sam9x25ek.dtb
16849 arch/arm/boot/dts/at91sam9x35ek.dtb

Quoted 352 lines

Best Regards,
J.

Quoted 350 lines

Signed-off-by Boris BREZILLON <[email protected]>

---
   arch/arm/boot/dts/at91sam9g25.dtsi       |    2 +
   arch/arm/boot/dts/at91sam9g35.dtsi       |    1 +
   arch/arm/boot/dts/at91sam9x25.dtsi       |   24 ++---------
   arch/arm/boot/dts/at91sam9x35.dtsi       |    1 +
   arch/arm/boot/dts/at91sam9x5.dtsi        |   67 ------------------------------
   arch/arm/boot/dts/at91sam9x5_macb0.dtsi  |   56 +++++++++++++++++++++++++
   arch/arm/boot/dts/at91sam9x5_macb1.dtsi  |   44 ++++++++++++++++++++
   arch/arm/boot/dts/at91sam9x5_usart3.dtsi |   51 +++++++++++++++++++++++
   8 files changed, 158 insertions(+), 88 deletions(-)

create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi

arch/arm/boot/dts/at91sam9g25.dtsi +2 -0

index b4ec6fe..17b8799 100644
@@ -7,6 +7,8 @@
    */
 
   #include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
   / {
    model = "Atmel AT91SAM9G25 SoC";

arch/arm/boot/dts/at91sam9g35.dtsi +1 -0

index bebf9f5..e35c2fc 100644
@@ -7,6 +7,7 @@
    */
 
   #include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
   / {
    model = "Atmel AT91SAM9G35 SoC";

arch/arm/boot/dts/at91sam9x25.dtsi +3 ~~-21~~

index 49e94ab..c255421 100644
@@ -7,6 +7,9 @@
    */
 
   #include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_macb1.dtsi"
 
   / {
    model = "Atmel AT91SAM9X25 SoC";

@@ -22,27 +25,6 @@
                                   0x80000000 0xfffd0000 0xb83fffff  /* pioC */
                                   0x003fffff 0x003f8000 0x00000000  /* pioD */
                                  >;
-
-                           macb1 {
-                                   pinctrl_macb1_rmii: macb1_rmii-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC16 periph B */
-                                                    AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC18 periph B */
-                                                    AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC19 periph B */
-                                                    AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC20 periph B */
-                                                    AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC21 periph B */
-                                                    AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC27 periph B */
-                                                    AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC28 periph B */
-                                                    AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC29 periph B */
-                                                    AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC30 periph B */
-                                                    AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
-                                   };
-                           };
-                   };
-
-                   macb1: ethernet at f8030000 {
-                           pinctrl-names = "default";
-                           pinctrl-0 = <&pinctrl_macb1_rmii>;
                    };
            };
    };

arch/arm/boot/dts/at91sam9x35.dtsi +1 -0

index 1a3d525..8eac66c 100644
@@ -7,6 +7,7 @@
    */
 
   #include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
 
   / {
    model = "Atmel AT91SAM9X35 SoC";

arch/arm/boot/dts/at91sam9x5.dtsi +0 ~~-67~~

index 57d45f5..05f4c74 100644
@@ -206,29 +206,6 @@
                                    };
                            };
 
-                           usart3 {
-                                   pinctrl_usart3: usart3-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PC22 periph B with pullup */
-                                                    AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
-                                   };
-
-                                   pinctrl_usart3_rts: usart3_rts-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
-                                   };
-
-                                   pinctrl_usart3_cts: usart3_cts-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
-                                   };
-
-                                   pinctrl_usart3_sck: usart3_sck-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
-                                   };
-                           };
-
                            uart0 {
                                    pinctrl_uart0: uart0-0 {
                                            atmel,pins =

@@ -277,34 +254,6 @@
                                    };
                            };
 
-                           macb0 {
-                                   pinctrl_macb0_rmii: macb0_rmii-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A */
-                                                    AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A */
-                                                    AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB2 periph A */
-                                                    AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB3 periph A */
-                                                    AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
-                                                    AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB5 periph A */
-                                                    AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A */
-                                                    AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB7 periph A */
-                                                    AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A */
-                                                    AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
-                                   };
-
-                                   pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
-                                           atmel,pins =
-                                                   <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB8 periph A */
-                                                    AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB11 periph A */
-                                                    AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB12 periph A */
-                                                    AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB13 periph A */
-                                                    AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB14 periph A */
-                                                    AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB15 periph A */
-                                                    AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB16 periph A */
-                                                    AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
-                                   };
-                           };
-
                            mmc0 {
                                    pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
                                            atmel,pins =

@@ -605,22 +554,6 @@
                            status = "disabled";
                    };
 
-                   macb0: ethernet at f802c000 {
-                           compatible = "cdns,at32ap7000-macb", "cdns,macb";
-                           reg = <0xf802c000 0x100>;
-                           interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
-                           pinctrl-names = "default";
-                           pinctrl-0 = <&pinctrl_macb0_rmii>;
-                           status = "disabled";
-                   };
-
-                   macb1: ethernet at f8030000 {
-                           compatible = "cdns,at32ap7000-macb", "cdns,macb";
-                           reg = <0xf8030000 0x100>;
-                           interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
-                           status = "disabled";
-                   };
-
                    i2c0: i2c at f8010000 {
                            compatible = "atmel,at91sam9x5-i2c";
                            reg = <0xf8010000 0x100>;

arch/arm/boot/dts/at91sam9x5_macb0.dtsi new file +56 -0

new file mode 100644
index 0000000..55731ff
@@ -0,0 +1,56 @@
+/*
+ * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
+ * Ethernet interface.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+   ahb {
+           apb {
+                   pinctrl at fffff400 {
+                           macb0 {
+                                   pinctrl_macb0_rmii: macb0_rmii-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A */
+                                                    AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A */
+                                                    AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB2 periph A */
+                                                    AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB3 periph A */
+                                                    AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
+                                                    AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB5 periph A */
+                                                    AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A */
+                                                    AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB7 periph A */
+                                                    AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A */
+                                                    AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
+                                   };
+
+                                   pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB8 periph A */
+                                                    AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB11 periph A */
+                                                    AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB12 periph A */
+                                                    AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB13 periph A */
+                                                    AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB14 periph A */
+                                                    AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB15 periph A */
+                                                    AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB16 periph A */
+                                                    AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
+                                   };
+                           };
+                   };
+
+                   macb0: ethernet at f802c000 {
+                           compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                           reg = <0xf802c000 0x100>;
+                           interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
+                           pinctrl-names = "default";
+                           pinctrl-0 = <&pinctrl_macb0_rmii>;
+                           status = "disabled";
+                   };
+           };
+   };
+};

arch/arm/boot/dts/at91sam9x5_macb1.dtsi new file +44 -0

new file mode 100644
index 0000000..77425a6
@@ -0,0 +1,44 @@
+/*
+ * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2
+ * Ethernet interfaces.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+   ahb {
+           apb {
+                   pinctrl at fffff400 {
+                           macb1 {
+                                   pinctrl_macb1_rmii: macb1_rmii-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC16 periph B */
+                                                    AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC18 periph B */
+                                                    AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC19 periph B */
+                                                    AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC20 periph B */
+                                                    AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC21 periph B */
+                                                    AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC27 periph B */
+                                                    AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC28 periph B */
+                                                    AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC29 periph B */
+                                                    AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC30 periph B */
+                                                    AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
+                                   };
+                           };
+                   };
+
+                   macb1: ethernet at f8030000 {
+                           compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                           reg = <0xf8030000 0x100>;
+                           interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
+                           pinctrl-names = "default";
+                           pinctrl-0 = <&pinctrl_macb1_rmii>;
+                           status = "disabled";
+                   };
+           };
+   };
+};

arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file +46 -0

new file mode 100644
index 0000000..5589579
@@ -0,0 +1,51 @@
+/*
+ * at91sam9x5_lcdc.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * 4 USART.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+   ahb {
+           apb {
+                   pinctrl at fffff400 {
+                           usart3 {
+                                   pinctrl_usart3: usart3-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PC22 periph B with pullup */
+                                                    AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC23 periph B */
+                                   };
+
+                                   pinctrl_usart3_rts: usart3_rts-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC24 periph B */
+                                   };
+
+                                   pinctrl_usart3_cts: usart3_cts-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC25 periph B */
+                                   };
+
+                                   pinctrl_usart3_sck: usart3_sck-0 {
+                                           atmel,pins =
+                                                   <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC26 periph B */
+                                   };
+                           };
+                   };
+
+                   usart3: serial at f8028000 {
+                           compatible = "atmel,at91sam9260-usart";
+                           reg = <0xf8028000 0x200>;
+                           interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+                           pinctrl-names = "default";
+                           pinctrl-0 = <&pinctrl_usart3>;

Quoted 10 lines

Quoted 8 lines
Quoted 8 lines
arch/arm/boot/dts/at91sam9x5_usart3.dtsi new file +5 -1
+                           status = "disabled";
+                   };
+           };
+   };
+};
--
1.7.9.5

--
Nicolas Ferre