am33xx/omap5: Improve docs for customization

PATCH New Tom Rini 2 participants 16 messages Aug 20, 2013 – Aug 28, 2013 Arm (32-bit)

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Tom Rini

author

2013-08-20 12:53 UTC #0 lore raw

cover am33xx/omap5: Improve docs for customization

Hey all,

The following series aims to make it easier to take the various ARMv7 TI reference platforms and use them as the base for a custom hardware project. The main outputs here are some re-shuffling of the config headers to try and group things somewhat logically, expanding on comments to make it clear where some values come from and finally correcting a few values based on careful reading of the TRM. The big change here is that we've changed where OMAP5/DRA7xx loads SPL to. Based on reading the TRM as well as testing DRA7xx with UART loading, we're moving the load address to the start of the ROM defined download area, and using another area for scratch space.

The series has been boot tested on am335x and omap5_uevm.

Signature · 1 line

Tom

Tom Rini

author

2013-08-20 12:53 UTC #1 lore raw

PATCH 1/12 am33xx: Correct and expand comments on CONFIG_SPL_MAX_SIZE

We had been allowing the max size to be larger than actually allowed by the ROM. Expand the commentary here to explain why we set these locations.

Signed-off-by Tom Rini <[email protected]>

---
 arch/arm/include/asm/arch-am33xx/omap.h |    2 +-
 include/configs/ti_am335x_common.h      |   10 ++++++++--
 2 files changed, 9 insertions(+), 3 deletions(-)

arch/arm/include/asm/arch-am33xx/omap.h +1 -1

index 1f84311..2250721 100644
@@ -18,7 +18,7 @@
 #ifdef CONFIG_AM33XX
 #define NON_SECURE_SRAM_START	0x402F0400
 #define NON_SECURE_SRAM_END	0x40310000
-#define SRAM_SCRATCH_SPACE_ADDR	0x4030C000
+#define SRAM_SCRATCH_SPACE_ADDR	0x4030B800
 #elif defined(CONFIG_TI81XX)
 #define NON_SECURE_SRAM_START	0x40300000
 #define NON_SECURE_SRAM_END	0x40320000

include/configs/ti_am335x_common.h +8 -2

index fd3ffab..0eae9c8 100644
@@ -41,9 +41,15 @@
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_NET_RETRY_COUNT         10
 
-/* SPL defines. */
+/*
+ * SPL related defines.  The Public RAM memory map the ROM defines the
+ * area between 0x402F0400 and 0x4030B800 as a download area and
+ * 0x4030B800 to 0x4030CE00 as a public stack area.  The ROM also
+ * supports X-MODEM loading via UART, and we leverage this and then use
+ * Y-MODEM to load u-boot.img, when booted over UART.
+ */
 #define CONFIG_SPL_TEXT_BASE		0x402F0400
-#define CONFIG_SPL_MAX_SIZE		(0x4030C000 - CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SPL_MAX_SIZE		(0x4030B800 - CONFIG_SPL_TEXT_BASE)
 #define CONFIG_SPL_YMODEM_SUPPORT
 
 /*

Signature · 1 line

1.7.9.5

Tom Rini

author

2013-08-20 12:53 UTC #2 lore raw

PATCH 2/12 TI:armv7: Move CONFIG_SPL_LIBDISK_SUPPORT to MMC section

In reply to Tom Rini

We only need this library when we're doing "disk" access to MMC/SD. Update comment around the rest of CONFIG_SPL_LIB* to note that the others are always required.

Signed-off-by Tom Rini <[email protected]>

---
 include/configs/ti_armv7_common.h |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

include/configs/ti_armv7_common.h +2 -2

index e0ab691..1e4bca5 100644
@@ -223,14 +223,14 @@
 #endif
 
 #ifdef CONFIG_MMC
+#define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SPL_FAT_SUPPORT
 #endif
 
-/* General parts of the framework. */
+/* General parts of the framework, required. */
 #define CONFIG_SPL_I2C_SUPPORT
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_GPIO_SUPPORT

Signature · 1 line

1.7.9.5

Tom Rini

author

2013-08-20 12:53 UTC #3 lore raw

PATCH 3/12 omap5: Expand CONFIG_SPL_MAX_SIZE and comment upon SRAM_SCRATCH_SPACE_ADDR

In reply to Tom Rini

After examining both TRMs and doing some experimentation, we can rely on using the start of the download area for CONFIG_SPL_TEXT_BASE and then move SRAM_SCRATCH_SPACE_ADDR up, just like am335x. This is required for peripheral boot modes such as UART.

Signed-off-by Tom Rini <[email protected]>

---
 arch/arm/include/asm/arch-omap5/omap.h |   11 ++++++++++-
 include/configs/omap5_common.h         |    4 ++--
 2 files changed, 12 insertions(+), 3 deletions(-)

arch/arm/include/asm/arch-omap5/omap.h +10 -1

index 597c692..e9a51d3 100644
@@ -153,6 +153,15 @@ struct s32ktimer {
 #define EFUSE_4 0x45145100
 #endif /* __ASSEMBLY__ */
 
+/*
+ * In all cases, the TRM defines the RAM Memory Map for the processor
+ * and indicates the area for the downloaded image.  We use all of that
+ * space for download and once up and running may use other parts of the
+ * map for our needs.  We set a scratch space that is at the end of the
+ * OMAP5 download area, but within the DRA7xx download area (as it is
+ * much larger) and do not, at this time, make use of the additional
+ * space.
+ */
 #ifdef CONFIG_DRA7XX
 #define NON_SECURE_SRAM_START	0x40300000
 #define NON_SECURE_SRAM_END	0x40380000	/* Not inclusive */

@@ -160,7 +169,7 @@ struct s32ktimer {
 #define NON_SECURE_SRAM_START	0x40300000
 #define NON_SECURE_SRAM_END	0x40320000	/* Not inclusive */
 #endif
-#define SRAM_SCRATCH_SPACE_ADDR	NON_SECURE_SRAM_START
+#define SRAM_SCRATCH_SPACE_ADDR	0x4031E000
 
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE	0x4031F000

include/configs/omap5_common.h +2 -2

index 8e82fed..0345c57 100644
@@ -128,8 +128,8 @@
 
 
 /* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE		0x40300350
-#define CONFIG_SPL_MAX_SIZE		0x19000	/* 100K */
+#define CONFIG_SPL_TEXT_BASE		0x40300000
+#define CONFIG_SPL_MAX_SIZE		(0x4031E000 - CONFIG_SPL_TEXT_BASE)
 #define CONFIG_SPL_DISPLAY_PRINT
 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"

Signature · 1 line

1.7.9.5

Sricharan R

2013-08-21 05:22 UTC #4 lore raw

PATCH 3/12 omap5: Expand CONFIG_SPL_MAX_SIZE and comment upon SRAM_SCRATCH_SPACE_ADDR

Hi Tom,

Quoted 45 lines · Tom Rini

Signed-off-by Tom Rini <[email protected]>

---
 arch/arm/include/asm/arch-omap5/omap.h |   11 ++++++++++-
 include/configs/omap5_common.h         |    4 ++--
 2 files changed, 12 insertions(+), 3 deletions(-)

arch/arm/include/asm/arch-omap5/omap.h +10 -1

index 597c692..e9a51d3 100644
@@ -153,6 +153,15 @@ struct s32ktimer {
 #define EFUSE_4 0x45145100
 #endif /* __ASSEMBLY__ */
 
+/*
+ * In all cases, the TRM defines the RAM Memory Map for the processor
+ * and indicates the area for the downloaded image.  We use all of that
+ * space for download and once up and running may use other parts of the
+ * map for our needs.  We set a scratch space that is at the end of the
+ * OMAP5 download area, but within the DRA7xx download area (as it is
+ * much larger) and do not, at this time, make use of the additional
+ * space.
+ */
 #ifdef CONFIG_DRA7XX
 #define NON_SECURE_SRAM_START	0x40300000
 #define NON_SECURE_SRAM_END	0x40380000	/* Not inclusive */

@@ -160,7 +169,7 @@ struct s32ktimer {
 #define NON_SECURE_SRAM_START	0x40300000
 #define NON_SECURE_SRAM_END	0x40320000	/* Not inclusive */
 #endif
-#define SRAM_SCRATCH_SPACE_ADDR	NON_SECURE_SRAM_START
+#define SRAM_SCRATCH_SPACE_ADDR	0x4031E000
 
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE	0x4031F000

include/configs/omap5_common.h +0 -0

index 8e82fed..0345c57 100644

include/configs/omap5_common.h line 135

Quoted 10 lines

include/configs/omap5_common.h +2 -2

@@ -128,8 +128,8 @@
 
 
 /* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE		0x40300350
-#define CONFIG_SPL_MAX_SIZE		0x19000	/* 100K */
+#define CONFIG_SPL_TEXT_BASE		0x40300000
+#define CONFIG_SPL_MAX_SIZE		(0x4031E000 - CONFIG_SPL_TEXT_BASE)
 #define CONFIG_SPL_DISPLAY_PRINT
 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"

Ok, we keep the SPL stack at

#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - GENERATED_GBL_DATA_SIZE)

So does this now create any possiblity of STACK overlap with the SCRATCH PAD area ? or since we have 8K at TOP, this is enough to avoid overlap ?

Is it good to keep NON_SECURE_SRAM_END 0x4031E000 otherwise ?

Also with the base address change to 0x40300000, wanted to check this once on HS devices. I can check this and let you know.

Regards,
Sricharan

Tom Rini

author

2013-08-21 13:49 UTC #5 lore raw

PATCH 3/12 omap5: Expand CONFIG_SPL_MAX_SIZE and comment upon SRAM_SCRATCH_SPACE_ADDR

Quoted 60 lines · Sricharan R

Hi Tom,

Quoted 45 lines · Tom Rini

Signed-off-by Tom Rini <[email protected]>

---
 arch/arm/include/asm/arch-omap5/omap.h |   11 ++++++++++-
 include/configs/omap5_common.h         |    4 ++--
 2 files changed, 12 insertions(+), 3 deletions(-)

arch/arm/include/asm/arch-omap5/omap.h +10 -1

index 597c692..e9a51d3 100644
@@ -153,6 +153,15 @@ struct s32ktimer {
 #define EFUSE_4 0x45145100
 #endif /* __ASSEMBLY__ */
 
+/*
+ * In all cases, the TRM defines the RAM Memory Map for the processor
+ * and indicates the area for the downloaded image.  We use all of that
+ * space for download and once up and running may use other parts of the
+ * map for our needs.  We set a scratch space that is at the end of the
+ * OMAP5 download area, but within the DRA7xx download area (as it is
+ * much larger) and do not, at this time, make use of the additional
+ * space.
+ */
 #ifdef CONFIG_DRA7XX
 #define NON_SECURE_SRAM_START	0x40300000
 #define NON_SECURE_SRAM_END	0x40380000	/* Not inclusive */

@@ -160,7 +169,7 @@ struct s32ktimer {
 #define NON_SECURE_SRAM_START	0x40300000
 #define NON_SECURE_SRAM_END	0x40320000	/* Not inclusive */
 #endif
-#define SRAM_SCRATCH_SPACE_ADDR	NON_SECURE_SRAM_START
+#define SRAM_SCRATCH_SPACE_ADDR	0x4031E000
 
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE	0x4031F000

include/configs/omap5_common.h +0 -0

index 8e82fed..0345c57 100644

include/configs/omap5_common.h line 135

Quoted 10 lines

include/configs/omap5_common.h +2 -2

@@ -128,8 +128,8 @@
 
 
 /* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE		0x40300350
-#define CONFIG_SPL_MAX_SIZE		0x19000	/* 100K */
+#define CONFIG_SPL_TEXT_BASE		0x40300000
+#define CONFIG_SPL_MAX_SIZE		(0x4031E000 - CONFIG_SPL_TEXT_BASE)
 #define CONFIG_SPL_DISPLAY_PRINT
 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"

Ok, we keep the SPL stack at

Quoted 5 lines

#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - GENERATED_GBL_DATA_SIZE)
So does this now create any possiblity of STACK overlap with the SCRATCH PAD area ? or since we have 8K at TOP, this is enough to avoid overlap ?

Yes, we should be fine here, from a quick look at the .su files we've got around.

Quoted 4 lines

Is it good to keep NON_SECURE_SRAM_END 0x4031E000 otherwise ?
Also with the base address change to 0x40300000, wanted to check this once on HS devices. I can check this and let you know.

OK, thanks.

Signature · 8 lines

Tom
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Tom Rini

author

2013-08-20 12:53 UTC #6 lore raw

PATCH 4/12 TI:am335x: Better comment and organize the networking related options

In reply to Tom Rini

While in here, drop CONFIG_BOOTP_DEFAULT as it is unused in the code.

Signed-off-by Tom Rini <[email protected]>

---
 include/configs/am335x_evm.h       |   11 +++++++++--
 include/configs/ti_am335x_common.h |   11 +++++------
 2 files changed, 14 insertions(+), 8 deletions(-)

include/configs/am335x_evm.h +9 -2

index e0a87f8..5ed1dca 100644
@@ -228,17 +228,24 @@
 /* SPL */
 #ifndef CONFIG_NOR_BOOT
 #define CONFIG_SPL_YMODEM_SUPPORT
+
+/* CPSW support */
+#define CONFIG_SPL_ETH_SUPPORT
+
+/* USB gadget RNDIS */
+#define CONFIG_SPL_MUSB_NEW_SUPPORT
+
+/* General network SPL, both CPSW and USB gadget RNDIS */
 #define CONFIG_SPL_NET_SUPPORT
 #define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SPL_NET_VCI_STRING	"AM335x U-Boot SPL"
-#define CONFIG_SPL_ETH_SUPPORT
+
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SPL_SPI_BUS		0
 #define CONFIG_SPL_SPI_CS		0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
-#define CONFIG_SPL_MUSB_NEW_SUPPORT
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
 
 #ifdef CONFIG_NAND

include/configs/ti_am335x_common.h +5 -6

index 0eae9c8..837c02c 100644
@@ -28,18 +28,17 @@
 #define CONFIG_SYS_NS16550_CLK		48000000
 
 /* Network defines. */
-#define CONFIG_CMD_NET
+#define CONFIG_CMD_NET			/* 'bootp' and 'tftp' */
 #define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_DRIVER_TI_CPSW
-#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS		/* Configurable parts of CMD_DHCP */
 #define CONFIG_BOOTP_DNS2
 #define CONFIG_BOOTP_SEND_HOSTNAME
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_NET_RETRY_COUNT         10
+#define CONFIG_CMD_PING
+#define CONFIG_DRIVER_TI_CPSW		/* Driver for IP block */
+#define CONFIG_MII			/* Required in net/eth.c */
 
 /*
  * SPL related defines.  The Public RAM memory map the ROM defines the

Signature · 1 line

1.7.9.5

Tom Rini

author

2013-08-20 12:53 UTC #7 lore raw

PATCH 5/12 am335x_evm: Add comment by SPL SPI support

In reply to Tom Rini

Signed-off-by Tom Rini <[email protected]>

---
 include/configs/am335x_evm.h |    2 ++
 1 file changed, 2 insertions(+)

include/configs/am335x_evm.h +2 -0

index 5ed1dca..4e6429c 100644
@@ -240,12 +240,14 @@
 #define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SPL_NET_VCI_STRING	"AM335x U-Boot SPL"
 
+/* SPI flash. */
 #define CONFIG_SPL_SPI_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SPL_SPI_BUS		0
 #define CONFIG_SPL_SPI_CS		0
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
+
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
 
 #ifdef CONFIG_NAND

Signature · 1 line

1.7.9.5

Tom Rini

author

2013-08-20 12:53 UTC #8 lore raw

PATCH 6/12 am335x_evm: Regroup USB options

In reply to Tom Rini

Signed-off-by Tom Rini <[email protected]>

---
 include/configs/am335x_evm.h |   80 ++++++++++++++++++++++--------------------
 1 file changed, 41 insertions(+), 39 deletions(-)

include/configs/am335x_evm.h +41 ~~-39~~

index 4e6429c..eae5a19 100644
@@ -171,44 +171,6 @@
 	"run mmcboot;" \
 	"run nandboot;"
 
-/* USB Composite download gadget - g_dnl */
-#define CONFIG_USB_GADGET
-#define CONFIG_USBDOWNLOAD_GADGET
-
-/* USB TI's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0403
-#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
-
-/* USB Device Firmware Update support */
-#define CONFIG_DFU_FUNCTION
-#define CONFIG_DFU_MMC
-#define CONFIG_CMD_DFU
-#define DFU_ALT_INFO_MMC \
-	"boot part 0 1;" \
-	"rootfs part 0 2;" \
-	"MLO fat 0 1;" \
-	"MLO.raw mmc 100 100;" \
-	"u-boot.img.raw mmc 300 400;" \
-	"spl-os-args.raw mmc 80 80;" \
-	"spl-os-image.raw mmc 900 2000;" \
-	"spl-os-args fat 0 1;" \
-	"spl-os-image fat 0 1;" \
-	"u-boot.img fat 0 1;" \
-	"uEnv.txt fat 0 1"
-#ifdef CONFIG_NAND
-#define CONFIG_DFU_NAND
-#define DFU_ALT_INFO_NAND \
-	"SPL part 0 1;" \
-	"SPL.backup1 part 0 2;" \
-	"SPL.backup2 part 0 3;" \
-	"SPL.backup3 part 0 4;" \
-	"u-boot part 0 5;" \
-	"u-boot-spl-os part 0 6;" \
-	"kernel part 0 8;" \
-	"rootfs part 0 9"
-#endif
-
 /* NS16550 Configuration */
 #define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
 #define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */

@@ -283,13 +245,19 @@
 #endif
 
 /*
- * USB configuration
+ * USB configuration.  We enable MUSB support, both for host and for
+ * gadget.  We set USB0 as peripheral and USB1 as host, based on the
+ * board schematic and physical port wired to each.  Then for host we
+ * add mass storage support and for gadget we add both RNDIS ethernet
+ * and DFU.
  */
 #define CONFIG_USB_MUSB_DSPS
 #define CONFIG_ARCH_MISC_INIT
 #define CONFIG_MUSB_GADGET
 #define CONFIG_MUSB_PIO_ONLY
 #define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_USB_GADGET
+#define CONFIG_USBDOWNLOAD_GADGET
 #define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_GADGET_VBUS_DRAW	2
 #define CONFIG_MUSB_HOST

@@ -307,6 +275,11 @@
 #define CONFIG_USB_ETHER
 #define CONFIG_USB_ETH_RNDIS
 #define CONFIG_USBNET_HOST_ADDR	"de:ad:be:af:00:00"
+
+/* USB TI's IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x0403
+#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
+#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #endif /* CONFIG_MUSB_GADGET */
 
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)

@@ -318,6 +291,35 @@
 #undef CONFIG_SPL_ETH_SUPPORT
 #endif
 
+/* USB Device Firmware Update support */
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+#define CONFIG_CMD_DFU
+#define DFU_ALT_INFO_MMC \
+	"boot part 0 1;" \
+	"rootfs part 0 2;" \
+	"MLO fat 0 1;" \
+	"MLO.raw mmc 100 100;" \
+	"u-boot.img.raw mmc 300 400;" \
+	"spl-os-args.raw mmc 80 80;" \
+	"spl-os-image.raw mmc 900 2000;" \
+	"spl-os-args fat 0 1;" \
+	"spl-os-image fat 0 1;" \
+	"u-boot.img fat 0 1;" \
+	"uEnv.txt fat 0 1"
+#ifdef CONFIG_NAND
+#define CONFIG_DFU_NAND
+#define DFU_ALT_INFO_NAND \
+	"SPL part 0 1;" \
+	"SPL.backup1 part 0 2;" \
+	"SPL.backup2 part 0 3;" \
+	"SPL.backup3 part 0 4;" \
+	"u-boot part 0 5;" \
+	"u-boot-spl-os part 0 6;" \
+	"kernel part 0 8;" \
+	"rootfs part 0 9"
+#endif
+
 /*
  * Default to using SPI for environment, etc.
  * 0x000000 - 0x020000 : SPL (128KiB)

Signature · 1 line

1.7.9.5

Tom Rini

author

2013-08-20 12:53 UTC #9 lore raw

PATCH 7/12 TI:armv7: Re-order slightly the generic CONFIG options, expand related comments

In reply to Tom Rini

Re-group the general options to note things that can be removed safely to reduce binary size when not required, and expand the comment about what commands we do include to note it could be replaced with a specific list of required one. While at it, move the CMD parts of various blocks IP to the end of the list for consistency.

Signed-off-by Tom Rini <[email protected]>

---
 include/configs/ti_armv7_common.h |   22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

include/configs/ti_armv7_common.h +12 ~~-10~~

index 1e4bca5..e89e874 100644
@@ -60,12 +60,12 @@
 
 /* I2C IP block */
 #define CONFIG_I2C
-#define CONFIG_CMD_I2C
 #define CONFIG_HARD_I2C
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_SYS_I2C_SLAVE		1
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_DRIVER_OMAP24XX_I2C
+#define CONFIG_CMD_I2C
 
 /* MMC/SD IP block */
 #define CONFIG_MMC

@@ -87,10 +87,10 @@
  * access CS0 at is 0x8000000.
  */
 #ifdef CONFIG_NAND
-#define CONFIG_CMD_NAND
 #define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_SYS_NAND_BASE		0x8000000
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_CMD_NAND
 #endif
 
 /*

@@ -103,14 +103,18 @@
  * console baudrate of 115200 and use the default baud rate table.
  */
 #define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
-#define CONFIG_SYS_LONGHELP
 #define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"U-Boot# "
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_ENV_VARS_UBOOT_CONFIG	/* Strongly encouraged */
+#define CONFIG_ENV_OVERWRITE		/* Overwrite ethaddr / serial# */
+
+/* As stated above, the following choices are optional. */
+#define CONFIG_SYS_LONGHELP
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_PROMPT		"U-Boot# "
 #define CONFIG_VERSION_VARIABLE
-#define CONFIG_ENV_VARS_UBOOT_CONFIG
-#define CONFIG_BAUDRATE			115200
 
 /* We set the max number of command args high to avoid HUSH bugs. */
 #define CONFIG_SYS_MAXARGS		64

@@ -123,9 +127,6 @@
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
 /*
  * When we have SPI, NOR or NAND flash we expect to be making use of
  * mtdparts, both for ease of use in U-Boot and for passing information

@@ -141,7 +142,8 @@
  * useful commands.  Note that we must have set CONFIG_SYS_NO_FLASH
  * prior to this include, in order to skip a few commands.  When we do
  * have flash, if we expect these commands they must be enabled in that
- * config.
+ * config.  If desired, a specific list of desired commands can be used
+ * instead.
  */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_ASKENV

Signature · 1 line

1.7.9.5

Tom Rini

author

2013-08-20 12:53 UTC #10 lore raw

PATCH 8/12 am335x_evm: Update README for customization

In reply to Tom Rini

As this is a reference platform, update the README to note which IP blocks are required for use due to design choices of the reference rather than required by the SoC itself.

Signed-off-by Tom Rini <[email protected]>

---
 board/ti/am335x/README |   28 +++++++++++++++++++++++++++-
 1 file changed, 27 insertions(+), 1 deletion(-)

board/ti/am335x/README +27 -1

index 67b5246..2a30ab8 100644
@@ -13,7 +13,33 @@ documented in TI's reference designs:
 - AM335x EVM SK
 - Beaglebone White
 - Beaglebone Black
-'
+
+Customization
+=============
+
+Given that all of the above boards are reference platforms (and the
+Beaglebone platforms are OSHA), it is likely that this platform code and
+configuration will be used as the basis of a custom platform.  It is
+worth noting that aside from things such as NAND or MMC only being
+required if a custom platform makes use of these blocks, the following
+are required, depending on design:
+
+- GPIO is only required if DDR3 power is controlled in a way similar to
+  EVM SK
+- SPI is only required for SPI flash, or exposing the SPI bus.
+
+The following blocks are required:
+- I2C, to talk with the PMIC and ensure that we do not run afoul of
+  errata 1.0.24.
+
+When removing options as part of customization,
+CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your
+needs and to remove no longer relevant options as in some cases we
+define additional text blocks (such as for NAND or DFU strings).  Also
+note that all of the SPL options are grouped together, rather than with
+the IP blocks, so both areas will need their choices updated to reflect
+the custom design.
+
 NAND
 ====

Signature · 1 line

1.7.9.5

Tom Rini

author

2013-08-20 12:53 UTC #11 lore raw

PATCH 9/12 TI:am33xx: Move SPL YMODEM support to the per-board config

In reply to Tom Rini

Signed-off-by Tom Rini <[email protected]>

---
 include/configs/ti_am335x_common.h |    1 -
 1 file changed, 1 deletion(-)

include/configs/ti_am335x_common.h +0 -1

index 837c02c..d2e34ae 100644
@@ -49,7 +49,6 @@
  */
 #define CONFIG_SPL_TEXT_BASE		0x402F0400
 #define CONFIG_SPL_MAX_SIZE		(0x4030B800 - CONFIG_SPL_TEXT_BASE)
-#define CONFIG_SPL_YMODEM_SUPPORT
 
 /*
  * Since SPL did pll and ddr initialization for us,

Signature · 1 line

1.7.9.5

Tom Rini

author

2013-08-20 12:53 UTC #12 lore raw

PATCH 10/12 TI:omap5: Clarify comments about SPL and DDR timings in common config

In reply to Tom Rini

Signed-off-by Tom Rini <[email protected]>

---
 include/configs/omap5_common.h |   15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

include/configs/omap5_common.h +12 -3

index 0345c57..98ba559 100644
@@ -28,9 +28,12 @@
 /* Use General purpose timer 1 */
 #define CONFIG_SYS_TIMERBASE		GPT2_BASE
 
+/*
+ * For the DDR timing information we can either dynamically determine
+ * the timings to use or use pre-determined timings (based on using the
+ * dynamic method.  Default to the static timing infomation.
+ */
 #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-
-/* Defines for SDRAM init */
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
 #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS

@@ -127,7 +130,13 @@
 	"fi"
 
 
-/* Defines for SPL */
+/*
+ * SPL related defines.  The Public RAM memory map the ROM defines the
+ * area between 0x40300000 and 0x4031E000 as a download area for OMAP5
+ * (dra7xx is larger, but we do not need to be larger at this time).  We
+ * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
+ * print some information.
+ */
 #define CONFIG_SPL_TEXT_BASE		0x40300000
 #define CONFIG_SPL_MAX_SIZE		(0x4031E000 - CONFIG_SPL_TEXT_BASE)
 #define CONFIG_SPL_DISPLAY_PRINT

Signature · 1 line

1.7.9.5

Tom Rini

author

2013-08-20 12:53 UTC #13 lore raw

PATCH 11/12 omap5_uevm: Better comment why we have TCA642X and the reset time

In reply to Tom Rini

Signed-off-by Tom Rini <[email protected]>

---
 include/configs/omap5_uevm.h |    3 +++
 1 file changed, 3 insertions(+)

include/configs/omap5_uevm.h +3 -0

index d10c2b5..3948709 100644
@@ -35,12 +35,15 @@
 #define CONFIG_PARTITION_UUIDS
 #define CONFIG_CMD_PART
 
+/* Required support for the TCA642X GPIO we have on the uEVM */
 #define CONFIG_TCA642X
 #define CONFIG_CMD_TCA642X
 #define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4
 #define CONFIG_SYS_I2C_TCA642X_ADDR 0x22
 
 #define CONSOLEDEV		"ttyO2"
+
+/* Max time to hold reset on this board, see doc/README.omap-reset-time */
 #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC	16296
 
 #include <configs/omap5_common.h>

Signature · 1 line

1.7.9.5

Tom Rini

author

2013-08-20 12:53 UTC #14 lore raw

PATCH 12/12 dra7xx_evm: Re-order and comment the networking related config options

In reply to Tom Rini

Signed-off-by Tom Rini <[email protected]>

---
 include/configs/dra7xx_evm.h |   18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

include/configs/dra7xx_evm.h +8 ~~-10~~

index 58786ff..4fbe768 100644
@@ -26,21 +26,19 @@
 #include <configs/omap5_common.h>
 
 /* CPSW Ethernet */
-#define CONFIG_CMD_NET
+#define CONFIG_CMD_NET			/* 'bootp' and 'tftp' */
 #define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_MII
-#define CONFIG_DRIVER_TI_CPSW
-#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS		/* Configurable parts of CMD_DHCP */
 #define CONFIG_BOOTP_DNS2
 #define CONFIG_BOOTP_SEND_HOSTNAME
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_NET_RETRY_COUNT         10
-#define CONFIG_NET_MULTI
-#define CONFIG_PHY_GIGE
+#define CONFIG_NET_RETRY_COUNT		10
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_DRIVER_TI_CPSW		/* Driver for IP block */
+#define CONFIG_MII			/* Required in net/eth.c */
+#define CONFIG_PHY_GIGE			/* per-board part of CPSW */
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ADDR			2

Signature · 1 line

1.7.9.5

Tom Rini

author

2013-08-28 18:25 UTC #15 lore raw

cover am33xx/omap5: Improve docs for customization

In reply to Tom Rini

Quoted 13 lines · Tom Rini

Hey all,
The following series aims to make it easier to take the various ARMv7 TI reference platforms and use them as the base for a custom hardware project. The main outputs here are some re-shuffling of the config headers to try and group things somewhat logically, expanding on comments to make it clear where some values come from and finally correcting a few values based on careful reading of the TRM. The big change here is that we've changed where OMAP5/DRA7xx loads SPL to. Based on reading the TRM as well as testing DRA7xx with UART loading, we're moving the load address to the start of the ROM defined download area, and using another area for scratch space.

Quoted 1 line

The series has been boot tested on am335x and omap5_uevm.

Applied to u-boot-ti/master, thanks!

Signature · 8 lines

Tom
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