irqchip: sirf: move from legacy mode to linear irqdomain

PATCH New Barry Song 2 participants 5 messages Aug 6, 2013 – Aug 29, 2013

Subsystems (3)

Arm (32-bit) Arm sub-architectures irqchip drivers

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Barry Song

author

2013-08-06 05:37 UTC #0 lore raw

PATCH 1/2 irqchip: sirf: move from legacy mode to linear irqdomain

the series of patches for irqdomain core in 3.11 has broken sirf irq which uses legacy mapping. all users fail in the new kernel while setupping irq.

this patch moves to linear irqdomain and drop old legacy irqdomain codes since we don't need it any more, and at the same time, it also fixes the broken interrupts of sirfsoc in 3.11.

on the other hand, we actually only have 64 interrupt sources for prima2 and atlas6, but there are 128 interrupt souces for marco which uses GIC. in the legacy codes, sirf gpio also uses legacy irqdomain, so to make gpio interrupt mapping not depend on the prima2/atlas6/marco an use unified marco,we enlarge prima2/atlas6 interrupt number to 128. here we don't need this workaround any more as sirf gpio also moved to linear mode before. so we move SIRFSOC_NUM_IRQS back to 64 too.

Signed-off-by Barry Song <[email protected]>

---
 drivers/irqchip/irq-sirfsoc.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

drivers/irqchip/irq-sirfsoc.c +10 -8

index 69ea44e..4851afa 100644
@@ -23,7 +23,7 @@
 #define SIRFSOC_INT_RISC_LEVEL1         0x0024
 #define SIRFSOC_INIT_IRQ_ID		0x0038
 
-#define SIRFSOC_NUM_IRQS		128
+#define SIRFSOC_NUM_IRQS		64
 
 static struct irq_domain *sirfsoc_irqdomain;

@@ -32,15 +32,18 @@ sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
 {
 	struct irq_chip_generic *gc;
 	struct irq_chip_type *ct;
+	int ret;
+	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
 
-	gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
-	ct = gc->chip_types;
+	ret = irq_alloc_domain_generic_chips(sirfsoc_irqdomain, num, 1, "irq_sirfsoc",
+		handle_level_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE);
 
+	gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, irq_start);
+	gc->reg_base = base;
+	ct = gc->chip_types;
 	ct->chip.irq_mask = irq_gc_mask_clr_bit;
 	ct->chip.irq_unmask = irq_gc_mask_set_bit;
 	ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
-
-	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
 }
 
 static asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)

@@ -60,9 +63,8 @@ static int __init sirfsoc_irq_init(struct device_node *np, struct device_node *p
 	if (!base)
 		panic("unable to map intc cpu registers\n");
 
-	/* using legacy because irqchip_generic does not work with linear */
-	sirfsoc_irqdomain = irq_domain_add_legacy(np, SIRFSOC_NUM_IRQS, 0, 0,
-				 &irq_domain_simple_ops, base);
+	sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
+		&irq_generic_chip_ops, base);
 
 	sirfsoc_alloc_gc(base, 0, 32);
 	sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32);

Signature · 1 line

1.8.2.3

Barry Song

author

2013-08-19 09:30 UTC #1 lore raw

PATCH 1/2 irqchip: sirf: move from legacy mode to linear irqdomain

2013/8/6 Barry Song <[email protected]>:

Quoted 17 lines

the series of patches for irqdomain core in 3.11 has broken sirf irq which uses legacy mapping. all users fail in the new kernel while setupping irq.
this patch moves to linear irqdomain and drop old legacy irqdomain codes since we don't need it any more, and at the same time, it also fixes the broken interrupts of sirfsoc in 3.11.
on the other hand, we actually only have 64 interrupt sources for prima2 and atlas6, but there are 128 interrupt souces for marco which uses GIC. in the legacy codes, sirf gpio also uses legacy irqdomain, so to make gpio interrupt mapping not depend on the prima2/atlas6/marco an use unified marco,we enlarge prima2/atlas6 interrupt number to 128. here we don't need this workaround any more as sirf gpio also moved to linear mode before. so we move SIRFSOC_NUM_IRQS back to 64 too.

Quoted 1 line

Signed-off-by Barry Song <[email protected]>

ping, this should touch 3.11 as sirfsoc interrupts break in 3.11.

Quoted 53 lines

---
 drivers/irqchip/irq-sirfsoc.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

drivers/irqchip/irq-sirfsoc.c +10 -9

index 69ea44e..4851afa 100644
@@ -23,7 +23,7 @@
 #define SIRFSOC_INT_RISC_LEVEL1         0x0024
 #define SIRFSOC_INIT_IRQ_ID            0x0038
 
-#define SIRFSOC_NUM_IRQS               128
+#define SIRFSOC_NUM_IRQS               64
 
 static struct irq_domain *sirfsoc_irqdomain;

@@ -32,15 +32,18 @@ sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
 {
        struct irq_chip_generic *gc;
        struct irq_chip_type *ct;
+       int ret;
+       unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
 
-       gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
-       ct = gc->chip_types;
+       ret = irq_alloc_domain_generic_chips(sirfsoc_irqdomain, num, 1, "irq_sirfsoc",
+               handle_level_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE);
 
+       gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, irq_start);
+       gc->reg_base = base;
+       ct = gc->chip_types;
        ct->chip.irq_mask = irq_gc_mask_clr_bit;
        ct->chip.irq_unmask = irq_gc_mask_set_bit;
        ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
-
-       irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
 }
 
 static asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)

@@ -60,9 +63,8 @@ static int __init sirfsoc_irq_init(struct device_node *np, struct device_node *p
        if (!base)
                panic("unable to map intc cpu registers\n");
 
-       /* using legacy because irqchip_generic does not work with linear */
-       sirfsoc_irqdomain = irq_domain_add_legacy(np, SIRFSOC_NUM_IRQS, 0, 0,
-                                &irq_domain_simple_ops, base);
+       sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
+               &irq_generic_chip_ops, base);
 
        sirfsoc_alloc_gc(base, 0, 32);
        sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32);
--

Quoted 2 lines

1.8.2.3

-barry

Olof Johansson

2013-08-29 16:48 UTC #2 lore raw

PATCH 1/2 irqchip: sirf: move from legacy mode to linear irqdomain

Quoted 18 lines · Barry Song

2013/8/6 Barry Song <[email protected]>:
Quoted 17 lines
the series of patches for irqdomain core in 3.11 has broken sirf irq which uses legacy mapping. all users fail in the new kernel while setupping irq.
this patch moves to linear irqdomain and drop old legacy irqdomain codes since we don't need it any more, and at the same time, it also fixes the broken interrupts of sirfsoc in 3.11.
on the other hand, we actually only have 64 interrupt sources for prima2 and atlas6, but there are 128 interrupt souces for marco which uses GIC. in the legacy codes, sirf gpio also uses legacy irqdomain, so to make gpio interrupt mapping not depend on the prima2/atlas6/marco an use unified marco,we enlarge prima2/atlas6 interrupt number to 128. here we don't need this workaround any more as sirf gpio also moved to linear mode before. so we move SIRFSOC_NUM_IRQS back to 64 too.

Quoted 3 lines

Quoted 1 line
Signed-off-by Barry Song <[email protected]>
ping, this should touch 3.11 as sirfsoc interrupts break in 3.11.

Yeah, apologies for missing this -- applied now and will send up shortly.

-Olof

Barry Song

author

2013-08-06 05:37 UTC #3 lore raw

PATCH 2/2 arm: prima2: drop nr_irqs in mach as we moved to linear irqdomain

In reply to Barry Song

we don't need nr_irqs in machine any more after we move to linear irqdomain for sirfsoc irqchip, so drop them.

Signed-off-by Barry Song <[email protected]>

---
 arch/arm/mach-prima2/common.c | 2 --
 1 file changed, 2 deletions(-)

arch/arm/mach-prima2/common.c +0 -2

index 2c70f74..e110b6d 100644
@@ -42,7 +42,6 @@ static const char *atlas6_dt_match[] __initdata = {
 
 DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
 	/* Maintainer: Barry Song <[email protected]> */
-	.nr_irqs	= 128,
 	.map_io         = sirfsoc_map_io,
 	.init_time	= sirfsoc_init_time,
 	.init_late	= sirfsoc_init_late,

@@ -59,7 +58,6 @@ static const char *prima2_dt_match[] __initdata = {
 
 DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
 	/* Maintainer: Barry Song <[email protected]> */
-	.nr_irqs	= 128,
 	.map_io         = sirfsoc_map_io,
 	.init_time	= sirfsoc_init_time,
 	.dma_zone_size	= SZ_256M,

Signature · 1 line

1.8.2.3

Olof Johansson

2013-08-29 16:48 UTC #4 lore raw

PATCH 1/2 irqchip: sirf: move from legacy mode to linear irqdomain

In reply to Barry Song

Quoted 17 lines · Barry Song

the series of patches for irqdomain core in 3.11 has broken sirf irq which uses legacy mapping. all users fail in the new kernel while setupping irq.
this patch moves to linear irqdomain and drop old legacy irqdomain codes since we don't need it any more, and at the same time, it also fixes the broken interrupts of sirfsoc in 3.11.
on the other hand, we actually only have 64 interrupt sources for prima2 and atlas6, but there are 128 interrupt souces for marco which uses GIC. in the legacy codes, sirf gpio also uses legacy irqdomain, so to make gpio interrupt mapping not depend on the prima2/atlas6/marco an use unified marco,we enlarge prima2/atlas6 interrupt number to 128. here we don't need this workaround any more as sirf gpio also moved to linear mode before. so we move SIRFSOC_NUM_IRQS back to 64 too.

Quoted 1 line

Signed-off-by Barry Song <[email protected]>

Sorry for missing this earlier. I'll apply and send up for 3.11.

-Olof