arm64: suspend/resume implementation

Power management software requires the kernel to save and restore CPU registers while going through suspend and resume operations triggered by kernel subsystems like CPU idle and suspend to RAM.

This patch implements code that provides save and restore mechanism for the arm v8 implementation. Memory for the context is passed as parameter to both cpu_do_suspend and cpu_do_resume functions, and allows the callers to implement context allocation as they deem fit.

The registers that are saved and restored correspond to the registers actually required by the kernel to be up and running and is by no means a complete save and restore of the entire v8 register set.

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 arch/arm64/include/asm/proc-fns.h |  3 ++
 arch/arm64/mm/proc.S              | 64 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 67 insertions(+)

arch/arm64/include/asm/proc-fns.h +3 -0

index 7cdf466..0c657bb 100644
@@ -26,11 +26,14 @@
 #include <asm/page.h>
 
 struct mm_struct;
+struct cpu_suspend_ctx;
 
 extern void cpu_cache_off(void);
 extern void cpu_do_idle(void);
 extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
 extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
+extern void cpu_do_suspend(struct cpu_suspend_ctx *ptr);
+extern u64 cpu_do_resume(phys_addr_t ptr, u64 idmap_ttbr);
 
 #include <asm/memory.h>
 

arch/arm64/mm/proc.S +16 -0

index a82ae88..193bf98 100644
@@ -80,6 +80,70 @@ ENTRY(cpu_do_idle)
 	ret
 ENDPROC(cpu_do_idle)
 
+#ifdef CONFIG_ARM_CPU_SUSPEND
+/**
+ * cpu_do_suspend - save CPU registers context
+ * x0: virtual address of context pointer
+ */
+ENTRY(cpu_do_suspend)
+	mrs	x1, tpidr_el0
+	str	x1, [x0, #CPU_CTX_TPIDR_EL0]
+	mrs	x2, tpidrro_el0
+	str	x2, [x0, #CPU_CTX_TPIDRRO_EL0]
+	mrs	x3, contextidr_el1
+	str	x3, [x0, #CPU_CTX_CTXIDR_EL1]
+	mrs	x4, mair_el1
+	str	x4, [x0, #CPU_CTX_MAIR_EL1]
+	mrs	x5, cpacr_el1
+	str	x5, [x0, #CPU_CTX_CPACR_EL1]

arch/arm64/mm/proc.S +26 -0

+
+/**
+ * cpu_do_resume - registers layout should match the corresponding
+ *                 cpu_do_suspend call
+ *
+ * x0: Physical address of context pointer
+ * x1: Should contain the physical address of identity map page tables
+ *     used to turn on the MMU and complete context restore
+ *
+ * Returns:
+ *	sctlr value in x0
+ */
+ENTRY(cpu_do_resume)
+	tlbi	vmalle1is	// make sure tlb entries are invalid
+	ldr	x2, [x0, #CPU_CTX_TPIDR_EL0]
+	msr	tpidr_el0, x2
+	ldr	x3, [x0, #CPU_CTX_TPIDRRO_EL0]
+	msr	tpidrro_el0, x3
+	ldr	x4, [x0, #CPU_CTX_CTXIDR_EL1]
+	msr	contextidr_el1, x4
+	ldr	x5, [x0, #CPU_CTX_MAIR_EL1]
+	msr	mair_el1, x5
+	ldr	x6, [x0, #CPU_CTX_CPACR_EL1]
+	msr	cpacr_el1, x6
+	msr	ttbr0_el1, x1
+	ldr	x7, [x0, #CPU_CTX_TTBR1_EL1]

Quoted 66 lines · Lorenzo Pieralisi

Power management software requires the kernel to save and restore CPU registers while going through suspend and resume operations triggered by kernel subsystems like CPU idle and suspend to RAM.

This patch implements code that provides save and restore mechanism for the arm v8 implementation. Memory for the context is passed as parameter to both cpu_do_suspend and cpu_do_resume functions, and allows the callers to implement context allocation as they deem fit.

The registers that are saved and restored correspond to the registers actually required by the kernel to be up and running and is by no means a complete save and restore of the entire v8 register set.

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 arch/arm64/include/asm/proc-fns.h |  3 ++
 arch/arm64/mm/proc.S              | 64 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 67 insertions(+)

arch/arm64/include/asm/proc-fns.h +3 -0

index 7cdf466..0c657bb 100644
@@ -26,11 +26,14 @@
 #include <asm/page.h>
 
 struct mm_struct;
+struct cpu_suspend_ctx;
 
 extern void cpu_cache_off(void);
 extern void cpu_do_idle(void);
 extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
 extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
+extern void cpu_do_suspend(struct cpu_suspend_ctx *ptr);
+extern u64 cpu_do_resume(phys_addr_t ptr, u64 idmap_ttbr);
 
 #include <asm/memory.h>
 

arch/arm64/mm/proc.S +20 -0

index a82ae88..193bf98 100644
@@ -80,6 +80,70 @@ ENTRY(cpu_do_idle)
 	ret
 ENDPROC(cpu_do_idle)
 
+#ifdef CONFIG_ARM_CPU_SUSPEND
+/**
+ * cpu_do_suspend - save CPU registers context
+ * x0: virtual address of context pointer
+ */
+ENTRY(cpu_do_suspend)
+	mrs	x1, tpidr_el0
+	str	x1, [x0, #CPU_CTX_TPIDR_EL0]
+	mrs	x2, tpidrro_el0
+	str	x2, [x0, #CPU_CTX_TPIDRRO_EL0]
+	mrs	x3, contextidr_el1
+	str	x3, [x0, #CPU_CTX_CTXIDR_EL1]
+	mrs	x4, mair_el1
+	str	x4, [x0, #CPU_CTX_MAIR_EL1]
+	mrs	x5, cpacr_el1
+	str	x5, [x0, #CPU_CTX_CPACR_EL1]
+	mrs	x6, ttbr1_el1
+	str	x6, [x0, #CPU_CTX_TTBR1_EL1]
+	mrs	x7, tcr_el1
+	str	x7, [x0, #CPU_CTX_TCR_EL1]

arch/arm64/mm/proc.S ENTRY(cpu_do_idle) · line 108

Quoted 6 lines

arch/arm64/mm/proc.S +6 -0

+	mrs	x8, vbar_el1
+	str	x8, [x0, #CPU_CTX_VBAR_EL1]
+	mrs	x9, sctlr_el1
+	str	x9, [x0, #CPU_CTX_SCTLR_EL1]
+	ret
+ENDPROC(cpu_do_suspend)

Can you read all the registers a once and do some stp to save them?

Quoted 26 lines

arch/arm64/mm/proc.S +26 -0

+
+/**
+ * cpu_do_resume - registers layout should match the corresponding
+ *                 cpu_do_suspend call
+ *
+ * x0: Physical address of context pointer
+ * x1: Should contain the physical address of identity map page tables
+ *     used to turn on the MMU and complete context restore
+ *
+ * Returns:
+ *	sctlr value in x0
+ */
+ENTRY(cpu_do_resume)
+	tlbi	vmalle1is	// make sure tlb entries are invalid
+	ldr	x2, [x0, #CPU_CTX_TPIDR_EL0]
+	msr	tpidr_el0, x2
+	ldr	x3, [x0, #CPU_CTX_TPIDRRO_EL0]
+	msr	tpidrro_el0, x3
+	ldr	x4, [x0, #CPU_CTX_CTXIDR_EL1]
+	msr	contextidr_el1, x4
+	ldr	x5, [x0, #CPU_CTX_MAIR_EL1]
+	msr	mair_el1, x5
+	ldr	x6, [x0, #CPU_CTX_CPACR_EL1]
+	msr	cpacr_el1, x6
+	msr	ttbr0_el1, x1
+	ldr	x7, [x0, #CPU_CTX_TTBR1_EL1]

arch/arm64/mm/proc.S ENTRY(cpu_do_idle) · line 144

Quoted 10 lines

arch/arm64/mm/proc.S +10 -0

+	msr	ttbr1_el1, x7
+	ldr	x8, [x0, #CPU_CTX_TCR_EL1]
+	msr	tcr_el1, x8
+	ldr	x9, [x0, #CPU_CTX_VBAR_EL1]
+	msr	vbar_el1, x9
+	ldr	x0, [x0, #CPU_CTX_SCTLR_EL1]
+	isb
+	dsb	sy
+	ret
+ENDPROC(cpu_do_resume)

Same here, use ldp.

BTW, do we need the DSB here or just the ISB?

Quoted 67 lines · Catalin Marinas

Quoted 66 lines · Lorenzo Pieralisi

Power management software requires the kernel to save and restore CPU registers while going through suspend and resume operations triggered by kernel subsystems like CPU idle and suspend to RAM.

This patch implements code that provides save and restore mechanism for the arm v8 implementation. Memory for the context is passed as parameter to both cpu_do_suspend and cpu_do_resume functions, and allows the callers to implement context allocation as they deem fit.

The registers that are saved and restored correspond to the registers actually required by the kernel to be up and running and is by no means a complete save and restore of the entire v8 register set.

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 arch/arm64/include/asm/proc-fns.h |  3 ++
 arch/arm64/mm/proc.S              | 64 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 67 insertions(+)

arch/arm64/include/asm/proc-fns.h +3 -0

index 7cdf466..0c657bb 100644
@@ -26,11 +26,14 @@
 #include <asm/page.h>
 
 struct mm_struct;
+struct cpu_suspend_ctx;
 
 extern void cpu_cache_off(void);
 extern void cpu_do_idle(void);
 extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
 extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
+extern void cpu_do_suspend(struct cpu_suspend_ctx *ptr);
+extern u64 cpu_do_resume(phys_addr_t ptr, u64 idmap_ttbr);
 
 #include <asm/memory.h>
 

arch/arm64/mm/proc.S +20 -0

index a82ae88..193bf98 100644
@@ -80,6 +80,70 @@ ENTRY(cpu_do_idle)
 	ret
 ENDPROC(cpu_do_idle)
 
+#ifdef CONFIG_ARM_CPU_SUSPEND
+/**
+ * cpu_do_suspend - save CPU registers context
+ * x0: virtual address of context pointer
+ */
+ENTRY(cpu_do_suspend)
+	mrs	x1, tpidr_el0
+	str	x1, [x0, #CPU_CTX_TPIDR_EL0]
+	mrs	x2, tpidrro_el0
+	str	x2, [x0, #CPU_CTX_TPIDRRO_EL0]
+	mrs	x3, contextidr_el1
+	str	x3, [x0, #CPU_CTX_CTXIDR_EL1]
+	mrs	x4, mair_el1
+	str	x4, [x0, #CPU_CTX_MAIR_EL1]
+	mrs	x5, cpacr_el1
+	str	x5, [x0, #CPU_CTX_CPACR_EL1]
+	mrs	x6, ttbr1_el1
+	str	x6, [x0, #CPU_CTX_TTBR1_EL1]
+	mrs	x7, tcr_el1
+	str	x7, [x0, #CPU_CTX_TCR_EL1]

Quoted 8 lines

arch/arm64/mm/proc.S ENTRY(cpu_do_idle) · line 108

Quoted 6 lines

arch/arm64/mm/proc.S +6 -0

+	mrs	x8, vbar_el1
+	str	x8, [x0, #CPU_CTX_VBAR_EL1]
+	mrs	x9, sctlr_el1
+	str	x9, [x0, #CPU_CTX_SCTLR_EL1]
+	ret
+ENDPROC(cpu_do_suspend)

Can you read all the registers a once and do some stp to save them?

Yes, absolutely. In a way the store pair will require an assumption on the context structure layout - eg:

	mrs	x1, tpidr_el0
	mrs	x2, tpidrro_el0
	stp	x1, x2, [x0, #CPU_CTX_TPIDR_EL0]

implicitly assumes that the storage for TPIDR_EL0 and TPIDRRO_EL0 is contiguous, we can't change the layout later, but I guess we can live with that.

Quoted 38 lines

Quoted 25 lines

arch/arm64/mm/proc.S +25 -0

+/**
+ * cpu_do_resume - registers layout should match the corresponding
+ *                 cpu_do_suspend call
+ *
+ * x0: Physical address of context pointer
+ * x1: Should contain the physical address of identity map page tables
+ *     used to turn on the MMU and complete context restore
+ *
+ * Returns:
+ *	sctlr value in x0
+ */
+ENTRY(cpu_do_resume)
+	tlbi	vmalle1is	// make sure tlb entries are invalid
+	ldr	x2, [x0, #CPU_CTX_TPIDR_EL0]
+	msr	tpidr_el0, x2
+	ldr	x3, [x0, #CPU_CTX_TPIDRRO_EL0]
+	msr	tpidrro_el0, x3
+	ldr	x4, [x0, #CPU_CTX_CTXIDR_EL1]
+	msr	contextidr_el1, x4
+	ldr	x5, [x0, #CPU_CTX_MAIR_EL1]
+	msr	mair_el1, x5
+	ldr	x6, [x0, #CPU_CTX_CPACR_EL1]
+	msr	cpacr_el1, x6
+	msr	ttbr0_el1, x1
+	ldr	x7, [x0, #CPU_CTX_TTBR1_EL1]

arch/arm64/mm/proc.S ENTRY(cpu_do_idle) · line 144

Quoted 10 lines

arch/arm64/mm/proc.S +10 -0

+	msr	ttbr1_el1, x7
+	ldr	x8, [x0, #CPU_CTX_TCR_EL1]
+	msr	tcr_el1, x8
+	ldr	x9, [x0, #CPU_CTX_VBAR_EL1]
+	msr	vbar_el1, x9
+	ldr	x0, [x0, #CPU_CTX_SCTLR_EL1]
+	isb
+	dsb	sy
+	ret
+ENDPROC(cpu_do_resume)

Same here, use ldp.

Quoted 1 line

BTW, do we need the DSB here or just the ISB?

A dsb is required to ensure that the tlb invalidate has completed, I think it is mandatory from an architectural standpoint but please correct me if I am wrong.

Quoted 84 lines · Lorenzo Pieralisi

Quoted 67 lines · Catalin Marinas

Quoted 66 lines · Lorenzo Pieralisi

Power management software requires the kernel to save and restore CPU registers while going through suspend and resume operations triggered by kernel subsystems like CPU idle and suspend to RAM.

This patch implements code that provides save and restore mechanism for the arm v8 implementation. Memory for the context is passed as parameter to both cpu_do_suspend and cpu_do_resume functions, and allows the callers to implement context allocation as they deem fit.

The registers that are saved and restored correspond to the registers actually required by the kernel to be up and running and is by no means a complete save and restore of the entire v8 register set.

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 arch/arm64/include/asm/proc-fns.h |  3 ++
 arch/arm64/mm/proc.S              | 64 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 67 insertions(+)

arch/arm64/include/asm/proc-fns.h +3 -0

index 7cdf466..0c657bb 100644
@@ -26,11 +26,14 @@
 #include <asm/page.h>
 
 struct mm_struct;
+struct cpu_suspend_ctx;
 
 extern void cpu_cache_off(void);
 extern void cpu_do_idle(void);
 extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
 extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
+extern void cpu_do_suspend(struct cpu_suspend_ctx *ptr);
+extern u64 cpu_do_resume(phys_addr_t ptr, u64 idmap_ttbr);
 
 #include <asm/memory.h>
 

arch/arm64/mm/proc.S +20 -0

index a82ae88..193bf98 100644
@@ -80,6 +80,70 @@ ENTRY(cpu_do_idle)
 	ret
 ENDPROC(cpu_do_idle)
 
+#ifdef CONFIG_ARM_CPU_SUSPEND
+/**
+ * cpu_do_suspend - save CPU registers context
+ * x0: virtual address of context pointer
+ */
+ENTRY(cpu_do_suspend)
+	mrs	x1, tpidr_el0
+	str	x1, [x0, #CPU_CTX_TPIDR_EL0]
+	mrs	x2, tpidrro_el0
+	str	x2, [x0, #CPU_CTX_TPIDRRO_EL0]
+	mrs	x3, contextidr_el1
+	str	x3, [x0, #CPU_CTX_CTXIDR_EL1]
+	mrs	x4, mair_el1
+	str	x4, [x0, #CPU_CTX_MAIR_EL1]
+	mrs	x5, cpacr_el1
+	str	x5, [x0, #CPU_CTX_CPACR_EL1]
+	mrs	x6, ttbr1_el1
+	str	x6, [x0, #CPU_CTX_TTBR1_EL1]
+	mrs	x7, tcr_el1
+	str	x7, [x0, #CPU_CTX_TCR_EL1]

Quoted 8 lines

arch/arm64/mm/proc.S ENTRY(cpu_do_idle) · line 108

Quoted 6 lines

arch/arm64/mm/proc.S +6 -0

+	mrs	x8, vbar_el1
+	str	x8, [x0, #CPU_CTX_VBAR_EL1]
+	mrs	x9, sctlr_el1
+	str	x9, [x0, #CPU_CTX_SCTLR_EL1]
+	ret
+ENDPROC(cpu_do_suspend)

Can you read all the registers a once and do some stp to save them?

Yes, absolutely. In a way the store pair will require an assumption on the context structure layout - eg:

	mrs	x1, tpidr_el0
	mrs	x2, tpidrro_el0
	stp	x1, x2, [x0, #CPU_CTX_TPIDR_EL0]

Quoted 3 lines

implicitly assumes that the storage for TPIDR_EL0 and TPIDRRO_EL0 is contiguous, we can't change the layout later, but I guess we can live with that.

Do we need to access the individual saved registers from this structure, outside the suspend/resume code? Otherwise we could simply have a plain array to save the registers.

Quoted 38 lines

Quoted 38 lines

Quoted 25 lines

arch/arm64/mm/proc.S +25 -0

+/**
+ * cpu_do_resume - registers layout should match the corresponding
+ *                 cpu_do_suspend call
+ *
+ * x0: Physical address of context pointer
+ * x1: Should contain the physical address of identity map page tables
+ *     used to turn on the MMU and complete context restore
+ *
+ * Returns:
+ *	sctlr value in x0
+ */
+ENTRY(cpu_do_resume)
+	tlbi	vmalle1is	// make sure tlb entries are invalid
+	ldr	x2, [x0, #CPU_CTX_TPIDR_EL0]
+	msr	tpidr_el0, x2
+	ldr	x3, [x0, #CPU_CTX_TPIDRRO_EL0]
+	msr	tpidrro_el0, x3
+	ldr	x4, [x0, #CPU_CTX_CTXIDR_EL1]
+	msr	contextidr_el1, x4
+	ldr	x5, [x0, #CPU_CTX_MAIR_EL1]
+	msr	mair_el1, x5
+	ldr	x6, [x0, #CPU_CTX_CPACR_EL1]
+	msr	cpacr_el1, x6
+	msr	ttbr0_el1, x1
+	ldr	x7, [x0, #CPU_CTX_TTBR1_EL1]

arch/arm64/mm/proc.S ENTRY(cpu_do_idle) · line 144

Quoted 10 lines

arch/arm64/mm/proc.S +10 -0

+	msr	ttbr1_el1, x7
+	ldr	x8, [x0, #CPU_CTX_TCR_EL1]
+	msr	tcr_el1, x8
+	ldr	x9, [x0, #CPU_CTX_VBAR_EL1]
+	msr	vbar_el1, x9
+	ldr	x0, [x0, #CPU_CTX_SCTLR_EL1]
+	isb
+	dsb	sy
+	ret
+ENDPROC(cpu_do_resume)

Same here, use ldp.

Quoted 5 lines

Quoted 1 line

BTW, do we need the DSB here or just the ISB?

A dsb is required to ensure that the tlb invalidate has completed, I think it is mandatory from an architectural standpoint but please correct me if I am wrong.

Yes, it's needed for that (though usually it comes before isb, but in this case the MMU is disabled anyway, so it doesn't matter).

Kernel subsystems like CPU idle and suspend to RAM require a generic mechanism to suspend a processor, save its context and put it into a quiescent state. The cpu_{suspend}/{resume} implementation provides such a framework through a kernel interface allowing to save/restore registers, flush the context to DRAM and suspend/resume to/from low-power states where processor context may be lost.

Different SoCs might require different operations to be carried out before a power down request is committed. For this reason the kernel allows the caller of cpu_suspend to provide a function pointer (fn in the cpu_suspend prototype below),

int cpu_suspend(unsigned long arg, int (*fn)(unsigned long));

called suspend finisher, that is executed after the context is saved and flushed to DRAM, so that SoC/platform specific operations can be carried out before issuing power down commands.

Context memory is allocated on the stack, whose address is stashed in a per-cpu variable to keep track of it and passed to core functions that save/restore the registers required by the architecture.

Even though, upon successful execution, the cpu_suspend function shuts down the suspending processor, the warm boot resume mechanism, based on the cpu_resume function, makes the resume path operate as a cpu_suspend function return, so that cpu_suspend can be treated as a C function by the caller, which simplifies coding the PM drivers that rely on the cpu_suspend API.

Upon context save, the minimal amount of memory is flushed to DRAM so that it can be retrieved when the MMU is off and caches are not searched.

The suspend finisher, depending on the required operations (eg CPU vs Cluster shutdown) is in charge of flushing the cache hierarchy either implicitly (by calling firmware implementations like PSCI) or explicitly by executing the required cache maintainance functions.

Quoted 29 lines · Lorenzo Pieralisi

Kernel subsystems like CPU idle and suspend to RAM require a generic mechanism to suspend a processor, save its context and put it into a quiescent state. The cpu_{suspend}/{resume} implementation provides such a framework through a kernel interface allowing to save/restore registers, flush the context to DRAM and suspend/resume to/from low-power states where processor context may be lost.

Different SoCs might require different operations to be carried out before a power down request is committed. For this reason the kernel allows the caller of cpu_suspend to provide a function pointer (fn in the cpu_suspend prototype below),

int cpu_suspend(unsigned long arg, int (*fn)(unsigned long));

called suspend finisher, that is executed after the context is saved and flushed to DRAM, so that SoC/platform specific operations can be carried out before issuing power down commands.

Context memory is allocated on the stack, whose address is stashed in a per-cpu variable to keep track of it and passed to core functions that save/restore the registers required by the architecture.

Even though, upon successful execution, the cpu_suspend function shuts down the suspending processor, the warm boot resume mechanism, based on the cpu_resume function, makes the resume path operate as a cpu_suspend function return, so that cpu_suspend can be treated as a C function by the caller, which simplifies coding the PM drivers that rely on the cpu_suspend API.

Quoted 7 lines

Upon context save, the minimal amount of memory is flushed to DRAM so that it can be retrieved when the MMU is off and caches are not searched.

The suspend finisher, depending on the required operations (eg CPU vs Cluster shutdown) is in charge of flushing the cache hierarchy either implicitly (by calling firmware implementations like PSCI) or explicitly by executing the required cache maintainance functions.

As we discussed, I would like the finisher argument to cpu_suspend() to be removed and just use the default cpu_operations.cpu_suspend (currently smp_operations) which is populated from DT and uses PSCI as the default finisher. The cpuidle drivers can still pass arguments that would make their way into the PSCI CPU_SUSPEND call (like how deep to go) but I would like to avoid each cpuidle driver implementing a finisher that does the PSCI call.

If PSCI is not available, the cpuidle driver can register a different cpu_suspend method.

To enable the suspend infrastructure for the ARM64 kernel the corresponding Kconfig and Makefile entries must be updated.

This patch adds a menu entry for power management options and entries to enable newly added suspend/resume implementation.

Makefile changes add appropriate entries to include corresponding files in the kernel image.

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 arch/arm64/Kconfig         | 12 ++++++++++++
 arch/arm64/kernel/Makefile |  1 +
 2 files changed, 13 insertions(+)

arch/arm64/Kconfig +0 -0

index 5855519..827d95e 100644
@@ -272,6 +272,18 @@ config SYSVIPC_COMPAT
 
 endmenu

Quoted 23 lines · Lorenzo Pieralisi

To enable the suspend infrastructure for the ARM64 kernel the corresponding Kconfig and Makefile entries must be updated.

This patch adds a menu entry for power management options and entries to enable newly added suspend/resume implementation.

Makefile changes add appropriate entries to include corresponding files in the kernel image.

Signed-off-by Lorenzo Pieralisi <[email protected]>

---
 arch/arm64/Kconfig         | 12 ++++++++++++
 arch/arm64/kernel/Makefile |  1 +
 2 files changed, 13 insertions(+)

arch/arm64/Kconfig +0 -0

index 5855519..827d95e 100644
@@ -272,6 +272,18 @@ config SYSVIPC_COMPAT
 
 endmenu
 

arch/arm64/Kconfig config SYSVIPC_COMPAT · line 283

Quoted 9 lines

arch/arm64/Kconfig +9 -0

+menu "Power management options"
+
+source "kernel/power/Kconfig"
+
+config ARCH_SUSPEND_POSSIBLE
+	def_bool y
+
+config ARM_CPU_SUSPEND
+	def_bool y

I think we should call this ARM64_CPU_SUSPEND. The cpuidle drivers need to be modified anyway since things like set_cr(), scu_power_mode() etc. no longer apply. If a driver supports both, that's great, it can select both ARM and ARM64.

Longer term, I would like a generic cpuidle driver for PSCI with DT bindings for describing the sleep states, target residency (not sure how this would look like yet).