ARM: OMAP2+: AM43x PRCM basic support

PATCH Superseded Afzal Mohammed 3 participants 15 messages Oct 1, 2013 – Oct 10, 2013

Subsystems (6)

Arm (32-bit) Arm sub-architectures OMAP2+ support OMAP clock framework support +2 more subsystems

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Afzal Mohammed

author

2013-10-01 07:04 UTC #0 lore raw

v5 cover ARM: OMAP2+: AM43x PRCM basic support

Hi Paul, Benoit, Tony,

This series adds PRCM support (except clock tree) for AM43x SoC's. Please consider this for inclusion in the coming merge window.

Patch 02/11 "ARM: OMAP2+: hwmod: AM335x/AM43x: move common data" may not reach mailing lists due to bigger size, this series is also present @git://gitorious.org/x0148406-public/linux-kernel.git tags/am43x-prcm-v5

Compared to v4, only change is in fixing the powerdomain data.

Major changes compared to rfc v3:
1. All register offsets properly taken care for AM43x (with rfc v3, a couple of issues was detected while testing on pre-silicon)
2. There were two patches for common hwmod data movement (one for interconnect and other for ip block data), both were combined to have a cleaner series that is bisectable.
3. Cleaner seperation of common data

Major changes compared to v2 (v3 was only an rfc for current approach):
1. omap_hwmod_33xx_43xx_interconnect_data.c has the common interconnect ocp's structs shared between AM335x and AM43x
2. omap_hwmod_33xx_43xx_ipblock_data.c has the common hwmod structs shared between AM335x and AM43x
3. Instances where clock domain or clock topology has changed in the few cases, have separate structures for AM335x and AM43x
4. To handle scenarios where register offsets are different, they are dynamically init-ed in omap_hwmod_33xx_43xx_ipblock_data.c
5. Register offsets for hwmod's that are present either in AM335x or AM43x are updated statically in omap_hwmod_33xx_data.c or omap_hwmod_43xx_data.c as that was cleaner.
6. Remove the change that re-introduces SW_SLEEP for OMAP4, this will be taken care separately.

This series has been boot tested on pre-silicon platform with the help of Tero's DT clock tree conversion series. This series has been tested on AM335x-EVM too.

Additional details:
AM43x reuses most of the IP's from AM335x, as that is the case, much of the AM335x hwmod data is reused. As AM43x PRCM register layout differs from AM335x and is similar to OMAP4, power domain, clock domain & hwmod operations are reused from OMAP4. Currently there is no public TRM available for AM43x.

Changes based on: v3.12-rc2

Regards
Afzal

Afzal Mohammed (7):
ARM: OMAP2+: hwmod: AM335x/AM43x: move common data
ARM: OMAP2+: hwmod: AM335x: runtime register update
ARM: OMAP2+: hwmod: AM335x: remove static register offs
ARM: OMAP2+: PRCM: AM43x definitions
ARM: OMAP2+: hwmod: AM43x support
ARM: OMAP2+: hwmod: AM43x operations
ARM: OMAP2+: AM43x: PRCM kbuild

Ambresh K (3):
ARM: OMAP2+: PM: AM43x powerdomain data
ARM: OMAP2+: CM: AM43x clockdomain data
ARM: OMAP2+: AM43x PRCM init

Ankur Kishore (1):
ARM: OMAP2+: CM: cm_inst offset s16->u16

 arch/arm/mach-omap2/Makefile                       |    9 +-
 arch/arm/mach-omap2/clockdomain.h                  |    4 +-
 arch/arm/mach-omap2/clockdomains43xx_data.c        |  196 ++
 arch/arm/mach-omap2/cm33xx.c                       |   16 +-
 arch/arm/mach-omap2/cm33xx.h                       |   12 +-
 arch/arm/mach-omap2/cminst44xx.c                   |   29 +-
 arch/arm/mach-omap2/cminst44xx.h                   |   26 +-
 arch/arm/mach-omap2/io.c                           |    6 +
 arch/arm/mach-omap2/omap_hwmod.c                   |    8 +
 arch/arm/mach-omap2/omap_hwmod.h                   |    1 +
 .../mach-omap2/omap_hwmod_33xx_43xx_common_data.h  |  163 ++
 .../omap_hwmod_33xx_43xx_interconnect_data.c       |  643 +++++++
 .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 1456 +++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c         | 1966 +-------------------
 arch/arm/mach-omap2/omap_hwmod_43xx_data.c         |  622 +++++++
 arch/arm/mach-omap2/powerdomain.h                  |    1 +
 arch/arm/mach-omap2/powerdomains43xx_data.c        |  136 ++
 arch/arm/mach-omap2/prcm43xx.h                     |  141 ++
 18 files changed, 3432 insertions(+), 2003 deletions(-)
 create mode 100644 arch/arm/mach-omap2/clockdomains43xx_data.c
 create mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
 create mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
 create mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
 create mode 100644 arch/arm/mach-omap2/omap_hwmod_43xx_data.c
 create mode 100644 arch/arm/mach-omap2/powerdomains43xx_data.c
 create mode 100644 arch/arm/mach-omap2/prcm43xx.h

Signature · 1 line

1.8.3.4

Afzal Mohammed

author

2013-10-01 07:06 UTC #1 lore raw

PATCH v5 1/11 ARM: OMAP2+: CM: cm_inst offset s16->u16

From: Ankur Kishore <[email protected]>

Most of the AM43x CM reg address offsets are with MSB bit '1' (on 16-bit value) leading to arithmetic miscalculations while calculating CLOCK ENABLE register's address because cm_inst field was a type of "const s16", so make it "const u16".

Also modify relevant functions so as to take care of the above.

[afzal at ti.com: fixup and cleanup]

Signed-off-by Ankur Kishore <[email protected]>

Signed-off-by Afzal Mohammed <[email protected]>

---
 arch/arm/mach-omap2/clockdomain.h |  2 +-
 arch/arm/mach-omap2/cm33xx.c      | 16 ++++++++--------
 arch/arm/mach-omap2/cm33xx.h      | 10 +++++-----
 arch/arm/mach-omap2/cminst44xx.c  | 20 ++++++++++----------
 arch/arm/mach-omap2/cminst44xx.h  | 26 +++++++++++++-------------
 5 files changed, 37 insertions(+), 37 deletions(-)

arch/arm/mach-omap2/clockdomain.h +1 -1

index 4b03394..5431b0c 100644
@@ -132,7 +132,7 @@ struct clockdomain {
 	u8 _flags;
 	const u8 dep_bit;
 	const u8 prcm_partition;
-	const s16 cm_inst;
+	const u16 cm_inst;
 	const u16 clkdm_offs;
 	struct clkdm_dep *wkdep_srcs;
 	struct clkdm_dep *sleepdep_srcs;

arch/arm/mach-omap2/cm33xx.c +8 -8

index 325a515..40a22e5 100644
@@ -48,13 +48,13 @@
 /* Private functions */
 
 /* Read a register in a CM instance */
-static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx)
+static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx)
 {
 	return __raw_readl(cm_base + inst + idx);
 }
 
 /* Write into a register in a CM */
-static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx)
+static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx)
 {
 	__raw_writel(val, cm_base + inst + idx);
 }

@@ -138,7 +138,7 @@ static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
  * @c must be the unshifted value for CLKTRCTRL - i.e., this function
  * will handle the shift itself.
  */
-static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs)
+static void _clktrctrl_write(u8 c, u16 inst, u16 cdoffs)
 {
 	u32 v;

@@ -158,7 +158,7 @@ static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs)
  * Returns true if the clockdomain referred to by (@inst, @cdoffs)
  * is in hardware-supervised idle mode, or 0 otherwise.
  */
-bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs)
+bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs)
 {
 	u32 v;

@@ -177,7 +177,7 @@ bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs)
  * Put a clockdomain referred to by (@inst, @cdoffs) into
  * hardware-supervised idle mode.  No return value.
  */
-void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs)
+void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs)
 {
 	_clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
 }

@@ -191,7 +191,7 @@ void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs)
  * software-supervised idle mode, i.e., controlled manually by the
  * Linux OMAP clockdomain code.  No return value.
  */
-void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs)
+void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs)
 {
 	_clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
 }

@@ -204,7 +204,7 @@ void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs)
  * Put a clockdomain referred to by (@inst, @cdoffs) into idle
  * No return value.
  */
-void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs)
+void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs)
 {
 	_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
 }

@@ -217,7 +217,7 @@ void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs)
  * Take a clockdomain referred to by (@inst, @cdoffs) out of idle,
  * waking it up.  No return value.
  */
-void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs)
+void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs)
 {
 	_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
 }

arch/arm/mach-omap2/cm33xx.h +5 -5

index 9d1f4fc..757320b 100644
@@ -377,11 +377,11 @@
 
 
 #ifndef __ASSEMBLER__
-extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
-extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
-extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
-extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs);
-extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs);
+bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs);
+void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs);
+void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs);
+void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs);
+void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs);
 
 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,

arch/arm/mach-omap2/cminst44xx.c +10 ~~-10~~

index f0290f5..e957222 100644
@@ -111,7 +111,7 @@ static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
 /* Public functions */
 
 /* Read a register in a CM instance */
-u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
+u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
 {
 	BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
 	       part == OMAP4430_INVALID_PRCM_PARTITION ||

@@ -120,7 +120,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
 }
 
 /* Write into a register in a CM instance */
-void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
+void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
 {
 	BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
 	       part == OMAP4430_INVALID_PRCM_PARTITION ||

@@ -129,7 +129,7 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
 }
 
 /* Read-modify-write a register in CM1. Caller must lock */
-u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
+u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst,
 				   s16 idx)
 {
 	u32 v;

@@ -142,12 +142,12 @@ u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
 	return v;
 }
 
-u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx)
+u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx)
 {
 	return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx);
 }
 
-u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx)
+u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx)
 {
 	return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx);
 }

@@ -177,7 +177,7 @@ u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
  * @c must be the unshifted value for CLKTRCTRL - i.e., this function
  * will handle the shift itself.
  */
-static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs)
+static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs)
 {
 	u32 v;

@@ -196,7 +196,7 @@ static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs)
  * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs)
  * is in hardware-supervised idle mode, or 0 otherwise.
  */
-bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs)
+bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs)
 {
 	u32 v;

@@ -216,7 +216,7 @@ bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs)
  * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
  * hardware-supervised idle mode.  No return value.
  */
-void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs)
+void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs)
 {
 	_clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs);
 }

@@ -231,7 +231,7 @@ void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs)
  * software-supervised idle mode, i.e., controlled manually by the
  * Linux OMAP clockdomain code.  No return value.
  */
-void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs)
+void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs)
 {
 	_clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs);
 }

@@ -245,7 +245,7 @@ void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs)
  * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle,
  * waking it up.  No return value.
  */
-void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs)
+void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs)
 {
 	_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs);
 }

arch/arm/mach-omap2/cminst44xx.h +13 ~~-13~~

index bd7bab8..7f56ea4 100644
@@ -11,11 +11,11 @@
 #ifndef __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
 #define __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
 
-extern bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs);
-extern void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs);
-extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs);
-extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs);
-extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
+bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs);
+void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs);
+void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs);
+void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs);
+void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs);
 extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
 extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
 					 u16 clkctrl_offs);

@@ -27,14 +27,14 @@ extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
  * In an ideal world, we would not export these low-level functions,
  * but this will probably take some time to fix properly
  */
-extern u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx);
-extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
-extern u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
-					   s16 inst, s16 idx);
-extern u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst,
-					   s16 idx);
-extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst,
-					   s16 idx);
+u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx);
+void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx);
+u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
+				   u16 inst, s16 idx);
+u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst,
+				   s16 idx);
+u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst,
+				     s16 idx);
 extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
 					   u32 mask);

Signature · 1 line

1.8.3.4

Afzal Mohammed

author

2013-10-01 07:07 UTC #2 lore raw

PATCH v5 3/11 ARM: OMAP2+: hwmod: AM335x: runtime register update

In reply to Afzal Mohammed

Most of IP's in AM335x is present on AM43x and so in those cases both will use same hwmod database (except for a few cases where clock related details differ), but there is difference w.r.t register offset between these. Update register offsets at runtime based on the SoC detected to help in sharing otherwise same hwmod.

Signed-off-by Afzal Mohammed <[email protected]>

---
 .../mach-omap2/omap_hwmod_33xx_43xx_common_data.h  |  2 +
 .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 77 ++++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c         |  1 +
 3 files changed, 80 insertions(+)

arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h +2 -0

index e873e72..a9a7902 100644
@@ -157,4 +157,6 @@ extern struct omap_hwmod_class am33xx_spi_hwmod_class;
 extern struct omap_gpio_dev_attr gpio_dev_attr;
 extern struct omap2_mcspi_dev_attr mcspi_attrib;
 
+void omap_hwmod_am33xx_reg(void);
+
 #endif

arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +77 -0

86 lines not on this page · raw message

arch/arm/mach-omap2/omap_hwmod_33xx_data.c +1 -0

index a7707ef..87cb9a8 100644
@@ -601,6 +601,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
 
 int __init am33xx_hwmod_init(void)
 {
+	omap_hwmod_am33xx_reg();
 	omap_hwmod_init();
 	return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
 }

Signature · 1 line

1.8.3.4

Afzal Mohammed

author

2013-10-01 07:07 UTC #3 lore raw

PATCH v5 4/11 ARM: OMAP2+: hwmod: AM335x: remove static register offs

In reply to Afzal Mohammed

Hwmod common to AM43x and AM335x has register offsets different. It is now updated based on SoC detection at run time, hence remove statically initialized ones.

Signed-off-by Afzal Mohammed <[email protected]>

---
 .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 57 ----------------------
 1 file changed, 57 deletions(-)

arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +0 ~~-57~~

index da40252..598f813 100644
@@ -44,7 +44,6 @@ struct omap_hwmod am33xx_l3_main_hwmod = {
 	.main_clk	= "l3_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -66,7 +65,6 @@ struct omap_hwmod am33xx_l3_instr_hwmod = {
 	.main_clk	= "l3_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -89,7 +87,6 @@ struct omap_hwmod am33xx_l4_ls_hwmod = {
 	.main_clk	= "l4ls_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -103,7 +100,6 @@ struct omap_hwmod am33xx_l4_wkup_hwmod = {
 	.flags		= (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -124,7 +120,6 @@ struct omap_hwmod am33xx_mpu_hwmod = {
 	.main_clk	= "dpll_mpu_m2_ck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -159,8 +154,6 @@ struct omap_hwmod am33xx_pruss_hwmod = {
 	.main_clk	= "pruss_ocp_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
-			.rstctrl_offs	= AM33XX_RM_PER_RSTCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -185,9 +178,6 @@ struct omap_hwmod am33xx_gfx_hwmod = {
 	.main_clk	= "gfx_fck_div_ck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
-			.rstctrl_offs	= AM33XX_RM_GFX_RSTCTRL_OFFSET,
-			.rstst_offs	= AM33XX_RM_GFX_RSTST_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -232,7 +222,6 @@ struct omap_hwmod am33xx_aes0_hwmod = {
 	.main_clk	= "aes0_fck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -258,7 +247,6 @@ struct omap_hwmod am33xx_sha0_hwmod = {
 	.main_clk	= "l3_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -277,7 +265,6 @@ struct omap_hwmod am33xx_ocmcram_hwmod = {
 	.main_clk	= "l3_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -296,7 +283,6 @@ struct omap_hwmod am33xx_smartreflex0_hwmod = {
 	.main_clk	= "smartreflex0_fck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -310,7 +296,6 @@ struct omap_hwmod am33xx_smartreflex1_hwmod = {
 	.main_clk	= "smartreflex1_fck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -352,7 +337,6 @@ struct omap_hwmod am33xx_cpgmac0_hwmod = {
 	.mpu_rt_idx	= 1,
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -387,7 +371,6 @@ struct omap_hwmod am33xx_dcan0_hwmod = {
 	.main_clk	= "dcan0_fck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -401,7 +384,6 @@ struct omap_hwmod am33xx_dcan1_hwmod = {
 	.main_clk	= "dcan1_fck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -431,7 +413,6 @@ struct omap_hwmod am33xx_elm_hwmod = {
 	.main_clk	= "l4ls_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -473,7 +454,6 @@ struct omap_hwmod am33xx_epwmss0_hwmod = {
 	.main_clk	= "l4ls_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -511,7 +491,6 @@ struct omap_hwmod am33xx_epwmss1_hwmod = {
 	.main_clk	= "l4ls_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -549,7 +528,6 @@ struct omap_hwmod am33xx_epwmss2_hwmod = {
 	.main_clk	= "l4ls_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -618,7 +596,6 @@ struct omap_hwmod am33xx_gpio1_hwmod = {
 	.main_clk	= "l4ls_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -640,7 +617,6 @@ struct omap_hwmod am33xx_gpio2_hwmod = {
 	.main_clk	= "l4ls_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -662,7 +638,6 @@ struct omap_hwmod am33xx_gpio3_hwmod = {
 	.main_clk	= "l4ls_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -695,7 +670,6 @@ struct omap_hwmod am33xx_gpmc_hwmod = {
 	.main_clk	= "l3s_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -733,7 +707,6 @@ struct omap_hwmod am33xx_i2c1_hwmod = {
 	.main_clk	= "dpll_per_m2_div4_wkupdm_ck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -749,7 +722,6 @@ struct omap_hwmod am33xx_i2c2_hwmod = {
 	.main_clk	= "dpll_per_m2_div4_ck",
 	.prcm		= {
 		.omap4 = {
-			.clkctrl_offs	= AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -765,7 +737,6 @@ struct omap_hwmod am33xx_i2c3_hwmod = {
 	.main_clk	= "dpll_per_m2_div4_ck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -798,7 +769,6 @@ struct omap_hwmod am33xx_mailbox_hwmod = {
 	.main_clk	= "l4ls_gclk",
 	.prcm = {
 		.omap4 = {
-			.clkctrl_offs	= AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -828,7 +798,6 @@ struct omap_hwmod am33xx_mcasp0_hwmod = {
 	.main_clk	= "mcasp0_fck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -842,7 +811,6 @@ struct omap_hwmod am33xx_mcasp1_hwmod = {
 	.main_clk	= "mcasp1_fck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -877,7 +845,6 @@ struct omap_hwmod am33xx_mmc0_hwmod = {
 	.main_clk	= "mmc_clk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -896,7 +863,6 @@ struct omap_hwmod am33xx_mmc1_hwmod = {
 	.main_clk	= "mmc_clk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -914,7 +880,6 @@ struct omap_hwmod am33xx_mmc2_hwmod = {
 	.main_clk	= "mmc_clk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -946,7 +911,6 @@ struct omap_hwmod am33xx_rtc_hwmod = {
 	.main_clk	= "clk_32768_ck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -981,7 +945,6 @@ struct omap_hwmod am33xx_spi0_hwmod = {
 	.main_clk	= "dpll_per_m2_div4_ck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -996,7 +959,6 @@ struct omap_hwmod am33xx_spi1_hwmod = {
 	.main_clk	= "dpll_per_m2_div4_ck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -1019,7 +981,6 @@ struct omap_hwmod am33xx_spinlock_hwmod = {
 	.main_clk	= "l4ls_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -1065,7 +1026,6 @@ struct omap_hwmod am33xx_timer1_hwmod = {
 	.main_clk	= "timer1_fck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -1078,7 +1038,6 @@ struct omap_hwmod am33xx_timer2_hwmod = {
 	.main_clk	= "timer2_fck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -1091,7 +1050,6 @@ struct omap_hwmod am33xx_timer3_hwmod = {
 	.main_clk	= "timer3_fck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -1104,7 +1062,6 @@ struct omap_hwmod am33xx_timer4_hwmod = {
 	.main_clk	= "timer4_fck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -1117,7 +1074,6 @@ struct omap_hwmod am33xx_timer5_hwmod = {
 	.main_clk	= "timer5_fck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -1130,7 +1086,6 @@ struct omap_hwmod am33xx_timer6_hwmod = {
 	.main_clk	= "timer6_fck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -1143,7 +1098,6 @@ struct omap_hwmod am33xx_timer7_hwmod = {
 	.main_clk	= "timer7_fck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -1161,7 +1115,6 @@ struct omap_hwmod am33xx_tpcc_hwmod = {
 	.main_clk	= "l3_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -1191,7 +1144,6 @@ struct omap_hwmod am33xx_tptc0_hwmod = {
 	.main_clk	= "l3_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -1206,7 +1158,6 @@ struct omap_hwmod am33xx_tptc1_hwmod = {
 	.main_clk	= "l3_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -1221,7 +1172,6 @@ struct omap_hwmod am33xx_tptc2_hwmod = {
 	.main_clk	= "l3_gclk",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -1252,7 +1202,6 @@ struct omap_hwmod am33xx_uart1_hwmod = {
 	.main_clk	= "dpll_per_m2_div4_wkupdm_ck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -1266,7 +1215,6 @@ struct omap_hwmod am33xx_uart2_hwmod = {
 	.main_clk	= "dpll_per_m2_div4_ck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -1281,7 +1229,6 @@ struct omap_hwmod am33xx_uart3_hwmod = {
 	.main_clk	= "dpll_per_m2_div4_ck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -1295,7 +1242,6 @@ struct omap_hwmod am33xx_uart4_hwmod = {
 	.main_clk	= "dpll_per_m2_div4_ck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -1309,7 +1255,6 @@ struct omap_hwmod am33xx_uart5_hwmod = {
 	.main_clk	= "dpll_per_m2_div4_ck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -1323,7 +1268,6 @@ struct omap_hwmod am33xx_uart6_hwmod = {
 	.main_clk	= "dpll_per_m2_div4_ck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

@@ -1359,7 +1303,6 @@ struct omap_hwmod am33xx_wd_timer1_hwmod = {
 	.main_clk	= "wdt1_fck",
 	.prcm		= {
 		.omap4	= {
-			.clkctrl_offs	= AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
 			.modulemode	= MODULEMODE_SWCTRL,
 		},
 	},

Signature · 1 line

1.8.3.4

Afzal Mohammed

author

2013-10-01 07:07 UTC #4 lore raw

PATCH v5 5/11 ARM: OMAP2+: PRCM: AM43x definitions

In reply to Afzal Mohammed

Add AM43x CMINST, CDOFFS, RM_RSTST & RM_RSTCTRL definitions - minimal ones that would be used.

Signed-off-by Afzal Mohammed <[email protected]>

---
 arch/arm/mach-omap2/prcm43xx.h | 141 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 141 insertions(+)
 create mode 100644 arch/arm/mach-omap2/prcm43xx.h

arch/arm/mach-omap2/prcm43xx.h new file +141 -0

new file mode 100644
index 0000000..f0636ec
@@ -0,0 +1,141 @@
+/*
+ * AM43x PRCM defines
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
+
+#define AM43XX_PRM_PARTITION				1
+#define AM43XX_CM_PARTITION				1
+
+/* PRM instances */
+#define AM43XX_PRM_OCP_SOCKET_INST			0x0000
+#define AM43XX_PRM_MPU_INST				0x0300
+#define AM43XX_PRM_GFX_INST				0x0400
+#define AM43XX_PRM_RTC_INST				0x0500
+#define AM43XX_PRM_TAMPER_INST				0x0600
+#define AM43XX_PRM_CEFUSE_INST				0x0700
+#define AM43XX_PRM_PER_INST				0x0800
+#define AM43XX_PRM_WKUP_INST				0x2000
+#define AM43XX_PRM_DEVICE_INST				0x4000
+
+/* RM RSTCTRL offsets */
+#define AM43XX_RM_PER_RSTCTRL_OFFSET			0x0010
+#define AM43XX_RM_GFX_RSTCTRL_OFFSET			0x0010
+#define AM43XX_RM_WKUP_RSTCTRL_OFFSET			0x0010
+
+/* RM RSTST offsets */
+#define AM43XX_RM_GFX_RSTST_OFFSET			0x0014
+#define AM43XX_RM_WKUP_RSTST_OFFSET			0x0014
+
+/* CM instances */
+#define AM43XX_CM_WKUP_INST				0x2800
+#define AM43XX_CM_DEVICE_INST				0x4100
+#define AM43XX_CM_DPLL_INST				0x4200
+#define AM43XX_CM_MPU_INST				0x8300
+#define AM43XX_CM_GFX_INST				0x8400
+#define AM43XX_CM_RTC_INST				0x8500
+#define AM43XX_CM_TAMPER_INST				0x8600
+#define AM43XX_CM_CEFUSE_INST				0x8700
+#define AM43XX_CM_PER_INST				0x8800
+
+/* CD offsets */
+#define AM43XX_CM_WKUP_L3_AON_CDOFFS			0x0000
+#define AM43XX_CM_WKUP_L3S_TSC_CDOFFS			0x0100
+#define AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS		0x0200
+#define AM43XX_CM_WKUP_WKUP_CDOFFS			0x0300
+#define AM43XX_CM_MPU_MPU_CDOFFS			0x0000
+#define AM43XX_CM_GFX_GFX_L3_CDOFFS			0x0000
+#define AM43XX_CM_RTC_RTC_CDOFFS			0x0000
+#define AM43XX_CM_TAMPER_TAMPER_CDOFFS			0x0000
+#define AM43XX_CM_CEFUSE_CEFUSE_CDOFFS			0x0000
+#define AM43XX_CM_PER_L3_CDOFFS				0x0000
+#define AM43XX_CM_PER_L3S_CDOFFS			0x0200
+#define AM43XX_CM_PER_ICSS_CDOFFS			0x0300
+#define AM43XX_CM_PER_L4LS_CDOFFS			0x0400
+#define AM43XX_CM_PER_EMIF_CDOFFS			0x0700
+#define AM43XX_CM_PER_DSS_CDOFFS			0x0a00
+#define AM43XX_CM_PER_CPSW_CDOFFS			0x0b00
+#define AM43XX_CM_PER_OCPWP_L3_CDOFFS			0x0c00
+
+/* CLK CTRL offsets */
+#define AM43XX_CM_PER_UART1_CLKCTRL_OFFSET		0x0580
+#define AM43XX_CM_PER_UART2_CLKCTRL_OFFSET		0x0588
+#define AM43XX_CM_PER_UART3_CLKCTRL_OFFSET		0x0590
+#define AM43XX_CM_PER_UART4_CLKCTRL_OFFSET		0x0598
+#define AM43XX_CM_PER_UART5_CLKCTRL_OFFSET		0x05a0
+#define AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET		0x0428
+#define AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET		0x0430
+#define AM43XX_CM_PER_ELM_CLKCTRL_OFFSET		0x0468
+#define AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET		0x0438
+#define AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET		0x0440
+#define AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET		0x0448
+#define AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET		0x0478
+#define AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET		0x0480
+#define AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET		0x0488
+#define AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET		0x04a8
+#define AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET		0x04b0
+#define AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET		0x04b8
+#define AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET		0x04c0
+#define AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET		0x04c8
+#define AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET		0x0500
+#define AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET		0x0508
+#define AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET		0x0528
+#define AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET		0x0530
+#define AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET		0x0538
+#define AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET		0x0540
+#define AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET		0x0548
+#define AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET		0x0550
+#define AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET		0x0558
+#define AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET		0x0228
+#define AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET		0x0360
+#define AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET	0x0350
+#define AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET	0x0358
+#define AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET		0x0348
+#define AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET		0x0328
+#define AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET		0x0340
+#define AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET		0x0368
+#define AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET		0x0120
+#define AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET		0x0338
+#define AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET		0x0220
+#define AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET		0x0020
+#define AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET		0x0248
+#define AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET		0x0220
+#define AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET		0x0238
+#define AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET		0x0240
+#define AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET		0x0420
+#define AM43XX_CM_PER_L3_CLKCTRL_OFFSET			0x0020
+#define AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET		0x0078
+#define AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET		0x0080
+#define AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET		0x0088
+#define AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET		0x0090
+#define AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET		0x0b20
+#define AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET		0x0320
+#define AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET		0x0020
+#define AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET		0x00a0
+#define AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET		0x0020
+#define AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET		0x0040
+#define AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET		0x0050
+#define AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET		0x0058
+#define AM43XX_CM_PER_AES0_CLKCTRL_OFFSET		0x0028
+#define AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET		0x0560
+#define AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET		0x0568
+#define AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET		0x0570
+#define AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET		0x0578
+#define AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET		0x0230
+#define AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET		0x0450
+#define AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET		0x0458
+#define AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET		0x0460
+#define AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET		0x0510
+#define AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET		0x0518
+#define AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET		0x0520
+#define AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET		0x0490
+#define AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET		0x0498
+
+#endif

Signature · 1 line

1.8.3.4

Afzal Mohammed

author

2013-10-01 07:07 UTC #5 lore raw

PATCH v5 6/11 ARM: OMAP2+: PM: AM43x powerdomain data

In reply to Afzal Mohammed

From: Ambresh K <[email protected]>

Add the data file to describe all power domains in AM43x SoC. OMAP4 powerdomain operations is being reused here.

Signed-off-by Ambresh K <[email protected]>

Signed-off-by Afzal Mohammed <[email protected]>

---
 arch/arm/mach-omap2/powerdomain.h           |   1 +
 arch/arm/mach-omap2/powerdomains43xx_data.c | 136 ++++++++++++++++++++++++++++
 2 files changed, 137 insertions(+)
 create mode 100644 arch/arm/mach-omap2/powerdomains43xx_data.c

arch/arm/mach-omap2/powerdomain.h +1 -0

index baf3d8b..da5a59a 100644
@@ -257,6 +257,7 @@ extern void am33xx_powerdomains_init(void);
 extern void omap44xx_powerdomains_init(void);
 extern void omap54xx_powerdomains_init(void);
 extern void dra7xx_powerdomains_init(void);
+void am43xx_powerdomains_init(void);
 
 extern struct pwrdm_ops omap2_pwrdm_operations;
 extern struct pwrdm_ops omap3_pwrdm_operations;

arch/arm/mach-omap2/powerdomains43xx_data.c new file +136 -0

136 lines not on this page · raw message

Signature · 1 line

1.8.3.4

Afzal Mohammed

author

2013-10-01 07:07 UTC #6 lore raw

PATCH v5 7/11 ARM: OMAP2+: CM: AM43x clockdomain data

In reply to Afzal Mohammed

From: Ambresh K <[email protected]>

Add the data file to describe clock domains in AM43x SoC. OMAP4 clockdomain operations is being reused here.

Signed-off-by Ambresh K <[email protected]>

Signed-off-by Afzal Mohammed <[email protected]>

---
 arch/arm/mach-omap2/clockdomain.h           |   2 +
 arch/arm/mach-omap2/clockdomains43xx_data.c | 196 ++++++++++++++++++++++++++++
 arch/arm/mach-omap2/cminst44xx.c            |   9 ++
 3 files changed, 207 insertions(+)
 create mode 100644 arch/arm/mach-omap2/clockdomains43xx_data.c

arch/arm/mach-omap2/clockdomain.h +2 -0

index 5431b0c..f17f006 100644
@@ -218,6 +218,7 @@ extern void __init am33xx_clockdomains_init(void);
 extern void __init omap44xx_clockdomains_init(void);
 extern void __init omap54xx_clockdomains_init(void);
 extern void __init dra7xx_clockdomains_init(void);
+void am43xx_clockdomains_init(void);
 
 extern void clkdm_add_autodeps(struct clockdomain *clkdm);
 extern void clkdm_del_autodeps(struct clockdomain *clkdm);

@@ -226,6 +227,7 @@ extern struct clkdm_ops omap2_clkdm_operations;
 extern struct clkdm_ops omap3_clkdm_operations;
 extern struct clkdm_ops omap4_clkdm_operations;
 extern struct clkdm_ops am33xx_clkdm_operations;
+extern struct clkdm_ops am43xx_clkdm_operations;
 
 extern struct clkdm_dep gfx_24xx_wkdeps[];
 extern struct clkdm_dep dsp_24xx_wkdeps[];

arch/arm/mach-omap2/clockdomains43xx_data.c new file +196 -0

196 lines not on this page · raw message

arch/arm/mach-omap2/cminst44xx.c +9 -0

index e957222..731ca13 100644
@@ -483,3 +483,12 @@ struct clkdm_ops omap4_clkdm_operations = {
 	.clkdm_clk_enable	= omap4_clkdm_clk_enable,
 	.clkdm_clk_disable	= omap4_clkdm_clk_disable,
 };
+
+struct clkdm_ops am43xx_clkdm_operations = {
+	.clkdm_sleep		= omap4_clkdm_sleep,
+	.clkdm_wakeup		= omap4_clkdm_wakeup,
+	.clkdm_allow_idle	= omap4_clkdm_allow_idle,
+	.clkdm_deny_idle	= omap4_clkdm_deny_idle,
+	.clkdm_clk_enable	= omap4_clkdm_clk_enable,
+	.clkdm_clk_disable	= omap4_clkdm_clk_disable,
+};

Signature · 1 line

1.8.3.4

Afzal Mohammed

author

2013-10-01 07:08 UTC #7 lore raw

PATCH v5 8/11 ARM: OMAP2+: hwmod: AM43x support

In reply to Afzal Mohammed

Add hwmod support for IP's that are present in AM43x, but not in AM335x. AM43x additional ones added here are,
1. synctimer
2. timer8-11
3. ehrpwm3-5
4. spi2-4
5. gpio4-5

AM43x pruss interconnect which is different as compared to AM335x, has been taken care.

And register offsets for same hwmod's shared with AM335x is different, AM43x register offsets are updated appropriately.

ocp clock of those in l4_wkup is fed from "sys_clkin_ck" instead of "dpll_core_m4_div2_ck", so "ocpif" for those in AM43x l4_wkup has been added seperately.

hwmod's has been added for those that have main clock (wkup_m3, control, gpio0) and clock domain (l4_hs) different from AM335x. debugss and adc_tsc that have different clocks and clockdomains repectively has not been added due to the reasons mentioned below.

AM43x also has IP's like qspi, hdq1w, vpfe, des, rng, usb, dss, debugss, adc_tsc. These are not handled here due to both/either of following reasons,
1. To avoid churn; most of them don't have DT bindings, which would necessitate adding address space in hwmod, which any way would have to be removed once DT bindings happen with driver support.
2. patches would come in from sources other than the author

Signed-off-by Afzal Mohammed <[email protected]>

---
 arch/arm/mach-omap2/omap_hwmod.h                   |   1 +
 .../mach-omap2/omap_hwmod_33xx_43xx_common_data.h  |   1 +
 .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c |  74 +++
 arch/arm/mach-omap2/omap_hwmod_43xx_data.c         | 622 +++++++++++++++++++++
 4 files changed, 698 insertions(+)
 create mode 100644 arch/arm/mach-omap2/omap_hwmod_43xx_data.c

arch/arm/mach-omap2/omap_hwmod.h +1 -0

index d02acf9..0f97d63 100644
@@ -752,6 +752,7 @@ extern int omap44xx_hwmod_init(void);
 extern int omap54xx_hwmod_init(void);
 extern int am33xx_hwmod_init(void);
 extern int dra7xx_hwmod_init(void);
+int am43xx_hwmod_init(void);
 
 extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);

arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h +1 -0

index a9a7902..130332c 100644
@@ -158,5 +158,6 @@ extern struct omap_gpio_dev_attr gpio_dev_attr;
 extern struct omap2_mcspi_dev_attr mcspi_attrib;
 
 void omap_hwmod_am33xx_reg(void);
+void omap_hwmod_am43xx_reg(void);
 
 #endif

arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +74 -0

83 lines not on this page · raw message

arch/arm/mach-omap2/omap_hwmod_43xx_data.c new file +622 -0

622 lines not on this page · raw message

Signature · 1 line

1.8.3.4

Afzal Mohammed

author

2013-10-01 07:08 UTC #8 lore raw

PATCH v5 9/11 ARM: OMAP2+: hwmod: AM43x operations

In reply to Afzal Mohammed

Reuse OMAP4 operations on AM43x.

Context related ops are not used on AM43x, as this would not add value when using DT and AM43x is DT only boot. This additionally helps not to add context register offset for each hwmod.

Signed-off-by Ambresh K <[email protected]>

Signed-off-by Afzal Mohammed <[email protected]>

---
 arch/arm/mach-omap2/omap_hwmod.c | 8 ++++++++
 1 file changed, 8 insertions(+)

arch/arm/mach-omap2/omap_hwmod.c +8 -0

index d9ee0ff..aa593da 100644
@@ -4125,6 +4125,14 @@ void __init omap_hwmod_init(void)
 		soc_ops.init_clkdm = _init_clkdm;
 		soc_ops.update_context_lost = _omap4_update_context_lost;
 		soc_ops.get_context_lost = _omap4_get_context_lost;
+	} else if (soc_is_am43xx()) {
+		soc_ops.enable_module = _omap4_enable_module;
+		soc_ops.disable_module = _omap4_disable_module;
+		soc_ops.wait_target_ready = _omap4_wait_target_ready;
+		soc_ops.assert_hardreset = _omap4_assert_hardreset;
+		soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
+		soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
+		soc_ops.init_clkdm = _init_clkdm;
 	} else if (soc_is_am33xx()) {
 		soc_ops.enable_module = _am33xx_enable_module;
 		soc_ops.disable_module = _am33xx_disable_module;

Signature · 1 line

1.8.3.4

Afzal Mohammed

author

2013-10-01 07:08 UTC #9 lore raw

PATCH v5 10/11 ARM: OMAP2+: AM43x: PRCM kbuild

In reply to Afzal Mohammed

Build AM43x power domain, clock domain and hwmod data.

Many of AM43x IP's and interconnects are similar as that in AM335x, hence AM335x hwmod data is being reused with necessary changes.

Earlier the plan was to reuse AM335x specific PRCM code, but as AM43x PRCM register layout is much similar to OMAP4/5, AM335x PRCM is divorced and instead married with OMAP4/5 PRCM for AM43x.

Signed-off-by Afzal Mohammed <[email protected]>

---
 arch/arm/mach-omap2/Makefile | 7 ++++++-
 arch/arm/mach-omap2/cm33xx.h | 2 +-
 2 files changed, 7 insertions(+), 2 deletions(-)

arch/arm/mach-omap2/Makefile +6 -1

index 0746494..cb7b527 100644
@@ -112,13 +112,13 @@ obj-$(CONFIG_ARCH_OMAP2)		+= prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= vc3xxx_data.o vp3xxx_data.o
 obj-$(CONFIG_SOC_AM33XX)		+= prm33xx.o cm33xx.o
-obj-$(CONFIG_SOC_AM43XX)		+= prm33xx.o cm33xx.o
 omap-prcm-4-5-common			=  cminst44xx.o cm44xx.o prm44xx.o \
 					   prcm_mpu44xx.o prminst44xx.o \
 					   vc44xx_data.o vp44xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(omap-prcm-4-5-common)
 obj-$(CONFIG_SOC_OMAP5)			+= $(omap-prcm-4-5-common)
 obj-$(CONFIG_SOC_DRA7XX)		+= $(omap-prcm-4-5-common)
+obj-$(CONFIG_SOC_AM43XX)		+= $(omap-prcm-4-5-common)
 
 # OMAP voltage domains
 voltagedomain-common			:= voltage.o vc.o vp.o

@@ -146,6 +146,7 @@ obj-$(CONFIG_ARCH_OMAP4)		+= powerdomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(powerdomain-common)
 obj-$(CONFIG_SOC_AM33XX)		+= powerdomains33xx_data.o
 obj-$(CONFIG_SOC_AM43XX)		+= $(powerdomain-common)
+obj-$(CONFIG_SOC_AM43XX)		+= powerdomains43xx_data.o
 obj-$(CONFIG_SOC_OMAP5)			+= $(powerdomain-common)
 obj-$(CONFIG_SOC_OMAP5)			+= powerdomains54xx_data.o
 obj-$(CONFIG_SOC_DRA7XX)		+= $(powerdomain-common)

@@ -165,6 +166,7 @@ obj-$(CONFIG_ARCH_OMAP4)		+= clockdomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(clockdomain-common)
 obj-$(CONFIG_SOC_AM33XX)		+= clockdomains33xx_data.o
 obj-$(CONFIG_SOC_AM43XX)		+= $(clockdomain-common)
+obj-$(CONFIG_SOC_AM43XX)		+= clockdomains43xx_data.o
 obj-$(CONFIG_SOC_OMAP5)			+= $(clockdomain-common)
 obj-$(CONFIG_SOC_OMAP5)			+= clockdomains54xx_data.o
 obj-$(CONFIG_SOC_DRA7XX)		+= $(clockdomain-common)

@@ -212,6 +214,9 @@ obj-$(CONFIG_ARCH_OMAP3)		+= omap_hwmod_3xxx_data.o
 obj-$(CONFIG_SOC_AM33XX)		+= omap_hwmod_33xx_data.o
 obj-$(CONFIG_SOC_AM33XX)		+= omap_hwmod_33xx_43xx_interconnect_data.o
 obj-$(CONFIG_SOC_AM33XX)		+= omap_hwmod_33xx_43xx_ipblock_data.o
+obj-$(CONFIG_SOC_AM43XX)		+= omap_hwmod_43xx_data.o
+obj-$(CONFIG_SOC_AM43XX)		+= omap_hwmod_33xx_43xx_interconnect_data.o
+obj-$(CONFIG_SOC_AM43XX)		+= omap_hwmod_33xx_43xx_ipblock_data.o
 obj-$(CONFIG_ARCH_OMAP4)		+= omap_hwmod_44xx_data.o
 obj-$(CONFIG_SOC_OMAP5)			+= omap_hwmod_54xx_data.o
 obj-$(CONFIG_SOC_DRA7XX)		+= omap_hwmod_7xx_data.o

arch/arm/mach-omap2/cm33xx.h +1 -1

index 757320b..cfb8891 100644
@@ -383,7 +383,7 @@ void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs);
 void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs);
 void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs);
 
-#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
+#ifdef CONFIG_SOC_AM33XX
 extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
 					u16 clkctrl_offs);
 extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,

Signature · 1 line

1.8.3.4

Afzal Mohammed

author

2013-10-01 07:14 UTC #10 lore raw

PATCH v5 11/11 ARM: OMAP2+: AM43x PRCM init

In reply to Afzal Mohammed

From: Ambresh K <[email protected]>

Initialise AM43x HWMOD, powerdomains and clockdomains.

Signed-off-by Ambresh K <[email protected]>

Signed-off-by Afzal Mohammed <[email protected]>

---
 arch/arm/mach-omap2/io.c | 6 ++++++
 1 file changed, 6 insertions(+)

arch/arm/mach-omap2/io.c +6 -0

index ff2113c..c90f647 100644
@@ -594,7 +594,13 @@ void __init am43xx_init_early(void)
 				  NULL);
 	omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
 	omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
+	omap_prm_base_init();
+	omap_cm_base_init();
 	omap3xxx_check_revision();
+	am43xx_powerdomains_init();
+	am43xx_clockdomains_init();
+	am43xx_hwmod_init();
+	omap_hwmod_init_postsetup();
 }
 #endif

Signature · 1 line

1.8.3.4

Rajendra Nayak

2013-10-04 06:42 UTC #11 lore raw

v5 cover ARM: OMAP2+: AM43x PRCM basic support

In reply to Afzal Mohammed

Quoted 19 lines · Afzal Mohammed

Hi Paul, Benoit, Tony,
This series adds PRCM support (except clock tree) for AM43x SoC's. Please consider this for inclusion in the coming merge window.
Patch 02/11 "ARM: OMAP2+: hwmod: AM335x/AM43x: move common data" may not reach mailing lists due to bigger size, this series is also present @git://gitorious.org/x0148406-public/linux-kernel.git tags/am43x-prcm-v5
Compared to v4, only change is in fixing the powerdomain data.
Major changes compared to rfc v3:
1. All register offsets properly taken care for AM43x (with rfc v3, a couple of issues was detected while testing on pre-silicon)
2. There were two patches for common hwmod data movement (one for interconnect and other for ip block data), both were combined to have a cleaner series that is bisectable.
3. Cleaner seperation of common data

Quoted 5 lines

Major changes compared to v2 (v3 was only an rfc for current approach):
1. omap_hwmod_33xx_43xx_interconnect_data.c has the common interconnect ocp's structs shared between AM335x and AM43x
2. omap_hwmod_33xx_43xx_ipblock_data.c has the common hwmod structs shared between AM335x and AM43x

This split and reuse looks much better and readable now.

For the complete series,

Acked-by Rajendra Nayak <[email protected]>

Quoted 71 lines

3. Instances where clock domain or clock topology has changed in the few cases, have separate structures for AM335x and AM43x
4. To handle scenarios where register offsets are different, they are dynamically init-ed in omap_hwmod_33xx_43xx_ipblock_data.c
5. Register offsets for hwmod's that are present either in AM335x or AM43x are updated statically in omap_hwmod_33xx_data.c or omap_hwmod_43xx_data.c as that was cleaner.
6. Remove the change that re-introduces SW_SLEEP for OMAP4, this will be taken care separately.
This series has been boot tested on pre-silicon platform with the help of Tero's DT clock tree conversion series. This series has been tested on AM335x-EVM too.
Additional details:
AM43x reuses most of the IP's from AM335x, as that is the case, much of the AM335x hwmod data is reused. As AM43x PRCM register layout differs from AM335x and is similar to OMAP4, power domain, clock domain & hwmod operations are reused from OMAP4. Currently there is no public TRM available for AM43x.
Changes based on: v3.12-rc2
Regards
Afzal
Afzal Mohammed (7):
ARM: OMAP2+: hwmod: AM335x/AM43x: move common data
ARM: OMAP2+: hwmod: AM335x: runtime register update
ARM: OMAP2+: hwmod: AM335x: remove static register offs
ARM: OMAP2+: PRCM: AM43x definitions
ARM: OMAP2+: hwmod: AM43x support
ARM: OMAP2+: hwmod: AM43x operations
ARM: OMAP2+: AM43x: PRCM kbuild
Ambresh K (3):
ARM: OMAP2+: PM: AM43x powerdomain data
ARM: OMAP2+: CM: AM43x clockdomain data
ARM: OMAP2+: AM43x PRCM init
Ankur Kishore (1):
ARM: OMAP2+: CM: cm_inst offset s16->u16
 arch/arm/mach-omap2/Makefile                       |    9 +-
 arch/arm/mach-omap2/clockdomain.h                  |    4 +-
 arch/arm/mach-omap2/clockdomains43xx_data.c        |  196 ++
 arch/arm/mach-omap2/cm33xx.c                       |   16 +-
 arch/arm/mach-omap2/cm33xx.h                       |   12 +-
 arch/arm/mach-omap2/cminst44xx.c                   |   29 +-
 arch/arm/mach-omap2/cminst44xx.h                   |   26 +-
 arch/arm/mach-omap2/io.c                           |    6 +
 arch/arm/mach-omap2/omap_hwmod.c                   |    8 +
 arch/arm/mach-omap2/omap_hwmod.h                   |    1 +
 .../mach-omap2/omap_hwmod_33xx_43xx_common_data.h  |  163 ++
 .../omap_hwmod_33xx_43xx_interconnect_data.c       |  643 +++++++
 .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 1456 +++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_33xx_data.c         | 1966 +-------------------
 arch/arm/mach-omap2/omap_hwmod_43xx_data.c         |  622 +++++++
 arch/arm/mach-omap2/powerdomain.h                  |    1 +
 arch/arm/mach-omap2/powerdomains43xx_data.c        |  136 ++
 arch/arm/mach-omap2/prcm43xx.h                     |  141 ++
 18 files changed, 3432 insertions(+), 2003 deletions(-)
 create mode 100644 arch/arm/mach-omap2/clockdomains43xx_data.c
 create mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
 create mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
 create mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
 create mode 100644 arch/arm/mach-omap2/omap_hwmod_43xx_data.c
 create mode 100644 arch/arm/mach-omap2/powerdomains43xx_data.c
 create mode 100644 arch/arm/mach-omap2/prcm43xx.h

Tony Lindgren

maintainer

2013-10-08 18:15 UTC #12 lore raw

v5 cover ARM: OMAP2+: AM43x PRCM basic support

Quoted 26 lines · Rajendra Nayak

Quoted 19 lines · Afzal Mohammed
Hi Paul, Benoit, Tony,
This series adds PRCM support (except clock tree) for AM43x SoC's. Please consider this for inclusion in the coming merge window.
Patch 02/11 "ARM: OMAP2+: hwmod: AM335x/AM43x: move common data" may not reach mailing lists due to bigger size, this series is also present @git://gitorious.org/x0148406-public/linux-kernel.git tags/am43x-prcm-v5
Compared to v4, only change is in fixing the powerdomain data.
Major changes compared to rfc v3:
1. All register offsets properly taken care for AM43x (with rfc v3, a couple of issues was detected while testing on pre-silicon)
2. There were two patches for common hwmod data movement (one for interconnect and other for ip block data), both were combined to have a cleaner series that is bisectable.
3. Cleaner seperation of common data
Quoted 5 lines
Major changes compared to v2 (v3 was only an rfc for current approach):
1. omap_hwmod_33xx_43xx_interconnect_data.c has the common interconnect ocp's structs shared between AM335x and AM43x
2. omap_hwmod_33xx_43xx_ipblock_data.c has the common hwmod structs shared between AM335x and AM43x

Quoted 4 lines

This split and reuse looks much better and readable now.
For the complete series,
Acked-by Rajendra Nayak <[email protected]>

Looks good to me too. I'm assuming that Paul will queue this.

And let's everybody make note that this will be the _last_ set of hwmod data we'll _ever_ merge as this all should be replaced with device tree + bus driver based approach for future SoCs.

But let's get the common clock framework conversion done first, so this can wait until after that.

Acked-by Tony Lindgren <[email protected]>

Rajendra Nayak

2013-10-10 05:25 UTC #13 lore raw

v5 cover ARM: OMAP2+: AM43x PRCM basic support

Quoted 32 lines · Tony Lindgren

Quoted 26 lines · Rajendra Nayak
Quoted 19 lines · Afzal Mohammed
Hi Paul, Benoit, Tony,
This series adds PRCM support (except clock tree) for AM43x SoC's. Please consider this for inclusion in the coming merge window.
Patch 02/11 "ARM: OMAP2+: hwmod: AM335x/AM43x: move common data" may not reach mailing lists due to bigger size, this series is also present @git://gitorious.org/x0148406-public/linux-kernel.git tags/am43x-prcm-v5
Compared to v4, only change is in fixing the powerdomain data.
Major changes compared to rfc v3:
1. All register offsets properly taken care for AM43x (with rfc v3, a couple of issues was detected while testing on pre-silicon)
2. There were two patches for common hwmod data movement (one for interconnect and other for ip block data), both were combined to have a cleaner series that is bisectable.
3. Cleaner seperation of common data
Quoted 5 lines
Major changes compared to v2 (v3 was only an rfc for current approach):
1. omap_hwmod_33xx_43xx_interconnect_data.c has the common interconnect ocp's structs shared between AM335x and AM43x
2. omap_hwmod_33xx_43xx_ipblock_data.c has the common hwmod structs shared between AM335x and AM43x
Quoted 4 lines
This split and reuse looks much better and readable now.
For the complete series,
Acked-by Rajendra Nayak <[email protected]>

Quoted 8 lines

Looks good to me too. I'm assuming that Paul will queue this.
And let's everybody make note that this will be the _last_ set of hwmod data we'll _ever_ merge as this all should be replaced with device tree + bus driver based approach for future SoCs.
But let's get the common clock framework conversion done first, so this can wait until after that.

Tony, I hope you meant the 'hwmod replaced with device tree + bus driver based approach' is what can wait until after the common clock framework DT conversion and not the $subject series itself :)

regards,
Rajendra

Quoted 3 lines

Acked-by Tony Lindgren <[email protected]>

Tony Lindgren

maintainer

2013-10-10 16:31 UTC #14 lore raw

v5 cover ARM: OMAP2+: AM43x PRCM basic support

Quoted 39 lines · Rajendra Nayak

Quoted 38 lines · Tony Lindgren
Quoted 26 lines · Rajendra Nayak
Quoted 19 lines · Afzal Mohammed
Hi Paul, Benoit, Tony,
This series adds PRCM support (except clock tree) for AM43x SoC's. Please consider this for inclusion in the coming merge window.
Patch 02/11 "ARM: OMAP2+: hwmod: AM335x/AM43x: move common data" may not reach mailing lists due to bigger size, this series is also present @git://gitorious.org/x0148406-public/linux-kernel.git tags/am43x-prcm-v5
Compared to v4, only change is in fixing the powerdomain data.
Major changes compared to rfc v3:
1. All register offsets properly taken care for AM43x (with rfc v3, a couple of issues was detected while testing on pre-silicon)
2. There were two patches for common hwmod data movement (one for interconnect and other for ip block data), both were combined to have a cleaner series that is bisectable.
3. Cleaner seperation of common data
Quoted 5 lines
Major changes compared to v2 (v3 was only an rfc for current approach):
1. omap_hwmod_33xx_43xx_interconnect_data.c has the common interconnect ocp's structs shared between AM335x and AM43x
2. omap_hwmod_33xx_43xx_ipblock_data.c has the common hwmod structs shared between AM335x and AM43x
Quoted 4 lines
This split and reuse looks much better and readable now.
For the complete series,
Acked-by Rajendra Nayak <[email protected]>
Looks good to me too. I'm assuming that Paul will queue this.
And let's everybody make note that this will be the _last_ set of hwmod data we'll _ever_ merge as this all should be replaced with device tree + bus driver based approach for future SoCs.

Quoted 6 lines

Quoted 2 lines
But let's get the common clock framework conversion done first, so this can wait until after that.
Tony, I hope you meant the 'hwmod replaced with device tree + bus driver based approach' is what can wait until after the common clock framework DT conversion and not the $subject series itself :)

Right, "hwmod replaced with device tree + bus driver based approach" is what I mean can wait until the clock conversion is done :)

Not this patch series.

Regards,

Tony