SATA support for OMAP5 uevm

RFC PATCH Superseded Roger Quadros 3 participants 16 messages Nov 6, 2013 – Jan 8, 2014 2 messages not in the archive

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Arm (32-bit) Block layer

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Roger Quadros

author

2013-11-06 14:47 UTC #0 lore raw

cover SATA support for OMAP5 uevm

Hi,

This series adds SATA support for OMAP5 uevm board.

This is an RFC patchset for review only. Patches are based on v2013.10.

cheers,
-roger

---
Roger Quadros (5):
ahci: Error out with message on malloc() failure
ARM: OMAP5: Add Pipe3 PHY driver
ARM: OMAP5: Add PRCM and Control information for SATA
ARM: OMAP5: Add SATA platform glue
ARM: omap5_uevm: Add SATA support

 arch/arm/cpu/armv7/omap-common/Makefile    |   7 +
 arch/arm/cpu/armv7/omap-common/pipe3-phy.c | 233 +++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/omap-common/pipe3-phy.h |  36 +++++
 arch/arm/cpu/armv7/omap-common/sata.c      |  78 ++++++++++
 arch/arm/cpu/armv7/omap5/prcm-regs.c       |   5 +
 arch/arm/include/asm/arch-omap5/clock.h    |   3 +
 arch/arm/include/asm/arch-omap5/omap.h     |   3 +
 arch/arm/include/asm/arch-omap5/sata.h     |  48 ++++++
 arch/arm/include/asm/omap_common.h         |   3 +
 board/ti/omap5_uevm/evm.c                  |   7 +
 drivers/block/ahci.c                       |  16 +-
 include/configs/omap5_uevm.h               |  10 ++
 12 files changed, 447 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.c
 create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.h
 create mode 100644 arch/arm/cpu/armv7/omap-common/sata.c
 create mode 100644 arch/arm/include/asm/arch-omap5/sata.h

Signature · 1 line

1.8.3.2

Roger Quadros

author

2013-11-06 14:47 UTC #1 lore raw

PATCH 1/5 ahci: Error out with message on malloc() failure

If malloc() fails, we don't want to continue in ahci_init() and ahci_init_one(). Also print a more informative error message on malloc() failures.

CC Rob Herring <[email protected]>

Signed-off-by Roger Quadros <[email protected]>

---
 drivers/block/ahci.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

drivers/block/ahci.c +14 -2

index 0daad36..e24d634 100644
@@ -379,6 +379,11 @@ static int ahci_init_one(pci_dev_t pdev)
 	int rc;
 
 	probe_ent = malloc(sizeof(struct ahci_probe_ent));
+	if (!probe_ent) {
+		printf("%s: No memory for probe_ent\n", __func__);
+		return -ENOMEM;
+	}
+
 	memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
 	probe_ent->dev = pdev;

@@ -503,7 +508,7 @@ static int ahci_port_start(u8 port)
 	mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
 	if (!mem) {
 		free(pp);
-		printf("No mem for table!\n");
+		printf("%s: No mem for table!\n", __func__);
 		return -ENOMEM;
 	}

@@ -638,8 +643,10 @@ static int ata_scsiop_inquiry(ccb *pccb)
 	/* Read id from sata */
 	port = pccb->target;
 	tmpid = malloc(ATA_ID_WORDS * 2);
-	if (!tmpid)
+	if (!tmpid) {
+		printf("%s: No memory for tmpid\n", __func__);
 		return -ENOMEM;
+	}
 
 	if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid,
 				ATA_ID_WORDS * 2, 0)) {

@@ -889,6 +896,11 @@ int ahci_init(u32 base)
 	u32 linkmap;
 
 	probe_ent = malloc(sizeof(struct ahci_probe_ent));
+	if (!probe_ent) {
+		printf("%s: No memory for probe_ent\n", __func__);
+		return -ENOMEM;
+	}
+
 	memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
 
 	probe_ent->host_flags = ATA_FLAG_SATA

Signature · 1 line

1.8.3.2

Roger Quadros

author

2013-11-06 14:47 UTC #2 lore raw

PATCH 2/5 ARM: OMAP5: Add Pipe3 PHY driver

In reply to Roger Quadros

Pipe3 PHY is used by SATA, USB3 and PCIe modules. This is a driver for the Pipe3 PHY.

Signed-off-by Roger Quadros <[email protected]>

---
 arch/arm/cpu/armv7/omap-common/Makefile    |   4 +
 arch/arm/cpu/armv7/omap-common/pipe3-phy.c | 233 +++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/omap-common/pipe3-phy.h |  36 +++++
 3 files changed, 273 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.c
 create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.h

arch/arm/cpu/armv7/omap-common/Makefile +4 -0

index 75b3753..6e4a0f0 100644
@@ -21,6 +21,10 @@ COBJS	+= vc.o
 COBJS	+= abb.o
 endif
 
+ifneq ($(CONFIG_OMAP54XX),)
+COBJS	+= pipe3-phy.o
+endif
+
 ifeq ($(CONFIG_OMAP34XX),)
 COBJS	+= boot-common.o
 SOBJS	+= lowlevel_init.o

arch/arm/cpu/armv7/omap-common/pipe3-phy.c new file +233 -0

233 lines not on this page · raw message

arch/arm/cpu/armv7/omap-common/pipe3-phy.h new file +36 -0

new file mode 100644
index 0000000..441f49a
@@ -0,0 +1,36 @@
+/*
+ * TI PIPE3 PHY
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __OMAP_PIPE3_PHY_H
+#define __OMAP_PIPE3_PHY_H
+
+struct pipe3_dpll_params {
+	u16     m;
+	u8      n;
+	u8      freq:3;
+	u8      sd;
+	u32     mf;
+};
+
+struct pipe3_dpll_map {
+	unsigned long rate;
+	struct pipe3_dpll_params params;
+};
+
+struct omap_pipe3 {
+	void __iomem            *pll_ctrl_base;
+	void __iomem		*power_reg;
+	struct pipe3_dpll_map   *dpll_map;
+};
+
+
+int phy_pipe3_power_on(struct omap_pipe3 *phy);
+int phy_pipe3_power_off(struct omap_pipe3 *pipe3);
+
+#endif /* __OMAP_PIPE3_PHY_H */

Signature · 1 line

1.8.3.2

Tom Rini

2013-11-06 21:48 UTC #3 lore raw

PATCH 2/5 ARM: OMAP5: Add Pipe3 PHY driver

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Quoted 4 lines · Roger Quadros

Pipe3 PHY is used by SATA, USB3 and PCIe modules. This is a driver for the Pipe3 PHY.
Signed-off-by Roger Quadros <[email protected]>

[snip]

Quoted 1 line

+#define perror(fmt, args...) printf("%s: " fmt, __func__ , ##args)

Please use the debug macro.

[snip[

arch/arm/cpu/armv7/omap-common/pipe3-phy.c line 83

Quoted 2 lines

arch/arm/cpu/armv7/omap-common/pipe3-phy.c new file +2 -0
+	perror("%s: No DPLL configuration for %u Hz SYS CLK\n",
+							__func__, rate);

Indent is wrong, we do like the kernel (and checkpatch.pl is in tools/ and will catch these). Thanks.

Code itself seems fine tho, thanks.

- --
Tom
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Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

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=tTZq
-----END PGP SIGNATURE-----

Roger Quadros

author

2013-11-07 12:23 UTC #4 lore raw

PATCH 2/5 ARM: OMAP5: Add Pipe3 PHY driver

Quoted 4 lines · Tom Rini

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On 11/06/2013 09:47 AM, Roger Quadros wrote:

Quoted 9 lines

Quoted 4 lines
Pipe3 PHY is used by SATA, USB3 and PCIe modules. This is a driver for the Pipe3 PHY.
Signed-off-by Roger Quadros <[email protected]>
[snip]
Quoted 1 line
+#define perror(fmt, args...) printf("%s: " fmt, __func__ , ##args)
Please use the debug macro.

But I want the message to be printed and not hidden if DEBUG is not defined.

Quoted 6 lines

[snip[
arch/arm/cpu/armv7/omap-common/pipe3-phy.c line 83
Quoted 2 lines
arch/arm/cpu/armv7/omap-common/pipe3-phy.c new file +2 -0
+	perror("%s: No DPLL configuration for %u Hz SYS CLK\n",
+							__func__, rate);
Indent is wrong, we do like the kernel (and checkpatch.pl is in tools/ and will catch these). Thanks.

you mean the function arguments '__func__' and 'rate' should be on the same line where perror is?

cheers,
-roger

Tom Rini

2013-11-11 13:52 UTC #5 lore raw

PATCH 2/5 ARM: OMAP5: Add Pipe3 PHY driver

Quoted 8 lines · Roger Quadros

Quoted 7 lines · Tom Rini
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Quoted 3 lines · Roger Quadros
Pipe3 PHY is used by SATA, USB3 and PCIe modules. This is a driver for the Pipe3 PHY.

Quoted 7 lines

Quoted 6 lines
Quoted 1 line
Signed-off-by Roger Quadros <[email protected]>
[snip]
Quoted 1 line
+#define perror(fmt, args...) printf("%s: " fmt, __func__ , ##args)
Please use the debug macro.
But I want the message to be printed and not hidden if DEBUG is not defined.

Then just call printf please. Or is this kernel-adapted code?

Quoted 9 lines

Quoted 6 lines
[snip[
arch/arm/cpu/armv7/omap-common/pipe3-phy.c line 83
Quoted 2 lines
arch/arm/cpu/armv7/omap-common/pipe3-phy.c new file +2 -0
+	perror("%s: No DPLL configuration for %u Hz SYS CLK\n",
+							__func__, rate);
Indent is wrong, we do like the kernel (and checkpatch.pl is in tools/ and will catch these). Thanks.
you mean the function arguments '__func__' and 'rate' should be on the same line where perror is?

perror("....\n",

       __func_, ...);

Signature · 8 lines

Tom
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Roger Quadros

author

2013-11-11 13:57 UTC #6 lore raw

PATCH 2/5 ARM: OMAP5: Add Pipe3 PHY driver

Quoted 10 lines · Tom Rini

Quoted 9 lines · Roger Quadros
Quoted 8 lines · Tom Rini
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Quoted 4 lines · Roger Quadros
Pipe3 PHY is used by SATA, USB3 and PCIe modules. This is a driver for the Pipe3 PHY.
Signed-off-by Roger Quadros <[email protected]>

Quoted 8 lines

Quoted 6 lines
Quoted 5 lines
[snip]
Quoted 1 line
+#define perror(fmt, args...) printf("%s: " fmt, __func__ , ##args)
Please use the debug macro.
But I want the message to be printed and not hidden if DEBUG is not defined.
Then just call printf please. Or is this kernel-adapted code?

OK. No this isn't in the kernel.

Quoted 8 lines

Quoted 8 lines
Quoted 7 lines
[snip[
arch/arm/cpu/armv7/omap-common/pipe3-phy.c line 83
Quoted 2 lines
arch/arm/cpu/armv7/omap-common/pipe3-phy.c new file +2 -0
+	perror("%s: No DPLL configuration for %u Hz SYS CLK\n",
+							__func__, rate);
Indent is wrong, we do like the kernel (and checkpatch.pl is in tools/ and will catch these). Thanks.

Quoted 6 lines

Quoted 2 lines
you mean the function arguments '__func__' and 'rate' should be on the same line where perror is?
perror("....\n",
       __func_, ...);

OK. I'll wait some more time for comments on v2 before I send out a v3 with these changes.

cheers,
-roger

Roger Quadros

author

2013-11-06 14:47 UTC #7 lore raw

PATCH 3/5 ARM: OMAP5: Add PRCM and Control information for SATA

In reply to Roger Quadros

Adds the necessary PRCM and Control register information for SATA on OMAP5.

Signed-off-by Roger Quadros <[email protected]>

---
 arch/arm/cpu/armv7/omap5/prcm-regs.c    | 5 +++++
 arch/arm/include/asm/arch-omap5/clock.h | 3 +++
 arch/arm/include/asm/arch-omap5/omap.h  | 3 +++
 arch/arm/include/asm/omap_common.h      | 3 +++
 4 files changed, 14 insertions(+)

arch/arm/cpu/armv7/omap5/prcm-regs.c +5 -0

index 764620d..78fd7ec 100644
@@ -203,8 +203,10 @@ struct prcm_regs const omap5_es1_prcm = {
 	.cm_l3init_hsusbotg_clkctrl = 0x4a009360,
 	.cm_l3init_hsusbtll_clkctrl = 0x4a009368,
 	.cm_l3init_p1500_clkctrl = 0x4a009378,
+	.cm_l3init_sata_clkctrl = 0x4a009388,
 	.cm_l3init_fsusb_clkctrl = 0x4a0093d0,
 	.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
+	.cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
 
 	/* cm2.l4per */
 	.cm_l4per_clkstctrl = 0x4a009400,

@@ -295,6 +297,7 @@ struct prcm_regs const omap5_es1_prcm = {
 struct omap_sys_ctrl_regs const omap5_ctrl = {
 	.control_status				= 0x4A002134,
 	.control_std_fuse_opp_vdd_mpu_2		= 0x4A0021B4,
+	.control_phy_power_sata			= 0x4A002374,
 	.control_padconf_core_base		= 0x4A002800,
 	.control_paconf_global			= 0x4A002DA0,
 	.control_paconf_mode			= 0x4A002DA4,

@@ -696,8 +699,10 @@ struct prcm_regs const omap5_es2_prcm = {
 	.cm_l3init_hsusbotg_clkctrl = 0x4a009660,
 	.cm_l3init_hsusbtll_clkctrl = 0x4a009668,
 	.cm_l3init_p1500_clkctrl = 0x4a009678,
+	.cm_l3init_sata_clkctrl = 0x4a009688,
 	.cm_l3init_fsusb_clkctrl = 0x4a0096d0,
 	.cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
+	.cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8,
 
 	/* prm irqstatus regs */
 	.prm_irqstatus_mpu_2 = 0x4ae06014,

arch/arm/include/asm/arch-omap5/clock.h +3 -0

index 9a2166c..aa934fb 100644
@@ -137,6 +137,9 @@
 #define HSMMC_CLKCTRL_CLKSEL_MASK		(1 << 24)
 #define HSMMC_CLKCTRL_CLKSEL_DIV_MASK		(1 << 25)
 
+/* CM_L3INIT_SATA_CLKCTRL */
+#define SATA_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
 /* CM_WKUP_GPTIMER1_CLKCTRL */
 #define GPTIMER1_CLKCTRL_CLKSEL_MASK		(1 << 24)

arch/arm/include/asm/arch-omap5/omap.h +3 -0

index 414d37a..150db0f 100644
@@ -64,6 +64,9 @@
 /* QSPI */
 #define QSPI_BASE		0x4B300000
 
+/* SATA */
+#define DWC_AHSATA_BASE		0x4A140000
+
 /*
  * Hardware Register Details
  */

arch/arm/include/asm/omap_common.h +3 -0

index 3a998cc..cffcb93 100644
@@ -224,8 +224,10 @@ struct prcm_regs {
 	u32 cm_l3init_hsusbotg_clkctrl;
 	u32 cm_l3init_hsusbtll_clkctrl;
 	u32 cm_l3init_p1500_clkctrl;
+	u32 cm_l3init_sata_clkctrl;
 	u32 cm_l3init_fsusb_clkctrl;
 	u32 cm_l3init_ocp2scp1_clkctrl;
+	u32 cm_l3init_ocp2scp3_clkctrl;
 
 	u32 prm_irqstatus_mpu_2;

@@ -361,6 +363,7 @@ struct omap_sys_ctrl_regs {
 	u32 control_ldosram_mpu_voltage_ctrl;
 	u32 control_ldosram_core_voltage_ctrl;
 	u32 control_usbotghs_ctrl;
+	u32 control_phy_power_sata;
 	u32 control_padconf_core_base;
 	u32 control_paconf_global;
 	u32 control_paconf_mode;

Signature · 1 line

1.8.3.2

Roger Quadros

author

2013-11-06 14:47 UTC #8 lore raw

PATCH 4/5 ARM: OMAP5: Add SATA platform glue

In reply to Roger Quadros

Add platform glue logic for the SATA controller.

Signed-off-by Roger Quadros <[email protected]>

---
 arch/arm/cpu/armv7/omap-common/Makefile |  3 ++
 arch/arm/cpu/armv7/omap-common/sata.c   | 78 +++++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap5/sata.h  | 48 ++++++++++++++++++++
 3 files changed, 129 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/omap-common/sata.c
 create mode 100644 arch/arm/include/asm/arch-omap5/sata.h

arch/arm/cpu/armv7/omap-common/Makefile +3 -0

index 6e4a0f0..0535b62 100644
@@ -23,6 +23,9 @@ endif
 
 ifneq ($(CONFIG_OMAP54XX),)
 COBJS	+= pipe3-phy.o
+ifdef CONFIG_SCSI_AHCI_PLAT
+COBJS	+= sata.o
+endif
 endif
 
 ifeq ($(CONFIG_OMAP34XX),)

arch/arm/cpu/armv7/omap-common/sata.c new file +78 -0

78 lines not on this page · raw message

arch/arm/include/asm/arch-omap5/sata.h new file +48 -0

48 lines not on this page · raw message

Signature · 1 line

1.8.3.2

Tom Rini

2013-11-06 22:11 UTC #9 lore raw

PATCH 4/5 ARM: OMAP5: Add SATA platform glue

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Quoted 3 lines · Roger Quadros

Add platform glue logic for the SATA controller.
Signed-off-by Roger Quadros <[email protected]>

[snip]

arch/arm/cpu/armv7/omap-common/Makefile endif · line 28

Quoted 11 lines

arch/arm/cpu/armv7/omap-common/Makefile +3 -0

index 6e4a0f0..0535b62 100644
@@ -23,6 +23,9 @@ endif
 
 ifneq ($(CONFIG_OMAP54XX),)
 COBJS	+= pipe3-phy.o
+ifdef CONFIG_SCSI_AHCI_PLAT
+COBJS	+= sata.o
+endif

This should be:
COBJS-$(CONFIG_SCSI_AHCI_PLAT) += sata.o, or obj-... with the recent changes.

Quoted 8 lines

arch/arm/cpu/armv7/omap-common/Makefile +0 -0
 endif
 
 ifeq ($(CONFIG_OMAP34XX),)
arch/arm/cpu/armv7/omap-common/sata.c new file +0 -0
new file mode 100644
index 0000000..eb079c3

[snip]

Quoted 1 line

+#if defined(CONFIG_SCSI_AHCI_PLAT)

The file already depends on this symbol to be built at all.

- --
Tom
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Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

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=kiAz
-----END PGP SIGNATURE-----

Roger Quadros

author

2013-11-07 12:24 UTC #10 lore raw

PATCH 4/5 ARM: OMAP5: Add SATA platform glue

Quoted 14 lines · Tom Rini

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Quoted 3 lines · Roger Quadros
Add platform glue logic for the SATA controller.
Signed-off-by Roger Quadros <[email protected]>
[snip]
Quoted 6 lines
arch/arm/cpu/armv7/omap-common/Makefile +0 -0
index 6e4a0f0..0535b62 100644
@@ -23,6 +23,9 @@ endif
 

Quoted 8 lines

arch/arm/cpu/armv7/omap-common/Makefile endif · line 28
Quoted 5 lines
arch/arm/cpu/armv7/omap-common/Makefile +3 -0
 ifneq ($(CONFIG_OMAP54XX),)
 COBJS	+= pipe3-phy.o
+ifdef CONFIG_SCSI_AHCI_PLAT
+COBJS	+= sata.o
+endif
This should be:
COBJS-$(CONFIG_SCSI_AHCI_PLAT) += sata.o, or obj-... with the recent changes.

OK.

Quoted 10 lines

Quoted 9 lines
arch/arm/cpu/armv7/omap-common/Makefile +0 -0
 endif
 
 ifeq ($(CONFIG_OMAP34XX),)
arch/arm/cpu/armv7/omap-common/sata.c new file +0 -0
new file mode 100644
index 0000000..eb079c3
[snip]

Quoted 3 lines

Quoted 1 line
+#if defined(CONFIG_SCSI_AHCI_PLAT)
The file already depends on this symbol to be built at all.

Right.

cheers,
-roger

Roger Quadros

author

2013-11-06 14:47 UTC #11 lore raw

PATCH 5/5 ARM: omap5_uevm: Add SATA support

In reply to Roger Quadros

The uevm has a SATA port. Inititialize the SATA controller.

Signed-off-by Roger Quadros <[email protected]>

---
 board/ti/omap5_uevm/evm.c    |  7 +++++++
 include/configs/omap5_uevm.h | 10 ++++++++++
 2 files changed, 17 insertions(+)

board/ti/omap5_uevm/evm.c +7 -0

index 4706330..86622c3 100644
@@ -20,6 +20,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/ehci.h>
 #include <asm/ehci-omap.h>
+#include <asm/arch/sata.h>
 
 #define DIE_ID_REG_BASE     (OMAP54XX_L4_CORE_BASE + 0x2000)
 #define DIE_ID_REG_OFFSET	0x200

@@ -67,6 +68,12 @@ int board_init(void)
 	return 0;
 }
 
+int board_late_init(void)
+{
+	omap_sata_init();
+	return 0;
+}
+
 int board_eth_init(bd_t *bis)
 {
 	return 0;

include/configs/omap5_uevm.h +10 -0

index 4d3a800..2f128b8 100644
@@ -69,4 +69,14 @@
 /* Max time to hold reset on this board, see doc/README.omap-reset-time */
 #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC	16296
 
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+
 #endif /* __CONFIG_OMAP5_EVM_H */

Signature · 1 line

1.8.3.2

Enric Balletbo Serra

2013-11-07 08:52 UTC #12 lore raw

cover SATA support for OMAP5 uevm

In reply to Roger Quadros

Hi Roger,

Thanks for the patches!

2013/11/6 Roger Quadros <[email protected]>:

Quoted 36 lines

Hi,

This series adds SATA support for OMAP5 uevm board.

This is an RFC patchset for review only. Patches are based on v2013.10.

cheers,
-roger

 arch/arm/cpu/armv7/omap-common/Makefile    |   7 +
 arch/arm/cpu/armv7/omap-common/pipe3-phy.c | 233 +++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/omap-common/pipe3-phy.h |  36 +++++
 arch/arm/cpu/armv7/omap-common/sata.c      |  78 ++++++++++
 arch/arm/cpu/armv7/omap5/prcm-regs.c       |   5 +
 arch/arm/include/asm/arch-omap5/clock.h    |   3 +
 arch/arm/include/asm/arch-omap5/omap.h     |   3 +
 arch/arm/include/asm/arch-omap5/sata.h     |  48 ++++++
 arch/arm/include/asm/omap_common.h         |   3 +
 board/ti/omap5_uevm/evm.c                  |   7 +
 drivers/block/ahci.c                       |  16 +-
 include/configs/omap5_uevm.h               |  10 ++
 12 files changed, 447 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.c
 create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.h
 create mode 100644 arch/arm/cpu/armv7/omap-common/sata.c
 create mode 100644 arch/arm/include/asm/arch-omap5/sata.h

Quoted 7 lines

--
1.8.3.2
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

I applied your patches and worked perfectly, however I've two small issues.

The first issue is that I see the following error:

    scanning bus for devices...
    ERROR: v7_dcache_inval_range - start address is not aligned - 0xfee48618
    ERROR: v7_dcache_inval_range - stop address is not aligned - 0xfee48818

The second issue, and I'm not sure if the problem should be solved at u-boot level, is that I'm not able to access to the SATA disk at kernel level. I meant, if I boot to the system with latest stable u-boot the kernel recognizes the SATA disk and I'm able to mount, read and write to the disk. If I boot using u-boot with your patches applied the kernel doesn't recognizes the SATA disk and doesn't work. In that case the kernel reports the following error:

ata1: COMRESET failed (errno=-16)

Note that the kernel version that I'm using is 3.8.13 from git.ti.com.

Cheers,
Enric

Roger Quadros

author

2013-11-07 10:44 UTC #13 lore raw

cover SATA support for OMAP5 uevm

+Aneesh.

Hi Enric,

Quoted 49 lines · Enric Balletbo Serra

Hi Roger,
Thanks for the patches!
2013/11/6 Roger Quadros <[email protected]>:
Quoted 36 lines
Hi,
This series adds SATA support for OMAP5 uevm board.
This is an RFC patchset for review only. Patches are based on v2013.10.
cheers,
-roger
---
Roger Quadros (5):
ahci: Error out with message on malloc() failure
ARM: OMAP5: Add Pipe3 PHY driver
ARM: OMAP5: Add PRCM and Control information for SATA
ARM: OMAP5: Add SATA platform glue
ARM: omap5_uevm: Add SATA support
 arch/arm/cpu/armv7/omap-common/Makefile    |   7 +
 arch/arm/cpu/armv7/omap-common/pipe3-phy.c | 233 +++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/omap-common/pipe3-phy.h |  36 +++++
 arch/arm/cpu/armv7/omap-common/sata.c      |  78 ++++++++++
 arch/arm/cpu/armv7/omap5/prcm-regs.c       |   5 +
 arch/arm/include/asm/arch-omap5/clock.h    |   3 +
 arch/arm/include/asm/arch-omap5/omap.h     |   3 +
 arch/arm/include/asm/arch-omap5/sata.h     |  48 ++++++
 arch/arm/include/asm/omap_common.h         |   3 +
 board/ti/omap5_uevm/evm.c                  |   7 +
 drivers/block/ahci.c                       |  16 +-
 include/configs/omap5_uevm.h               |  10 ++
 12 files changed, 447 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.c
 create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.h
 create mode 100644 arch/arm/cpu/armv7/omap-common/sata.c
 create mode 100644 arch/arm/include/asm/arch-omap5/sata.h
Quoted 7 lines
--
1.8.3.2
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Quoted 7 lines

I applied your patches and worked perfectly, however I've two small issues.
The first issue is that I see the following error:
    scanning bus for devices...
    ERROR: v7_dcache_inval_range - start address is not aligned - 0xfee48618
    ERROR: v7_dcache_inval_range - stop address is not aligned - 0xfee48818

I'm seeing this too. Not sure how to fix it.
Aneesh, any pointers?

Quoted 9 lines

The second issue, and I'm not sure if the problem should be solved at u-boot level, is that I'm not able to access to the SATA disk at kernel level. I meant, if I boot to the system with latest stable u-boot the kernel recognizes the SATA disk and I'm able to mount, read and write to the disk. If I boot using u-boot with your patches applied the kernel doesn't recognizes the SATA disk and doesn't work. In that case the kernel reports the following error:

Quoted 3 lines

ata1: COMRESET failed (errno=-16)
Note that the kernel version that I'm using is 3.8.13 from git.ti.com.

There is a known issue with the SATA DPLL

"1.52 SATA Lockup After SATA DPLL Unlock/Relock - Errata ID: i783"

So, we'll need to do something in the kernel before these patches get into u-boot.

I'll try to come up with a solution soon. Something on the lines of not re-initializing the SATA DPLL if it is already locked.

cheers,
-roger

A message that is not in the archive (sent off-list or not yet received): [email protected]

Roger Quadros

author

2013-11-11 13:16 UTC #15 lore raw

cover SATA support for OMAP5 uevm

Aneesh,

Quoted 82 lines · Aneesh

Hi Roger,
Quoted 67 lines
-----Original Message-----
From: Quadros, Roger
Sent: Thursday, November 07, 2013 2:45 AM
To: Enric Balletbo Serra
Cc: u-boot at lists.denx.de; Rini, Tom; Krishnamoorthy, Balaji T; rob.herring at calxeda.com; V, Aneesh
Subject: Re: [U-Boot] [RFC][PATCH 0/5] SATA support for OMAP5 uevm
+Aneesh.
Hi Enric,
Quoted 26 lines · Enric Balletbo Serra
Hi Roger,
Thanks for the patches!
2013/11/6 Roger Quadros <[email protected]>:
Quoted 21 lines
Hi,
This series adds SATA support for OMAP5 uevm board.
This is an RFC patchset for review only. Patches are based on v2013.10.
cheers,
-roger
---
Roger Quadros (5):
ahci: Error out with message on malloc() failure
ARM: OMAP5: Add Pipe3 PHY driver
ARM: OMAP5: Add PRCM and Control information for SATA
ARM: OMAP5: Add SATA platform glue
ARM: omap5_uevm: Add SATA support
 arch/arm/cpu/armv7/omap-common/Makefile    |   7 +
 arch/arm/cpu/armv7/omap-common/pipe3-phy.c | 233
+++++++++++++++++++++++++++++ arch/arm/cpu/armv7/omap-
common/pipe3-phy.h | 36 +++++
Quoted 27 lines
Quoted 15 lines
 arch/arm/cpu/armv7/omap-common/sata.c      |  78 ++++++++++
 arch/arm/cpu/armv7/omap5/prcm-regs.c       |   5 +
 arch/arm/include/asm/arch-omap5/clock.h    |   3 +
 arch/arm/include/asm/arch-omap5/omap.h     |   3 +
 arch/arm/include/asm/arch-omap5/sata.h     |  48 ++++++
 arch/arm/include/asm/omap_common.h         |   3 +
 board/ti/omap5_uevm/evm.c                  |   7 +
 drivers/block/ahci.c                       |  16 +-
 include/configs/omap5_uevm.h               |  10 ++
 12 files changed, 447 insertions(+), 2 deletions(-)  create mode
100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.c
 create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.h
 create mode 100644 arch/arm/cpu/armv7/omap-common/sata.c
 create mode 100644 arch/arm/include/asm/arch-omap5/sata.h
Quoted 7 lines
--
1.8.3.2
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
I applied your patches and worked perfectly, however I've two small issues.
The first issue is that I see the following error:
Quoted 7 lines
Quoted 4 lines
scanning bus for devices...
ERROR: v7_dcache_inval_range - start address is not aligned - 0xfee48618
ERROR: v7_dcache_inval_range - stop address is not aligned -
0xfee48818
I'm seeing this too. Not sure how to fix it.
Aneesh, any pointers?
The issue is that the dcache invalidation is requested for a buffer that is not aligned to cache-line boundary. The cpu instructions for cache invalidation operate on cache lines, so a cache line can not be invalidated partially. So in this case the invalidation function will refuse to invalidate the first and last cache lines.

Quoted 6 lines

The solution is to align your DMA buffer correctly. Take a look at :
ALLOC_CACHE_ALIGN_BUFFER() and DEFINE_CACHE_ALIGN_BUFFER() in include/common.h
Also, doc/README.arm-caches has instructions for handling cached buffers for DMA.

Thanks for this tip, it helped.

One more thing. While I was looking at arch/arm/cpu/armv7/cache_v7.c I failed to understand how you convert the cache line size from words to byte.

e.g.

Quoted 14 lines

static void v7_maint_dcache_level_setway(u32 level, u32 operation)

{
        u32 ccsidr;
        u32 num_sets, num_ways, log2_line_len, log2_num_ways;
        u32 way_shift;

        set_csselr(level, ARMV7_CSSELR_IND_DATA_UNIFIED);

        ccsidr = get_ccsidr();

        log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
                                CCSIDR_LINE_SIZE_OFFSET) + 2;
        /* Converting from words to bytes */
        log2_line_len += 2;

Shouldn't this be

	log2_line_len += 1;

cheers,
-roger

A message that is not in the archive (sent off-list or not yet received): [email protected]

Roger Quadros

author

2014-01-08 07:29 UTC #17 lore raw

cover SATA support for OMAP5 uevm

Aneesh,

Sorry for the late reply.

Quoted 128 lines · Aneesh

Roger,
Quoted 118 lines
-----Original Message-----
From: Quadros, Roger
Sent: Monday, November 11, 2013 5:16 AM
To: V, Aneesh
Cc: Enric Balletbo Serra; u-boot at lists.denx.de; Rini, Tom; Krishnamoorthy, Balaji T; rob.herring at calxeda.com
Subject: Re: [U-Boot] [RFC][PATCH 0/5] SATA support for OMAP5 uevm
Aneesh,
Quoted 74 lines · Aneesh
Hi Roger,
Quoted 72 lines
-----Original Message-----
From: Quadros, Roger
Sent: Thursday, November 07, 2013 2:45 AM
To: Enric Balletbo Serra
Cc: u-boot at lists.denx.de; Rini, Tom; Krishnamoorthy, Balaji T; rob.herring at calxeda.com; V, Aneesh
Subject: Re: [U-Boot] [RFC][PATCH 0/5] SATA support for OMAP5 uevm
+Aneesh.
Hi Enric,
Quoted 26 lines · Enric Balletbo Serra
Hi Roger,
Thanks for the patches!
2013/11/6 Roger Quadros <[email protected]>:
Quoted 21 lines
Hi,
This series adds SATA support for OMAP5 uevm board.
This is an RFC patchset for review only. Patches are based on v2013.10.
cheers,
-roger
---
Roger Quadros (5):
ahci: Error out with message on malloc() failure
ARM: OMAP5: Add Pipe3 PHY driver
ARM: OMAP5: Add PRCM and Control information for SATA
ARM: OMAP5: Add SATA platform glue
ARM: omap5_uevm: Add SATA support
 arch/arm/cpu/armv7/omap-common/Makefile    |   7 +
 arch/arm/cpu/armv7/omap-common/pipe3-phy.c | 233
+++++++++++++++++++++++++++++ arch/arm/cpu/armv7/omap-
common/pipe3-phy.h | 36 +++++
Quoted 31 lines
Quoted 15 lines
 arch/arm/cpu/armv7/omap-common/sata.c      |  78 ++++++++++
 arch/arm/cpu/armv7/omap5/prcm-regs.c       |   5 +
 arch/arm/include/asm/arch-omap5/clock.h    |   3 +
 arch/arm/include/asm/arch-omap5/omap.h     |   3 +
 arch/arm/include/asm/arch-omap5/sata.h     |  48 ++++++
 arch/arm/include/asm/omap_common.h         |   3 +
 board/ti/omap5_uevm/evm.c                  |   7 +
 drivers/block/ahci.c                       |  16 +-
 include/configs/omap5_uevm.h               |  10 ++
 12 files changed, 447 insertions(+), 2 deletions(-)  create mode
100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.c
 create mode 100644 arch/arm/cpu/armv7/omap-common/pipe3-phy.h
 create mode 100644 arch/arm/cpu/armv7/omap-common/sata.c
 create mode 100644 arch/arm/include/asm/arch-omap5/sata.h
Quoted 7 lines
--
1.8.3.2
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
I applied your patches and worked perfectly, however I've two small issues.
The first issue is that I see the following error:
scanning bus for devices...
ERROR: v7_dcache_inval_range - start address is not aligned - 0xfee48618
ERROR: v7_dcache_inval_range - stop address is not aligned -
0xfee48818
Quoted 7 lines
Quoted 2 lines
I'm seeing this too. Not sure how to fix it.
Aneesh, any pointers?
The issue is that the dcache invalidation is requested for a buffer that is not aligned to cache-line boundary. The cpu instructions for cache invalidation operate on cache lines, so a cache line can not be invalidated partially. So in this case the invalidation function will refuse to
invalidate the first and last cache lines.
Quoted 7 lines
The solution is to align your DMA buffer correctly. Take a look at :
ALLOC_CACHE_ALIGN_BUFFER() and DEFINE_CACHE_ALIGN_BUFFER() in include/common.h
Also, doc/README.arm-caches has instructions for handling cached buffers
for DMA.
Thanks for this tip, it helped.
One more thing. While I was looking at arch/arm/cpu/armv7/cache_v7.c I failed to understand how you convert the cache line size from words to byte.
e.g.
Quoted 9 lines
static void v7_maint_dcache_level_setway(u32 level, u32 operation) {
        u32 ccsidr;
        u32 num_sets, num_ways, log2_line_len, log2_num_ways;
        u32 way_shift;

        set_csselr(level, ARMV7_CSSELR_IND_DATA_UNIFIED);

        ccsidr = get_ccsidr();
Quoted 7 lines
Quoted 4 lines
        log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
                                CCSIDR_LINE_SIZE_OFFSET) + 2;
        /* Converting from words to bytes */
        log2_line_len += 2;
Shouldn't this be
	log2_line_len += 1;

Quoted 7 lines

I don?t remember the details of that calculation. But assuming 32-bit word and this variable representing the log2 of the line length it should be +=2 right? Let's say 32 bytes, which is the cache-line size of A15:
32 bytes = 8 words = 2^3 words
32 bytes = 2^5 bytes

Right, I mistook word to be 16-bit.

cheers,
-roger