dmaengine: Add support for BCM2835
Subsystems (4)
PATCH v3 1/1 dmaengine: Add support for BCM2835
Add support for DMA controller of BCM2835 as used in the Raspberry Pi. Currently it only supports cyclic DMA.
---
Thank you for your comments!
I hope I have now removed all leftovers of the sg struct.
Regarding the endian-ness: I have not found any hint about that in the datasheet. Therefore, I chose uint32_t. If you think fixed le32 is more likely I will change it. The PAD fields do not seem to be used, but the datasheet states they should be set to 0.
.../devicetree/bindings/dma/bcm2835-dma.txt | 57 ++ arch/arm/boot/dts/bcm2835.dtsi | 23 + drivers/dma/Kconfig | 6 + drivers/dma/Makefile | 1 + drivers/dma/bcm2835-dma.c | 810 ++++++++++++++++++++ 5 files changed, 897 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/bcm2835-dma.txt create mode 100644 drivers/dma/bcm2835-dma.c
Documentation/devicetree/bindings/dma/bcm2835-dma.txt new file +57 -0
@@ -0,0 +1,57 @@ +* BCM2835 DMA controller + +Required properties: +- compatible: Should be "brcm,bcm2835-dma". +- reg: Should contain DMA registers location and length. +- interrupts: Should contain all DMA interrupts. First cell is the IRQ bank + Second cell is the IRQ number. +- #dma-cells: Must be <1>, used to represent the number of integer cells in +the dmas property of client devices. +- dma-channels: Maximum number of DMA channels available +- dma-requests: Number of DMA Requests. +- dma-channel-mask: Bit mask representing the channels available. + +Example: + +dma: dma@7e007000 { + compatible = "brcm,bcm2835-dma"; + reg = <0x7e007000 0xf00>; + interrupts = <1 16 + 1 17 + 1 18 + 1 19 + 1 20 + 1 21 + 1 22 + 1 23 + 1 24 + 1 25 + 1 26 + 1 27 + 1 28>; + + #dma-cells = <1>; + dma-channels = <15>; + dma-requests = <32>; + dma-channel-mask = <0x7f35>; +}; + +DMA clients connected to the BCM2835 DMA controller must use the format +described in the dma.txt file, using a two-cell specifier for each channel: +a phandle plus one integer cells. +The two cells in order are: + +1. A phandle pointing to the DMA controller. +2. The DREQ number. + +Example: + +bcm2835_i2s: i2s@7e203000 { + compatible = "brcm,bcm2835-i2s"; + reg = < 0x7e203000 0x20 + 0x7e101098 0x02>; + + dmas = <&dma 2 + &dma 3>; + dma-names = "tx", "rx"; +};
arch/arm/boot/dts/bcm2835.dtsi +23 -0
@@ -103,6 +103,29 @@ clocks = <&clk_mmc>; status = "disabled"; }; + + dma: dma@7e007000 { + compatible = "brcm,bcm2835-dma"; + reg = <0x7e007000 0xf00>; + interrupts = <1 16 + 1 17 + 1 18 + 1 19 + 1 20 + 1 21 + 1 22 + 1 23 + 1 24 + 1 25 + 1 26 + 1 27 + 1 28>; + + #dma-cells = <1>; + dma-channels = <15>; /* DMA channel 15 is not handled yet */ + dma-requests = <32>; + dma-channel-mask = <0x7f35>; + }; }; clocks {
drivers/dma/Kconfig +6 -0
@@ -288,6 +288,12 @@ config DMA_OMAP select DMA_ENGINE select DMA_VIRTUAL_CHANNELS +config DMA_BCM2835 + tristate "BCM2835 DMA engine support" + depends on (ARCH_BCM2835 || MACH_BCM2708) + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + config TI_CPPI41 tristate "AM33xx CPPI41 DMA support" depends on ARCH_OMAP
drivers/dma/Makefile +1 -0
@@ -37,6 +37,7 @@ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o obj-$(CONFIG_DMA_OMAP) += omap-dma.o +obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o obj-$(CONFIG_TI_CPPI41) += cppi41.o
drivers/dma/bcm2835-dma.c new file +810 -0
810 lines not on this page · raw message
Signature · 1 line
1.7.9.5
Quoted 11 lines · Florian Meier
Add support for DMA controller of BCM2835 as used in the Raspberry Pi. Currently it only supports cyclic DMA.
Signed-off-by Florian Meier <[email protected]>---
Thank you for your comments!
I hope I have now removed all leftovers of the sg struct. Regarding the endian-ness: I have not found any hint about that in the datasheet. Therefore, I choseuint32_t. If you think fixed le32 is more likely I will change it.
I guess it's easy to change later if needed; there's likely a large number of drivers which fall into this same category.
Quoted 2 lines
The PAD fields do not seem to be used, but the datasheet states they should be set to 0.
Ok. This now looks a lot better, and is smaller too! There's a few issues which need to be resolved still...
drivers/dma/bcm2835-dma.c line 93
Quoted 4 lines
drivers/dma/bcm2835-dma.c new file +4
-0+struct bcm2835_desc { +struct virt_dma_desc vd; +enum dma_transfer_direction dir; +dma_addr_t dev_addr;
I don't think you need dev_addr here anymore - it seems to only be used within bcm2835_dma_prep_dma_cyclic().
drivers/dma/bcm2835-dma.c line 250
Quoted 6 lines
drivers/dma/bcm2835-dma.c new file +6
-0+static int bcm2835_dma_alloc_chan_resources (struct dma_chan *chan) +{ +struct bcm2835_chan *c =to_bcm2835_dma_chan (chan); +int ret; +struct bcm2835_dmadev *d =to_bcm2835_dma_dev (chan->device); +uint32_t chans = d->chans_available;
Probably just uint32_t chans; here is sufficient. Also, as you'll be touching this area again, a minor comment to order the variable declarations in a more tidy way here.
drivers/dma/bcm2835-dma.c line 251
Quoted 1 line
drivers/dma/bcm2835-dma.c new file +1
-0+int chanID =0 ;
Is a channel ID of zero a legal channel number?
Quoted 21 lines
drivers/dma/bcm2835-dma.c new file +21
-0+unsigned long flags; + +spin_lock_irqsave (&d->lock, flags); + + chans = d->chans_available; + +dev_dbg (c->vc.chan.device->dev, +"allocating channel for %u\n" , c->dma_sig); + +/* do not use the FIQ and BULK channels */ + chans &= ~0xD ; + +if (!chans) { +spin_unlock_irqrestore (&d->lock, flags); +return -ENOMEM ; + } + +/* return the ordinal of the first channel in the bitmap */ + chanID =__ffs (chans); + +/* claim the channel */
drivers/dma/bcm2835-dma.c line 282
Quoted 10 lines
drivers/dma/bcm2835-dma.c new file +10
-0+ d->chans_available &= ~(1 << chanID); + + c->dma_chan_base =BCM2835_DMA_CHANIO (d->dma_base, chanID); + c->dma_irq_number = d->dma_irq_numbers[chanID]; + c->dma_ch = chanID; + + ret =request_irq (c->dma_irq_number, + bcm2835_dma_callback,0 ,"DMA IRQ" , c); + +spin_unlock_irqrestore (&d->lock, flags);
Calling request_irq() from within a spinlocked region is not a nice thing to do. May I suggest an alternative coding for this function?
int chanID = -1;
dev_dbg(c->vc.chan.device->dev,
"allocating channel for %u\n", c->dma_sig);
spin_lock_irqsave(&d->lock, flags);
chans = d->chans_available;
if (chans) {
/* return the ordinal of the first channel in the bitmap */
chanID = __ffs(chans);
d->chans_available &= ~(1 << chanID);
}
spin_unlock_irqrestore(&d->lock, flags);
if (chanID == -1)
return -ENOMEM;
c->dma_chan_base = BCM2835_DMA_CHANIO(d->dma_base, chanID);
c->dma_irq_number = d->dma_irq_numbers[chanID];
c->dma_ch = chanID;
ret = request_irq(c->dma_irq_number,
bcm2835_dma_callback, 0, "DMA IRQ", c);Now, don't forget to clean up if request_irq() fails...
if (ret < 0) {
spin_lock_irqsave(&d->lock, flags);
d->chans_available |= 1 << chanID;
spin_unlock_irqrestore(&d->lock, flags);
}
return ret;How does that look?
Quoted 8 lines
drivers/dma/bcm2835-dma.c new file +8
-0+ +if (ret <0 ) +return ret; + +return 0 ; +} + +static void bcm2835_dma_free_chan_resources (struct dma_chan *chan)
drivers/dma/bcm2835-dma.c line 300
Quoted 10 lines
drivers/dma/bcm2835-dma.c new file +10
-0+{ +struct bcm2835_chan *c =to_bcm2835_dma_chan (chan); +struct bcm2835_dmadev *d =to_bcm2835_dma_dev (chan->device); +unsigned long flags; + +spin_lock_irqsave (&d->lock, flags); +vchan_free_chan_resources (&c->vc); + d->chans_available |=1 << c->dma_ch; +free_irq (c->dma_irq_number, c); +spin_unlock_irqrestore (&d->lock, flags);
A better ordering here would be:
vchan_free_chan_resources(&c->vc); free_irq(c->dma_irq_number, c); spin_lock_irqsave(&d->lock, flags); d->chans_available |= 1 << c->dma_ch; spin_unlock_irqrestore(&d->lock, flags);
You don't need to call the first two under the spinlock - all you need to protect is the read-modify-write of d->chans_available here and also in the above function.
...
drivers/dma/bcm2835-dma.c line 496
Quoted 7 lines
drivers/dma/bcm2835-dma.c new file +7
-0+/* +* Next block is the next frame. +* This DMA engine driver currently only supports cyclic DMA. +* Therefore, wrap around at number of frames. +*/ + control_block->next = d->control_block_base_phys + +sizeof (struct bcm2835_dma_cb ) * ((frame +1 ) % (d->frames));
Minor comment here - the parens around d->frames isn't required, and wrapping this a little better would be nice. I'd suggest moving ((frame + 1) % d->frames) onto the next line.
Other than those comments, it's looking really quite good! Well done.
Quoted 10 lines · Florian Meier
Add support for DMA controller of BCM2835 as used in the Raspberry Pi. Currently it only supports cyclic DMA.
Signed-off-by Florian Meier <[email protected]>---
Thank you for your comments!
I hope I have now removed all leftovers of the sg struct.
Regarding the endian-ness: I have not found any hint about that in the datasheet. Therefore, I choseuint32_t. If you think fixed le32 is more likely I will change it. The PAD fields do not seem to be used, but the datasheet states they should be set to 0.
can you pls reflow this to 80chars...
Also going thru driver I suspect you have not run checkpatch, pls do run this scriprt to check for coding style
Quoted 7 lines
drivers/dma/bcm2835-dma.c new file +7
-0+static irqreturn_t bcm2835_dma_callback (int irq,void *data) +{ +struct bcm2835_chan *c = data; +struct bcm2835_desc *d; +unsigned long flags; + +spin_lock_irqsave (&c->vc.lock, flags);
drivers/dma/bcm2835-dma.c line 230
Quoted 10 lines
drivers/dma/bcm2835-dma.c new file +10
-0+ +/* acknowledge interrupt */ +writel (BCM2835_DMA_INT , c->dma_chan_base +BCM2835_DMA_CS ); + + d = c->desc; + +if (d) { +if (!c->cyclic) { +bcm2835_dma_start_desc (c); +vchan_cookie_complete (&d->vd);
I dont see callback being invoked for this case?
Quoted 11 lines
drivers/dma/bcm2835-dma.c new file +11
-0+ }else { +vchan_cyclic_callback (&d->vd); + } + } + +/* keep the DMA engine running */ +dsb ();/* ARM synchronization barrier */ +writel (BCM2835_DMA_ACTIVE , c->dma_chan_base +BCM2835_DMA_CS ); + +spin_unlock_irqrestore (&c->vc.lock, flags); +
drivers/dma/bcm2835-dma.c line 251
Quoted 10 lines
drivers/dma/bcm2835-dma.c new file +10
-0+return IRQ_HANDLED ; +} + +static int bcm2835_dma_alloc_chan_resources (struct dma_chan *chan) +{ +struct bcm2835_chan *c =to_bcm2835_dma_chan (chan); +int ret; +struct bcm2835_dmadev *d =to_bcm2835_dma_dev (chan->device); +uint32_t chans = d->chans_available; +int chanID =0 ;
Pls avoid camel case
Quoted 26 lines
drivers/dma/bcm2835-dma.c new file +26
-0+unsigned long flags; + +spin_lock_irqsave (&d->lock, flags); + + chans = d->chans_available; + +dev_dbg (c->vc.chan.device->dev, +"allocating channel for %u\n" , c->dma_sig); + +/* do not use the FIQ and BULK channels */ + chans &= ~0xD ; + +if (!chans) { +spin_unlock_irqrestore (&d->lock, flags); +return -ENOMEM ; + } + +/* return the ordinal of the first channel in the bitmap */ + chanID =__ffs (chans); + +/* claim the channel */ + d->chans_available &= ~(1 << chanID); + + c->dma_chan_base =BCM2835_DMA_CHANIO (d->dma_base, chanID); + c->dma_irq_number = d->dma_irq_numbers[chanID]; + c->dma_ch = chanID;
drivers/dma/bcm2835-dma.c line 287
Quoted 10 lines
drivers/dma/bcm2835-dma.c new file +10
-0+ + ret =request_irq (c->dma_irq_number, + bcm2835_dma_callback,0 ,"DMA IRQ" , c); + +spin_unlock_irqrestore (&d->lock, flags); + +if (ret <0 ) +return ret; + +return 0 ;
unconditional return ret; will do same!
drivers/dma/bcm2835-dma.c line 317
Quoted 13 lines
drivers/dma/bcm2835-dma.c new file +13
-0+static size_t bcm2835_dma_desc_size (struct bcm2835_desc *d) +{ +unsigned i; +size_t size; + +for (size = i =0 ; i < d->frames; i++) { +struct bcm2835_dma_cb *control_block = + &d->control_block_base[i]; + + size += control_block->length; + } + +return size;
you may want to store this in descritpor which creating that, so you can avoid computation at query
Quoted 27 lines
drivers/dma/bcm2835-dma.c new file +27
-0+static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic ( +struct dma_chan *chan,dma_addr_t buf_addr,size_t buf_len, +size_t period_len,enum dma_transfer_direction direction, +unsigned long flags,void *context) +{ +struct bcm2835_chan *c =to_bcm2835_dma_chan (chan); +enum dma_slave_buswidth dev_width; +struct bcm2835_desc *d; +dma_addr_t dev_addr; +unsigned es, sync_type; +unsigned frame; + +/* Grab configuration */ +if (direction ==DMA_DEV_TO_MEM ) { + dev_addr = c->cfg.src_addr; + dev_width = c->cfg.src_addr_width; + sync_type =BCM2835_DMA_S_DREQ ; + }else if (direction ==DMA_MEM_TO_DEV ) { + dev_addr = c->cfg.dst_addr; + dev_width = c->cfg.dst_addr_width; + sync_type =BCM2835_DMA_D_DREQ ; + }else { +dev_err (chan->device->dev,"%s: bad direction?\n" , __func__); +return NULL ; + } + +/* Bus width translates to the element size (ES) */
drivers/dma/bcm2835-dma.c line 434
Quoted 10 lines
drivers/dma/bcm2835-dma.c new file +10
-0+switch (dev_width) { +case DMA_SLAVE_BUSWIDTH_4_BYTES : + es =BCM2835_DMA_DATA_TYPE_S32 ; +break ; +default : +return NULL ; + } + +/* Now allocate and setup the descriptor. */ + d =kzalloc (sizeof (*d),GFP_ATOMIC );
GFP_NOWAIT is recommendation for DMA drivers
drivers/dma/bcm2835-dma.c line 446
Quoted 12 lines
drivers/dma/bcm2835-dma.c new file +12
-0+if (!d) +return NULL ; + + d->dir = direction; + d->dev_addr = dev_addr; + d->frames = buf_len / period_len; + +/* Allocate memory for control blocks */ + d->control_block_size = d->frames *sizeof (struct bcm2835_dma_cb ); + d->control_block_base =dma_alloc_coherent (chan->device->dev, + d->control_block_size, &d->control_block_base_phys, +GFP_KERNEL );
ditto
drivers/dma/bcm2835-dma.c line 451
Quoted 5 lines
drivers/dma/bcm2835-dma.c new file +5
-0+ +if (!d->control_block_base) { +dev_err (chan->device->dev, +"%s: Memory allocation error\n" , __func__); +return NULL ;
you need to free "d" allocated above..
Quoted 20 lines
drivers/dma/bcm2835-dma.c new file +19
-0+ } + +memset (d->control_block_base,0 , d->control_block_size); +static int bcm2835_dma_control (struct dma_chan *chan,enum dma_ctrl_cmd cmd, +unsigned long arg) +{ +struct bcm2835_chan *c =to_bcm2835_dma_chan (chan); +int ret; + +switch (cmd) { +case DMA_SLAVE_CONFIG : +return bcm2835_dma_slave_config (c, + (struct dma_slave_config *)arg); + +case DMA_TERMINATE_ALL : +bcm2835_dma_terminate_all (c); +break ; + +case DMA_PAUSE :
drivers/dma/bcm2835-dma.c line 590
Quoted 10 lines
drivers/dma/bcm2835-dma.c new file +10
-0+ ret = -EINVAL ; +break ; + +case DMA_RESUME : + ret = -EINVAL ; +break ; + +default : + ret = -ENXIO ; +break ;
you should do same for PAUSE/RESUME, actually no need to add code for those and fall thru default!
Also since you are going to use for audio pls do implement the capablity APIs in the driver so that thing like what you support and parametsr and automatically discovered and need not be hard coded
Quoted 14 lines
drivers/dma/bcm2835-dma.c new file +14
-0+static int bcm2835_dma_probe (struct platform_device *pdev) +{ +struct bcm2835_dmadev *od; +struct resource *dma_res =NULL ; +void __iomem *dma_base =NULL ; +int rc =0 ; +int i; +struct resource *irq; +int irq_resources; + +if (!pdev->dev.dma_mask) + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; + + rc =dma_set_mask (&pdev->dev,DMA_BIT_MASK (32 ));
drivers/dma/bcm2835-dma.c line 694
Quoted 10 lines
drivers/dma/bcm2835-dma.c new file +10
-0+if (rc) +return rc; +dma_set_coherent_mask (&pdev->dev,DMA_BIT_MASK (32 )); + + od =devm_kzalloc (&pdev->dev,sizeof (*od),GFP_KERNEL ); +if (!od) +return -ENOMEM ; + + pdev->dev.dma_parms = &od->dma_parms; +dma_set_max_seg_size (&pdev->dev,0x3FFFFFFF );
Can you support such a large txn or you want to do this thur SW?
drivers/dma/bcm2835-dma.c line 809
Quoted 5 lines
drivers/dma/bcm2835-dma.c new file +5
-0+module_platform_driver (bcm2835_dma_driver); + +MODULE_AUTHOR ("Florian Meier" ); +MODULE_DESCRIPTION ("BCM2835 DMA engine driver" ); +MODULE_LICENSE ("GPL" );
MODULE_ALIAS too pls
--
~Vinod
Quoted 27 lines · Florian Meier
Add support for DMA controller of BCM2835 as used in the Raspberry Pi. Currently it only supports cyclic DMA.
Signed-off-by Florian Meier <florian.meier-oZ8rN/[email protected]>---
Thank you for your comments!
I hope I have now removed all leftovers of the sg struct.
Regarding the endian-ness: I have not found any hint about that in the datasheet. Therefore, I choseuint32_t. If you think fixed le32 is more likely I will change it. The PAD fields do not seem to be used, but the datasheet states they should be set to 0..../devicetree/bindings/dma/bcm2835-dma.txt | 57 ++ arch/arm/boot/dts/bcm2835.dtsi | 23 + drivers/dma/Kconfig | 6 + drivers/dma/Makefile | 1 + drivers/dma/bcm2835-dma.c | 810 ++++++++++++++++++++ 5 files changed, 897 insertions(+)create mode 100644
Documentation/devicetree/bindings/dma/bcm2835-dma.txtcreate mode 100644drivers/dma/bcm2835-dma.cDocumentation/devicetree/bindings/dma/bcm2835-dma.txt new file +0
-0
Documentation/devicetree/bindings/dma/bcm2835-dma.txt line 7
Quoted 7 lines
Documentation/devicetree/bindings/dma/bcm2835-dma.txt new file +7
-0@@ -0,0 +1,57 @@ +* BCM2835 DMA controller + +Required properties: +- compatible: Should be "brcm,bcm2835-dma". +- reg: Should contain DMA registers location and length. +- interrupts: Should contain all DMA interrupts. First cell is the IRQ bank + Second cell is the IRQ number.
Can you be more specific about what you mean by ‘all DMA interrupts’?
Documentation/devicetree/bindings/dma/bcm2835-dma.txt line 12
Quoted 5 lines
Documentation/devicetree/bindings/dma/bcm2835-dma.txt new file +5
-0+- #dma-cells: Must be <1>, used to represent the number of integer cells in +the dmas property of client devices. +- dma-channels: Maximum number of DMA channels available +- dma-requests: Number of DMA Requests. +- dma-channel-mask: Bit mask representing the channels available.
Should be brcm,dma-channel-mask
Quoted 35 lines
Documentation/devicetree/bindings/dma/bcm2835-dma.txt new file +35
-0+ +Example: + +dma: dma@7e007000 { + compatible = "brcm,bcm2835-dma"; + reg = <0x7e007000 0xf00>; + interrupts = <1 16 + 1 17 + 1 18 + 1 19 + 1 20 + 1 21 + 1 22 + 1 23 + 1 24 + 1 25 + 1 26 + 1 27 + 1 28>; + + #dma-cells = <1>; + dma-channels = <15>; + dma-requests = <32>; + dma-channel-mask = <0x7f35>; +}; + +DMA clients connected to the BCM2835 DMA controller must use the format +described in the dma.txt file, using a two-cell specifier for each channel: +a phandle plus one integer cells. +The two cells in order are: + +1. A phandle pointing to the DMA controller. +2. The DREQ number. + +Example:
Documentation/devicetree/bindings/dma/bcm2835-dma.txt line 57
Quoted 10 lines
Documentation/devicetree/bindings/dma/bcm2835-dma.txt new file +10
-0+ +bcm2835_i2s: i2s@7e203000 { + compatible = "brcm,bcm2835-i2s"; + reg = < 0x7e203000 0x20 + 0x7e101098 0x02>; + + dmas = <&dma 2 + &dma 3>; + dma-names = "tx", "rx"; +};
- k
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