pinctrl: sh-pfc: r7s72100 support V2

From: Magnus Damm <[email protected]>

Add r7s72100 PINCTRL support via sh-pfc V2. At this point the code provides enough support to allow use together with the gpio-rz driver. Incremental per-device patches will in the future be submitted on top of this base patch to allow PINCTRL enablement for each individual device.

Signed-off-by Magnus Damm <[email protected]>

---

Changes since V1:
- Moved RZ_PORT_PIN() macro
- Make use of _GP_GPIO() for 16-bit bank support
- Updated _P_DATA() and _P_FN() to control PIPC

Thanks to Laurent for the review.

 drivers/pinctrl/sh-pfc/Kconfig        |    5 +
 drivers/pinctrl/sh-pfc/Makefile       |    1
 drivers/pinctrl/sh-pfc/core.c         |    9 +
 drivers/pinctrl/sh-pfc/core.h         |    1
 drivers/pinctrl/sh-pfc/pfc-r7s72100.c |  161 ++++++++++++++++++++++++++++++
 5 files changed, 177 insertions(+)

drivers/pinctrl/sh-pfc/pfc-r7s72100.c new file +0 -0

10:47:26.000000000 +0900

drivers/pinctrl/sh-pfc/pfc-r7s72100.c new file +0 -0

@@ -0,0 +1,161 @@

+#define RZ_PORT_PIN(bank, pin) (((bank) * 16) + (pin))

drivers/pinctrl/sh-pfc/pfc-r7s72100.c new file +61 -0

+static const struct sh_pfc_pin_group pinmux_groups[] = {
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+};
+
+#define PFC_REG(idx, name, reg)						\
+	{ PINMUX_CFG_REG(__stringify(name), reg, 16, 1) {		\
+		P_##idx##_15_##name##_0, P_##idx##_15_##name##_1,	\
+		P_##idx##_14_##name##_0, P_##idx##_14_##name##_1,	\
+		P_##idx##_13_##name##_0, P_##idx##_13_##name##_1,	\
+		P_##idx##_12_##name##_0, P_##idx##_12_##name##_1,	\
+		P_##idx##_11_##name##_0, P_##idx##_11_##name##_1,	\
+		P_##idx##_10_##name##_0, P_##idx##_10_##name##_1,	\
+		P_##idx##_9_##name##_0, P_##idx##_9_##name##_1,		\
+		P_##idx##_8_##name##_0, P_##idx##_8_##name##_1,		\
+		P_##idx##_7_##name##_0, P_##idx##_7_##name##_1,		\
+		P_##idx##_6_##name##_0, P_##idx##_6_##name##_1,		\
+		P_##idx##_5_##name##_0, P_##idx##_5_##name##_1,		\
+		P_##idx##_4_##name##_0, P_##idx##_4_##name##_1,		\
+		P_##idx##_3_##name##_0, P_##idx##_3_##name##_1,		\
+		P_##idx##_2_##name##_0, P_##idx##_2_##name##_1,		\
+		P_##idx##_1_##name##_0, P_##idx##_1_##name##_1,		\
+		P_##idx##_0_##name##_0, P_##idx##_0_##name##_1 }	\
+	}
+
+#define PFC_REGS(idx)						\
+	PFC_REG(idx, PMC, (0xfcfe3400 + (idx * 4))),		\
+	PFC_REG(idx, PFC, (0xfcfe3500 + (idx * 4))),		\
+	PFC_REG(idx, PFCE, (0xfcfe3600 + (idx * 4))),		\
+	PFC_REG(idx, PFCAE, (0xfcfe3a00 + (idx * 4))),		\
+	PFC_REG(idx, PIBC, (0xfcfe7000 + (idx * 4))),		\
+	PFC_REG(idx, PBDC, (0xfcfe7100 + (idx * 4))),		\
+	PFC_REG(idx, PIPC, (0xfcfe7200 + (idx * 4)))
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+	PFC_REGS(0), PFC_REGS(1), PFC_REGS(2), PFC_REGS(3),
+	PFC_REGS(4), PFC_REGS(5), PFC_REGS(6), PFC_REGS(7),
+	PFC_REGS(8), PFC_REGS(9), PFC_REGS(10), PFC_REGS(11),
+	PFC_REG(12, PMC, 0xfcfe7b40),
+	PFC_REG(12, PIBC, 0xfcfe7f00),
+	{ },
+};
+
+const struct sh_pfc_soc_info r7s72100_pinmux_info = {
+	.name = "r7s72100_pfc",
+
+	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+	.pins = pinmux_pins,
+	.nr_pins = ARRAY_SIZE(pinmux_pins),
+	.groups = pinmux_groups,
+	.nr_groups = ARRAY_SIZE(pinmux_groups),
+	.functions = pinmux_functions,
+	.nr_functions = ARRAY_SIZE(pinmux_functions),
+
+	.cfg_regs = pinmux_config_regs,
+
+	.gpio_data = pinmux_data,
+	.gpio_data_size = ARRAY_SIZE(pinmux_data),
+};

Hi,

Review

Quoted 7 lines

(quoted diff) +7 -0

+#define _P_DATA(bank, pin, name, sfx)                                        \
+     PINMUX_DATA(name##_DATA, name##_PMC_0, name##_PIPC_0,           \
+                 name##_PIBC_1, name##_PBDC_1)
+
+#define _P_FN(n, fn, pfcae, pfce, pfc)                                       \
+     PINMUX_DATA(n##_MARK_FN##fn, n##_PMC_1, n##_PIPC_1,             \
+                 n##_PFCAE_##pfcae, n##_PFCE_##pfce, n##_PFC_##pfc)

I need to apply this patch, otherwise my i2c pinmuxing fails?

Quoted 10 lines

Review

Quoted 8 lines

(quoted diff) +7 -0

+#define _P_DATA(bank, pin, name, sfx)                                        \
+     PINMUX_DATA(name##_DATA, name##_PMC_0, name##_PIPC_0,           \
+                 name##_PIBC_1, name##_PBDC_1)
+
+#define _P_FN(n, fn, pfcae, pfce, pfc)                                       \
+     PINMUX_DATA(n##_MARK_FN##fn, n##_PMC_1, n##_PIPC_1,             \
+                 n##_PFCAE_##pfcae, n##_PFCE_##pfce, n##_PFC_##pfc)

I need to apply this patch, otherwise my i2c pinmuxing fails?

Thanks. It looks to me like the _P_FN() bits would be mainly needed. Can you try to omit the _P_DATA() portion and check if it is still behaving as expected?

Quoted 11 lines

Quoted 10 lines

Review

Quoted 8 lines

(quoted diff) +7 -0

+#define _P_DATA(bank, pin, name, sfx)                                        \
+     PINMUX_DATA(name##_DATA, name##_PMC_0, name##_PIPC_0,           \
+                 name##_PIBC_1, name##_PBDC_1)
+
+#define _P_FN(n, fn, pfcae, pfce, pfc)                                       \
+     PINMUX_DATA(n##_MARK_FN##fn, n##_PMC_1, n##_PIPC_1,             \
+                 n##_PFCAE_##pfcae, n##_PFCE_##pfce, n##_PFC_##pfc)

I need to apply this patch, otherwise my i2c pinmuxing fails?

Quoted 3 lines

Thanks. It looks to me like the _P_FN() bits would be mainly needed. Can you try to omit the _P_DATA() portion and check if it is still behaving as expected?

Nope, doesn't work.

static const struct sh_pfc_function pinmux_functions[] = { };

Hi Magnus,

Thank you for the patches.

drivers/pinctrl/sh-pfc/pfc-r7s72100.c 2013-12-16

Quoted 16 lines · On Tuesday 17 December 2013 11:38:14 Magnus Damm wrote:

From: Magnus Damm <[email protected]>

Introduce macros that allow description of one pin per line. Compared to the other ways of doing this, using this style we can compresses the description of each pin from 9 to 1 line.

Signed-off-by Magnus Damm <[email protected]>

---

This patch uses RZ_PMX_GROUP and RZ_GROUPS, thanks Laurent!

 drivers/pinctrl/sh-pfc/pfc-r7s72100.c |   21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

drivers/pinctrl/sh-pfc/pfc-r7s72100.c 2013-12-16 renamed from drivers/pinctrl/sh-pfc/pfc-r7s72100.c +0 -0

19:14:30.000000000

drivers/pinctrl/sh-pfc/pfc-r7s72100.c 2013-12-16

Quoted 5 lines

+0900 @@ -98,9 +98,30 @@ static struct sh_pfc_pin pinmux_pins[] >>
#define RZ_PORT_PIN(bank, pin) (((bank) * 16) + (pin))

drivers/pinctrl/sh-pfc/pfc-r7s72100.c 2013-12-16 renamed from drivers/pinctrl/sh-pfc/pfc-r7s72100.c +2 -0

+#define __RZ_STR(pfx, hw, bank, pin, sfx)            \
+     pfx##_##hw##_p##bank##_##pin####sfx

Do you mean s/####sfx/##sfx/ ?

Quoted 5 lines

drivers/pinctrl/sh-pfc/pfc-r7s72100.c 2013-12-16 renamed from drivers/pinctrl/sh-pfc/pfc-r7s72100.c +5 -0

+
+#define RZ_PIN_AND_MUX(pfx, hw, bank, pin, fn)                               \
+static const unsigned int __RZ_STR(pfx, hw, bank, pin, _pins)[] = {  \
+     RZ_PORT_PIN(bank, pin),                                         \
+};                                                                   \

drivers/pinctrl/sh-pfc/pfc-r7s72100.c 2013-12-16

Quoted 3 lines

drivers/pinctrl/sh-pfc/pfc-r7s72100.c 2013-12-16 renamed from drivers/pinctrl/sh-pfc/pfc-r7s72100.c +3 -0

+static const unsigned int __RZ_STR(pfx, hw, bank, pin, _mux)[] = {   \
+     P_##bank##_##pin##_MARK_FN##fn,                                 \
+};

I would have preferred keeping the trailing semicolon (and comma in the RZ_GROUPS macro) out of the macro, but that won't be possible as the RZ_PIN_AND_MUX and RZ_GROUPS macros are used as arguments to the SCIF macros in the next patch.

drivers/pinctrl/sh-pfc/pfc-r7s72100.c 2013-12-16

Quoted 5 lines

drivers/pinctrl/sh-pfc/pfc-r7s72100.c 2013-12-16 renamed from drivers/pinctrl/sh-pfc/pfc-r7s72100.c +5 -0

+
+#define RZ_PMX_GROUP(pfx, hw, bank, pin, fn) \
+     SH_PFC_PIN_GROUP(pfx##_##hw##_p##bank##_##pin),
+
+#define __RZ_GROUPS(x) #x

Can't you replace __RZ_GROUPS() by __stringify() ?

drivers/pinctrl/sh-pfc/pfc-r7s72100.c 2013-12-16

Quoted 8 lines

drivers/pinctrl/sh-pfc/pfc-r7s72100.c 2013-12-16 renamed from drivers/pinctrl/sh-pfc/pfc-r7s72100.c +5 -0

+#define RZ_GROUPS(pfx, hw, bank, pin, fn) \
+     __RZ_GROUPS(pfx##_##hw##_p##bank##_##pin),
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 };
 
+static const char * const scif2_groups[] = {
+};

I think this should be part of patch 04/05.

+0900 @@ -117,12 +117,170 @@ static const unsigned int __RZ_STR(pfx,
#define RZ_GROUPS(pfx, hw, bank, pin, fn) \

drivers/pinctrl/sh-pfc/pfc-r7s72100.c +0 -0

 	__RZ_GROUPS(pfx##_##hw##_p##bank##_##pin),
 

drivers/pinctrl/sh-pfc/pfc-r7s72100.c +148 -0

+
+#define SCIF1(fn)			\
+	fn(scif1, cts, 2, 3, 6)		\
+	fn(scif1, clk, 2, 4, 6)		\
+	fn(scif1, txd, 2, 5, 6)		\
+	fn(scif1, rxd, 2, 6, 6)		\
+	fn(scif1, rts, 2, 7, 6)		\
+	fn(scif1, clk, 4, 11, 7)	\
+	fn(scif1, txd, 4, 12, 7)	\
+	fn(scif1, rxd, 4, 13, 7)	\
+	fn(scif1, clk, 6, 11, 5)	\
+	fn(scif1, txd, 6, 12, 5)	\
+	fn(scif1, rxd, 6, 13, 5)	\
+	fn(scif1, clk, 9, 2, 4)		\
+	fn(scif1, txd, 9, 3, 4)		\
+	fn(scif1, rxd, 9, 4, 4)		\
+	fn(scif1, cts, 9, 5, 4)		\
+	fn(scif1, rts, 9, 6, 4)
+
+#define SCIF2(fn)			\
+	fn(scif2, clk, 3, 0, 4)		\
+	fn(scif2, txd, 3, 1, 4)		\
+	fn(scif2, rxd, 3, 2, 4)		\
+	fn(scif2, txd, 3, 0, 6)		\
+	fn(scif2, clk, 4, 1, 5)		\
+	fn(scif2, txd, 4, 2, 5)		\
+	fn(scif2, rxd, 4, 3, 5)		\
+	fn(scif2, txd, 4, 14, 7)	\
+	fn(scif2, rxd, 4, 15, 7)	\
+	fn(scif2, txd, 6, 2, 7)		\
+	fn(scif2, rxd, 6, 3, 7)		\
+	fn(scif2, clk, 8, 3, 7)		\
+	fn(scif2, rxd, 8, 4, 7)		\
+	fn(scif2, txd, 8, 6, 7)
+
+#define SCIF3(fn)			\
+	fn(scif3, clk, 3, 4, 7)		\
+	fn(scif3, txd, 3, 5, 7)		\
+	fn(scif3, rxd, 3, 6, 7)		\
+	fn(scif3, clk, 5, 2, 5)		\
+	fn(scif3, txd, 5, 3, 5)		\
+	fn(scif3, rxd, 5, 4, 5)		\
+	fn(scif3, rxd, 6, 0, 7)		\
+	fn(scif3, txd, 6, 1, 7)		\
+	fn(scif3, txd, 8, 8, 7)		\
+	fn(scif3, rxd, 8, 9, 7)
+
+#define SCIF4(fn)			\
+	fn(scif4, txd, 5, 0, 5)		\
+	fn(scif4, rxd, 5, 1, 5)		\
+	fn(scif4, clk, 7, 0, 4)		\
+	fn(scif4, txd, 7, 1, 4)		\
+	fn(scif4, rxd, 7, 2, 4)		\
+	fn(scif4, txd, 8, 14, 7)	\
+	fn(scif4, rxd, 8, 15, 7)
+
+#define SCIF5(fn)			\
+	fn(scif5, cts, 6, 3, 5)		\
+	fn(scif5, rts, 6, 4, 5)		\
+	fn(scif5, clk, 6, 5, 5)		\
+	fn(scif5, txd, 6, 6, 5)		\
+	fn(scif5, rxd, 6, 7, 5)		\
+	fn(scif5, cts, 7, 15, 4)	\
+	fn(scif5, clk, 8, 0, 4)		\
+	fn(scif5, txd, 8, 1, 4)		\
+	fn(scif5, rxd, 8, 2, 4)		\
+	fn(scif5, rts, 8, 3, 4)		\
+	fn(scif5, rxd, 8, 11, 5)	\
+	fn(scif5, clk, 8, 12, 5)	\
+	fn(scif5, txd, 8, 13, 5)	\
+	fn(scif5, cts, 11, 7, 3)	\
+	fn(scif5, rts, 11, 8, 3)	\
+	fn(scif5, clk, 11, 9, 3)	\
+	fn(scif5, txd, 11, 10, 3)	\
+	fn(scif5, rxd, 11, 11, 3)
+
+#define SCIF6(fn)			\
+	fn(scif6, txd, 5, 6, 5)		\
+	fn(scif6, rxd, 5, 7, 5)		\
+	fn(scif6, clk, 6, 13, 4)	\
+	fn(scif6, txd, 6, 14, 4)	\
+	fn(scif6, rxd, 6, 15, 4)	\
+	fn(scif6, clk, 11, 0, 4)	\
+	fn(scif6, txd, 11, 1, 4)	\
+	fn(scif6, rxd, 11, 2, 4)
+
+#define SCIF7(fn)			\
+	fn(scif7, clk, 7, 3, 4)		\
+	fn(scif7, txd, 7, 4, 4)		\
+	fn(scif7, rxd, 7, 5, 4)		\
+	fn(scif7, cts, 7, 6, 4)		\
+	fn(scif7, rts, 7, 7, 4)
+
+SCIF0(RZ_PIN_AND_MUX)
+SCIF1(RZ_PIN_AND_MUX)
+SCIF2(RZ_PIN_AND_MUX)
+SCIF3(RZ_PIN_AND_MUX)
+SCIF4(RZ_PIN_AND_MUX)
+SCIF5(RZ_PIN_AND_MUX)
+SCIF6(RZ_PIN_AND_MUX)
+SCIF7(RZ_PIN_AND_MUX)
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+	SCIF0(RZ_PMX_GROUP)
+	SCIF1(RZ_PMX_GROUP)
+	SCIF2(RZ_PMX_GROUP)
+	SCIF3(RZ_PMX_GROUP)
+	SCIF4(RZ_PMX_GROUP)
+	SCIF5(RZ_PMX_GROUP)
+	SCIF6(RZ_PMX_GROUP)
+	SCIF7(RZ_PMX_GROUP)
+};
+
+static const char * const scif0_groups[] = {
+	SCIF0(RZ_GROUPS)
+};
+
+static const char * const scif1_groups[] = {
+	SCIF1(RZ_GROUPS)
 };
 
 static const char * const scif2_groups[] = {
+	SCIF2(RZ_GROUPS)
+};
+
+static const char * const scif3_groups[] = {
+	SCIF3(RZ_GROUPS)
+};
+
+static const char * const scif4_groups[] = {
+	SCIF4(RZ_GROUPS)
+};
+
+static const char * const scif5_groups[] = {
+	SCIF5(RZ_GROUPS)
+};
+
+static const char * const scif6_groups[] = {
+	SCIF6(RZ_GROUPS)
 };
+
+static const char * const scif7_groups[] = {
+	SCIF7(RZ_GROUPS)
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(scif0),
+	SH_PFC_FUNCTION(scif1),
+	SH_PFC_FUNCTION(scif2),
+	SH_PFC_FUNCTION(scif3),
+	SH_PFC_FUNCTION(scif4),
+	SH_PFC_FUNCTION(scif5),
+	SH_PFC_FUNCTION(scif6),
+	SH_PFC_FUNCTION(scif7),
 };
 
 #define PFC_REG(idx, name, reg)						\

Hi Magnus,

Thank you for the patch.

drivers/pinctrl/sh-pfc/pfc-r7s72100.c 2013-12-17

Quoted 15 lines · On Tuesday 17 December 2013 11:38:23 Magnus Damm wrote:

From: Magnus Damm <[email protected]>

Add support for SCIF functions SCK, TXD, RXD, CTS and RTS to the r7s72100 PINCTRL code. There are two possible pins that can be used for TXD (Port 3 Pin 0 Function 6 and Port 3 Pin 1 Function 4) and because of that are pins broken out into separate functions.

Signed-off-by Magnus Damm <[email protected]>

---

 drivers/pinctrl/sh-pfc/pfc-r7s72100.c |  158 ++++++++++++++++++++++++++++++
 1 file changed, 158 insertions(+)

drivers/pinctrl/sh-pfc/pfc-r7s72100.c 2013-12-17 renamed from drivers/pinctrl/sh-pfc/pfc-r7s72100.c +0 -0

01:09:20.000000000

Quoted 4 lines

+0900 @@ -117,12 +117,170 @@ static const unsigned int __RZ_STR(pfx,

 #define RZ_GROUPS(pfx, hw, bank, pin, fn) \
      __RZ_GROUPS(pfx##_##hw##_p##bank##_##pin),

drivers/pinctrl/sh-pfc/pfc-r7s72100.c 2013-12-17

Quoted 10 lines

drivers/pinctrl/sh-pfc/pfc-r7s72100.c 2013-12-17 renamed from drivers/pinctrl/sh-pfc/pfc-r7s72100.c +10 -0

+#define SCIF0(fn)                    \
+     fn(scif0, clk, 2, 13, 6)        \
+     fn(scif0, txd, 2, 14, 6)        \
+     fn(scif0, rxd, 2, 15, 6)        \
+     fn(scif0, clk, 4, 8, 7)         \
+     fn(scif0, txd, 4, 9, 7)         \
+     fn(scif0, rxd, 4, 10, 7)        \
+     fn(scif0, clk, 6, 8, 5)         \
+     fn(scif0, txd, 6, 9, 5)         \
+     fn(scif0, rxd, 6, 10, 5)

The SCIF0 SCK, TXD and RXD pins are grouped together with three options to choose from. Unlike the PFC devices we support so far, the driver allows picking pins individually. This allows greater flexibility, at the cost of a more verbose PFC DT node.

I assume that this is correct, but could you please confirm that the SoC really allows picking pins individually (for instance using P2.14 as SCIF0 TXD together with P6.10 as SCIF0 RXD) ?

I also wonder whether other currently supported SoCs wouldn't happen to also support picking pins from different groups, even though they name the groups differently.

Quoted 35 lines · Laurent Pinchart

drivers/pinctrl/sh-pfc/pfc-r7s72100.c 2013-12-17

Quoted 15 lines · On Tuesday 17 December 2013 11:38:23 Magnus Damm wrote:

From: Magnus Damm <[email protected]>

Add support for SCIF functions SCK, TXD, RXD, CTS and RTS to the r7s72100 PINCTRL code. There are two possible pins that can be used for TXD (Port 3 Pin 0 Function 6 and Port 3 Pin 1 Function 4) and because of that are pins broken out into separate functions.

Signed-off-by Magnus Damm <[email protected]>

---

 drivers/pinctrl/sh-pfc/pfc-r7s72100.c |  158 +++++++++++++++++++++++++++
 1 file changed, 158 insertions(+)

drivers/pinctrl/sh-pfc/pfc-r7s72100.c 2013-12-17 renamed from drivers/pinctrl/sh-pfc/pfc-r7s72100.c +0 -0

01:09:20.000000000

Quoted 5 lines

+0900 @@ -117,12 +117,170 @@ static const unsigned int __RZ_STR(pfx,

 #define RZ_GROUPS(pfx, hw, bank, pin, fn) \
      __RZ_GROUPS(pfx##_##hw##_p##bank##_##pin),

drivers/pinctrl/sh-pfc/pfc-r7s72100.c 2013-12-17

Quoted 10 lines

drivers/pinctrl/sh-pfc/pfc-r7s72100.c 2013-12-17 renamed from drivers/pinctrl/sh-pfc/pfc-r7s72100.c +10 -0

+#define SCIF0(fn)                    \
+     fn(scif0, clk, 2, 13, 6)        \
+     fn(scif0, txd, 2, 14, 6)        \
+     fn(scif0, rxd, 2, 15, 6)        \
+     fn(scif0, clk, 4, 8, 7)         \
+     fn(scif0, txd, 4, 9, 7)         \
+     fn(scif0, rxd, 4, 10, 7)        \
+     fn(scif0, clk, 6, 8, 5)         \
+     fn(scif0, txd, 6, 9, 5)         \
+     fn(scif0, rxd, 6, 10, 5)

Quoted 4 lines

The SCIF0 SCK, TXD and RXD pins are grouped together with three options to choose from. Unlike the PFC devices we support so far, the driver allows picking pins individually. This allows greater flexibility, at the cost of a more verbose PFC DT node.

You need more detailed PFC data, yes, but I'm not sure if "Unlike the PFC devices we support so far" is a correct statement. =)

Quoted 3 lines

I assume that this is correct, but could you please confirm that the SoC really allows picking pins individually (for instance using P2.14 as SCIF0 TXD together with P6.10 as SCIF0 RXD) ?

Your example would work just fine, yes. I don't have any hardware to test that though. I suspect the same would be fine on all of our SoCs actually, unless

Quoted 3 lines

I also wonder whether other currently supported SoCs wouldn't happen to also support picking pins from different groups, even though they name the groups differently.

It seems to me that in general the hardware has much more flexibility than what the PINCTRL groups actually expose today. In the end it depends on the actual hardware, so its a case by case thing:

A) RZ series: Individual per-pin settings always available

B) R-Mobile series (PORTnCR + MSELnCR): Individual per-pin settings usually available

C) R-Car series (IPSRnn + MOD_SEL): Shared to some degree, but often still allows individual control.

So with the current PINCTRL interface it looks like we have introduced some artificial limitation based on software grouping even though the actual hardware often can handle per-pin settings.

pinctrl: sh-pfc: r7s72100 support V2

[PATCH 01/05 v2] pinctrl: sh-pfc: Rework _GP_GPIO, introduce _GP_GPIO32 [PATCH 02/05 v2] pinctrl: sh-pfc: r7s72100 base support [PATCH 03/05 v2] pinctrl: sh-pfc: r7s72100 single pin macros [PATCH 04/05 v2] pinctrl: sh-pfc: r7s72100 SCIF support [PATCH 05/05 v2] pinctrl: sh-pfc: r8a7791 and r7s72100 binding docs

This is V2 of r7s72100 PFC support. Included this time is:
- Some slight rework of shared sh-pfc macros
- Complete r7s72100 SCIF support
- Binding documentation

If you prefer me to adjust this code somehow then please let me know.

Signed-off-by Magnus Damm <[email protected]>

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Written against renesas.git tag renesas-devel-v3.13-rc3-20131214v2

 Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt |    2
 drivers/pinctrl/sh-pfc/Kconfig                                    |    5
 drivers/pinctrl/sh-pfc/Makefile                                   |    1
 drivers/pinctrl/sh-pfc/core.c                                     |    9
 drivers/pinctrl/sh-pfc/core.h                                     |    1
 drivers/pinctrl/sh-pfc/pfc-r7s72100.c                             |  340 ++
 drivers/pinctrl/sh-pfc/sh_pfc.h                                   |    9
 7 files changed, 363 insertions(+), 4 deletions(-)