clk: clk-divider: fix divisor > 255 bug
Subsystems (2)
PATCH 1/1 clk: clk-divider: fix divisor > 255 bug
Commit 6d9252bd9a4bb (clk: Add support for power of two type dividers) merged in v3.6 added the _get_val function to convert a divisor value to a register field value depending on the flags. However it used the type u8 for the div field, causing divisors larger than 255 to be masked and the resultant clock rate to be too high.
E.g. in my case an 11bit divider was supposed to divide 24.576 MHz down to 32.768KHz. The divisor was correctly calculated as 750 (0x2ee). This was masked to 238 (0xee) resulting in a frequency of 103.26KHz.
---
Since this bug was introduced in 3.6, it probably should by applied to stable 3.10 and 3.12.
--- drivers/clk/clk-divider.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/clk-divider.c +1 -1
@@ -87,7 +87,7 @@ static unsigned int _get_table_val(const struct clk_div_table *table,return 0 ; } -static unsigned int _get_val (struct clk_divider *divider,u8 div) +static unsigned int _get_val (struct clk_divider *divider,unsigned int div) {if (divider->flags &CLK_DIVIDER_ONE_BASED )return div;
Signature · 1 line
1.8.1.2
PATCH 1/1 clk: clk-divider: fix divisor > 255 bug
Quoting James Hogan (2013-12-16 02:41:38)
Quoted 11 lines
Commit
6d9252bd9a4bb(clk: Add support for power of two type dividers) merged in v3.6 added the_get_valfunction to convert a divisor value to a register field value depending on the flags. However it used the type u8 for the div field, causing divisors larger than 255 to be masked and the resultant clock rate to be too high.E.g. in my case an 11bit divider was supposed to divide 24.576 MHz down to 32.768KHz. The divisor was correctly calculated as 750 (
0x2ee). This was masked to 238 (0xee) resulting in a frequency of 103.26KHz.Signed-off-by James Hogan <[email protected]>
Taken into clk-next. Thanks for the fix!
Regards,
Mike
Quoted 28 lines
Cc Rajendra Nayak <[email protected]>Cc Mike Turquette <[email protected]>Cc linux-arm-kernel at lists.infradead.orgCc stable at vger.kernel.org---
Since this bug was introduced in 3.6, it probably should by applied to stable 3.10 and 3.12.--- drivers/clk/clk-divider.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/clk/clk-divider.c +1
-1@@ -87,7 +87,7 @@ static unsigned int _get_table_val(const struct clk_div_table *table,return 0 ; } -static unsigned int _get_val (struct clk_divider *divider,u8 div) +static unsigned int _get_val (struct clk_divider *divider,unsigned int div) {if (divider->flags &CLK_DIVIDER_ONE_BASED )return div;Signature · 1 line
1.8.1.2
Quoted 7 lines · Mike Turquette
Quoting James Hogan (2013-12-16 02:41:38)
Quoted 6 lines
Commit
6d9252bd9a4bb(clk: Add support for power of two type dividers) merged in v3.6 added the_get_valfunction to convert a divisor value to a register field value depending on the flags. However it used the type u8 for the div field, causing divisors larger than 255 to be masked and the resultant clock rate to be too high.
Quoted 7 lines
Quoted 5 lines
E.g. in my case an 11bit divider was supposed to divide 24.576 MHz down to 32.768KHz. The divisor was correctly calculated as 750 (
0x2ee). This was masked to 238 (0xee) resulting in a frequency of 103.26KHz.Signed-off-by James Hogan <[email protected]>Taken into clk-next. Thanks for the fix!
Thanks Mike, is there any chance of getting this into v3.13, or is it too late?
Cheers
James
Quoted 19 lines
Quoted 19 lines
Cc Rajendra Nayak <[email protected]>Cc Mike Turquette <[email protected]>Cc linux-arm-kernel at lists.infradead.orgCc stable at vger.kernel.org---
Since this bug was introduced in 3.6, it probably should by applied to stable 3.10 and 3.12.--- drivers/clk/clk-divider.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/clk/clk-divider.c +0
-0@@ -87,7 +87,7 @@ static unsigned int _get_table_val(const struct clk_div_table *table,return 0 ; }
Quoted 9 lines
Quoted 9 lines
drivers/clk/clk-divider.c +1
-1-static unsigned int _get_val (struct clk_divider *divider,u8 div) +static unsigned int _get_val (struct clk_divider *divider,unsigned int div) {if (divider->flags &CLK_DIVIDER_ONE_BASED )return div;Signature · 1 line
1.8.1.2
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PATCH 1/1 clk: clk-divider: fix divisor > 255 bug
Quoting James Hogan (2014-01-06 02:07:58)
Quoted 12 lines · Mike Turquette
Quoted 11 lines
Quoting James Hogan (2013-12-16 02:41:38)
Quoted 10 lines
Commit
6d9252bd9a4bb(clk: Add support for power of two type dividers) merged in v3.6 added the_get_valfunction to convert a divisor value to a register field value depending on the flags. However it used the type u8 for the div field, causing divisors larger than 255 to be masked and the resultant clock rate to be too high.E.g. in my case an 11bit divider was supposed to divide 24.576 MHz down to 32.768KHz. The divisor was correctly calculated as 750 (
0x2ee). This was masked to 238 (0xee) resulting in a frequency of 103.26KHz.
Quoted 6 lines
Quoted 3 lines
Quoted 1 line
Signed-off-by James Hogan <[email protected]>Taken into clk-next. Thanks for the fix!
Thanks Mike, is there any chance of getting this into v3.13, or is it too late?
I had applied it to clk-next but I just moved it over to my -fixes branch. Will send later today.
Regards,
Mike
Quoted 33 lines
Cheers
JamesQuoted 28 lines
Quoted 28 lines
Cc Rajendra Nayak <[email protected]>Cc Mike Turquette <[email protected]>Cc linux-arm-kernel at lists.infradead.orgCc stable at vger.kernel.org---
Since this bug was introduced in 3.6, it probably should by applied to stable 3.10 and 3.12.--- drivers/clk/clk-divider.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/clk/clk-divider.c +1
-1@@ -87,7 +87,7 @@ static unsigned int _get_table_val(const struct clk_div_table *table,return 0 ; } -static unsigned int _get_val (struct clk_divider *divider,u8 div) +static unsigned int _get_val (struct clk_divider *divider,unsigned int div) {if (divider->flags &CLK_DIVIDER_ONE_BASED )return div;Signature · 1 line
1.8.1.2