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ARM: omap3: Split the pinmux core device

PATCH New Laurent Pinchart 3 participants 10 messages Dec 20, 2013 – Jan 9, 2014

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Laurent Pinchart

author
#0 lore raw

v2 cover ARM: omap3: Split the pinmux core device

Hello,

While working on the OMAP3 ISP driver I've run into a failure to request a memory region already requested by the pinctrl-single driver. This patch set is an attempt to fix the problem.

Changes since v1:

- Rebased on top of Tony's master branch
- Handle IGEP LEDs
- Added Tony's PINCTRL macros
- Fixed unbalanced parentheses in Tony's PINCTRL macros ;-)

Laurent Pinchart (1):
ARM: omap3: Split the pinmux core device

Tony Lindgren (1):
ARM: dts: Add omap specific pinctrl defines to use padconf addresses

 arch/arm/boot/dts/omap3-beagle-xm.dts | 40 +++++++++++++++++----------
 arch/arm/boot/dts/omap3-beagle.dts    | 40 +++++++++++++++++----------
 arch/arm/boot/dts/omap3-igep.dtsi     |  2 --
 arch/arm/boot/dts/omap3-igep0020.dts  | 52 +++++++++++++++++++----------------
 arch/arm/boot/dts/omap3-igep0030.dts  | 10 ++++---
 arch/arm/boot/dts/omap3-zoom3.dts     | 23 ++++++++++------
 arch/arm/boot/dts/omap3.dtsi          | 13 ++++++++-
 include/dt-bindings/pinctrl/omap.h    | 19 +++++++++++++
 8 files changed, 133 insertions(+), 66 deletions(-)
Signature · 3 lines
Regards,

Laurent Pinchart
author
#1 lore raw

PATCH v2 1/2 ARM: dts: Add omap specific pinctrl defines to use padconf addresses

From: Tony Lindgren <[email protected]>

As we have one to three pinctrl-single instances for each SoC it is a bit confusing to configure the padconf register offset from the base of the padconf register base.

Let's add macros that allow using the physical address of the padconf register directly, or in most cases, just the last 16-bits of the address as they are shown in the documentation.

Note that most documentation shows two padconf registers for each 32-bit address, so adding 2 to the documentation address is needed for the second padconf register as we treat them as 16-bit registers for omap3+.

For example, omap36xx documentation shows sdmmc2_clk at 0x48002158, so we can just use the last 16-bits of that value:

	pinctrl-single,pins = <
		OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)
		...
	>;

And we don't need to separately calculate the offset from the 0x2030 base:

	pinctrl-single,pins = <
		0x128 (PIN_INPUT_PULLUP | MUX_MODE0)
		...
	>;

Naturally both ways of defining the registers can be used, and I'm not saying we should replace all the existing defines. But it may be handy to use these macros for new entries and when doing other related .dts file clean-up.

Signed-off-by Tony Lindgren <[email protected]>
Signed-off-by Laurent Pinchart <[email protected]>
---
 include/dt-bindings/pinctrl/omap.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
include/dt-bindings/pinctrl/omap.h +19 -0
index bed35e3..f8484ee 100644
@@ -49,5 +49,24 @@
 #define PIN_OFF_INPUT_PULLDOWN	(OFF_EN | OFF_PULL_EN)
 #define PIN_OFF_WAKEUPENABLE	WAKEUP_EN
 
+/*
+ * Macros to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define OMAP_IOPAD_OFFSET(pa, offset)	(((pa) & 0xffff) - (offset))
+
+#define OMAP2420_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
+#define OMAP2430_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3_CORE1_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3_CORE2_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
+#define OMAP3_WKUP_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
+#define AM33XX_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define OMAP4_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x0040) (val)
+#define OMAP4_WKUP_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0xe040) (val)
+#define AM4372_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define OMAP5_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2840) (val)
+#define OMAP5_WKUP_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0xc840) (val)
+#define DRA7XX_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x3400) (val)
+
 #endif
Signature · 1 line
1.8.3.2
#2 lore raw

PATCH v2 1/2 ARM: dts: Add omap specific pinctrl defines to use padconf addresses

Review

Quoted 11 lines · Laurent Pinchart

From: Tony Lindgren <[email protected]>

(quoted diff) +10 -0
+/*
+ * Macros to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define OMAP_IOPAD_OFFSET(pa, offset)	(((pa) & 0xffff) - (offset))
+
+#define OMAP2420_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
+#define OMAP2430_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3_CORE1_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3_CORE2_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)

Sorry for the delay on these, I'm only now getting back to looking at all the emails since the holidays :)

After looking at Nishant's omap3 pinctrl core2 patch, looks like we need to have separate OMAP3430_CORE2_IOPAD and OMAP3630_CORE2_IOPAD defines.

I've committed the following updated version of this patch into omap-for-v3.14/dt branch.

Regards,

Tony

8< ----------------------
From: Tony Lindgren <[email protected]>
Date: Tue, 7 Jan 2014 14:01:38 -0800
Subject: [PATCH] ARM: dts: Add omap specific pinctrl defines to use padconf addresses

As we have one to three pinctrl-single instances for each SoC it is a bit confusing to configure the padconf register offset from the base of the padconf register base.

Let's add macros that allow using the physical address of the padconf register directly, or in most cases, just the last 16-bits of the address as they are shown in the documentation.

Note that most documentation shows two padconf registers for each 32-bit address, so adding 2 to the documentation address is needed for the second padconf register as we treat them as 16-bit registers for omap3+.

For example, omap36xx documentation shows sdmmc2_clk at 0x48002158, so we can just use the last 16-bits of that value:

	pinctrl-single,pins = <
		OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)
		...
	>;

And we don't need to separately calculate the offset from the 0x2030 base:

	pinctrl-single,pins = <
		0x128 (PIN_INPUT_PULLUP | MUX_MODE0)
		...
	>;

Naturally both ways of defining the registers can be used, and I'm not saying we should replace all the existing defines. But it may be handy to use these macros for new entries and when doing other related .dts file clean-up.

Signed-off-by Laurent Pinchart <[email protected]>
[tony at atomide.com: updated for 3430 vs 3630 core2 range]
Signed-off-by Tony Lindgren <[email protected]>
include/dt-bindings/pinctrl/omap.h +20 -0
@@ -49,5 +49,25 @@
 #define PIN_OFF_INPUT_PULLDOWN	(OFF_EN | OFF_PULL_EN)
 #define PIN_OFF_WAKEUPENABLE	WAKEUP_EN
 
+/*
+ * Macros to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define OMAP_IOPAD_OFFSET(pa, offset)	(((pa) & 0xffff) - (offset))
+
+#define OMAP2420_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
+#define OMAP2430_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3_CORE1_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3430_CORE2_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
+#define OMAP3630_CORE2_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
+#define OMAP3_WKUP_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
+#define AM33XX_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define OMAP4_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x0040) (val)
+#define OMAP4_WKUP_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0xe040) (val)
+#define AM4372_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define OMAP5_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2840) (val)
+#define OMAP5_WKUP_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0xc840) (val)
+#define DRA7XX_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x3400) (val)
+
 #endif
author
#3 lore raw

PATCH v2 1/2 ARM: dts: Add omap specific pinctrl defines to use padconf addresses

Hi Tony,

Quoted 18 lines · On Tuesday 07 January 2014 14:30:21 Tony Lindgren wrote:

Review

Quoted 13 lines · Laurent Pinchart

From: Tony Lindgren <[email protected]>

include/dt-bindings/pinctrl/omap.h +7 -0
+/*
+ * Macros to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define OMAP_IOPAD_OFFSET(pa, offset)	(((pa) & 0xffff) - (offset))
+
+#define OMAP2420_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x0030)

(val)
+#define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030)
(val)

(quoted diff) +2 -0
+#define OMAP3_CORE1_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3_CORE2_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)

Sorry for the delay on these, I'm only now getting back to looking at all the emails since the holidays :)

Quoted 2 lines

After looking at Nishant's omap3 pinctrl core2 patch, looks like we need to have separate OMAP3430_CORE2_IOPAD and OMAP3630_CORE2_IOPAD defines.

That was my first impression as well, but I think we actually don't need to. The OMAP3430 just has no useful registers in the 0x25a0 - 0x25d7 area, so we can make the CORE2 macro span that for both 3430 and 3630.

Quoted 62 lines

I've committed the following updated version of this patch into omap-for-v3.14/dt branch.

Regards,

Tony

8< ----------------------
From: Tony Lindgren <[email protected]>
Date: Tue, 7 Jan 2014 14:01:38 -0800
Subject: [PATCH] ARM: dts: Add omap specific pinctrl defines to use padconf addresses

As we have one to three pinctrl-single instances for each SoC it is a bit confusing to configure the padconf register offset from the base of the padconf register base.

Let's add macros that allow using the physical address of the padconf register directly, or in most cases, just the last 16-bits of the address as they are shown in the documentation.

Note that most documentation shows two padconf registers for each 32-bit address, so adding 2 to the documentation address is needed for the second padconf register as we treat them as 16-bit registers for omap3+.

For example, omap36xx documentation shows sdmmc2_clk at 0x48002158, so we can just use the last 16-bits of that value:

	pinctrl-single,pins = <
		OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)
		...

	>;

And we don't need to separately calculate the offset from the 0x2030 base:

	pinctrl-single,pins = <
		0x128 (PIN_INPUT_PULLUP | MUX_MODE0)
		...

	>;

Naturally both ways of defining the registers can be used, and I'm not saying we should replace all the existing defines. But it may be handy to use these macros for new entries and when doing other related .dts file clean-up.

Signed-off-by Laurent Pinchart <[email protected]>
[[email protected]: updated for 3430 vs 3630 core2 range]
Signed-off-by Tony Lindgren <[email protected]>
include/dt-bindings/pinctrl/omap.h +3 -0
@@ -49,5 +49,25 @@
 #define PIN_OFF_INPUT_PULLDOWN	(OFF_EN | OFF_PULL_EN)
 #define PIN_OFF_WAKEUPENABLE	WAKEUP_EN
 
+/*
+ * Macros to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.

include/dt-bindings/pinctrl/omap.h line 64

Quoted 10 lines
include/dt-bindings/pinctrl/omap.h +8 -0
+ */
+#define OMAP_IOPAD_OFFSET(pa, offset)	(((pa) & 0xffff) - (offset))
+
+#define OMAP2420_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
+#define OMAP2430_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3_CORE1_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3430_CORE2_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
+#define OMAP3630_CORE2_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x25a0)
 (val) +#define OMAP3_WKUP_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2a00)
 (val) +#define AM33XX_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800)

(val)

include/dt-bindings/pinctrl/omap.h line 70

Quoted 6 lines
include/dt-bindings/pinctrl/omap.h +6 -0
+#define OMAP4_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x0040) (val)
+#define OMAP4_WKUP_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0xe040) (val)
+#define AM4372_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define OMAP5_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2840) (val)
+#define OMAP5_WKUP_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0xc840) (val)
+#define DRA7XX_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x3400) (val)

+

Quoted 1 line

#endif

Signature · 3 lines
Regards,

Laurent Pinchart
#4 lore raw

PATCH v2 1/2 ARM: dts: Add omap specific pinctrl defines to use padconf addresses

Quoted 21 lines · Laurent Pinchart

Hi Tony,

Quoted 18 lines · On Tuesday 07 January 2014 14:30:21 Tony Lindgren wrote:

Review

Quoted 13 lines · Laurent Pinchart

From: Tony Lindgren <[email protected]>

include/dt-bindings/pinctrl/omap.h +7 -0
+/*
+ * Macros to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define OMAP_IOPAD_OFFSET(pa, offset)	(((pa) & 0xffff) - (offset))
+
+#define OMAP2420_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x0030)

(val)
+#define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030)
(val)

(quoted diff) +2 -0
+#define OMAP3_CORE1_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3_CORE2_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)

Sorry for the delay on these, I'm only now getting back to looking at all the emails since the holidays :)

Quoted 6 lines
Quoted 2 lines

After looking at Nishant's omap3 pinctrl core2 patch, looks like we need to have separate OMAP3430_CORE2_IOPAD and OMAP3630_CORE2_IOPAD defines.

That was my first impression as well, but I think we actually don't need to. The OMAP3430 just has no useful registers in the 0x25a0 - 0x25d7 area, so we can make the CORE2 macro span that for both 3430 and 3630.

Hmm well I already did it :) In general my gut feeling is along the lines what you're saying, I think the padconf registers are all there on all omap3 SoCs, but only some of the padconf registers are used depending on the SoC revision and package.

Anyways, it should not hurt to have the padconf registers defined the same way as the documentation has them, at least we may get some extra warnings if people try to configure unused registers for 3430.

Regards,

Tony

author
#5 lore raw

PATCH v2 1/2 ARM: dts: Add omap specific pinctrl defines to use padconf addresses

Hi Tony,

Quoted 22 lines · On Tuesday 07 January 2014 15:20:18 Tony Lindgren wrote:
Quoted 21 lines · Laurent Pinchart
Quoted 20 lines · On Tuesday 07 January 2014 14:30:21 Tony Lindgren wrote:
Quoted 8 lines · Laurent Pinchart

From: Tony Lindgren <[email protected]>

include/dt-bindings/pinctrl/omap.h +7 -0
+/*
+ * Macros to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define OMAP_IOPAD_OFFSET(pa, offset)	(((pa) & 0xffff) - (offset))
+
+#define OMAP2420_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x0030)
Quoted 7 lines

(val)
+#define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030)
(val)
+#define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030)
(val)
+#define OMAP3_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0)
(val)

Sorry for the delay on these, I'm only now getting back to looking at all the emails since the holidays :)

Quoted 8 lines
Quoted 6 lines
Quoted 2 lines

After looking at Nishant's omap3 pinctrl core2 patch, looks like we need to have separate OMAP3430_CORE2_IOPAD and OMAP3630_CORE2_IOPAD defines.

That was my first impression as well, but I think we actually don't need to. The OMAP3430 just has no useful registers in the 0x25a0 - 0x25d7 area, so we can make the CORE2 macro span that for both 3430 and 3630.

Hmm well I already did it :)

Haven't you been taught that you should send patches for review before applying them ? ;-)

Quoted 7 lines

In general my gut feeling is along the lines what you're saying, I think the padconf registers are all there on all omap3 SoCs, but only some of the padconf registers are used depending on the SoC revision and package.

Anyways, it should not hurt to have the padconf registers defined the same way as the documentation has them, at least we may get some extra warnings if people try to configure unused registers for 3430.

As long as the bug is fixed in a reasonably clean way I'm fine with that. This seems to count as a reasonably clean way, so no complaint :-)

Signature · 3 lines
Regards,

Laurent Pinchart
#6 lore raw

PATCH v2 1/2 ARM: dts: Add omap specific pinctrl defines to use padconf addresses

Quoted 28 lines · Laurent Pinchart

Hi Tony,

Quoted 25 lines · On Tuesday 07 January 2014 15:20:18 Tony Lindgren wrote:
Quoted 24 lines · Laurent Pinchart
Quoted 22 lines · On Tuesday 07 January 2014 14:30:21 Tony Lindgren wrote:
Quoted 8 lines · Laurent Pinchart

From: Tony Lindgren <[email protected]>

include/dt-bindings/pinctrl/omap.h +7 -0
+/*
+ * Macros to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define OMAP_IOPAD_OFFSET(pa, offset)	(((pa) & 0xffff) - (offset))
+
+#define OMAP2420_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x0030)
Quoted 7 lines

(val)
+#define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030)
(val)
+#define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030)
(val)
+#define OMAP3_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0)
(val)

Sorry for the delay on these, I'm only now getting back to looking at all the emails since the holidays :)

After looking at Nishant's omap3 pinctrl core2 patch, looks like we need to have separate OMAP3430_CORE2_IOPAD and OMAP3630_CORE2_IOPAD defines.

Quoted 8 lines
Quoted 5 lines
Quoted 3 lines

That was my first impression as well, but I think we actually don't need to. The OMAP3430 just has no useful registers in the 0x25a0 - 0x25d7 area, so we can make the CORE2 macro span that for both 3430 and 3630.

Hmm well I already did it :)

Haven't you been taught that you should send patches for review before applying them ? ;-)

Using the "trivial change to an earlier patch" clause here ;)

Quoted 10 lines
Quoted 7 lines

In general my gut feeling is along the lines what you're saying, I think the padconf registers are all there on all omap3 SoCs, but only some of the padconf registers are used depending on the SoC revision and package.

Anyways, it should not hurt to have the padconf registers defined the same way as the documentation has them, at least we may get some extra warnings if people try to configure unused registers for 3430.

As long as the bug is fixed in a reasonably clean way I'm fine with that. This seems to count as a reasonably clean way, so no complaint :-)

Thanks :)

BTW, I'm queueing these for v3.14, hopefully everybody is fine with that as these changes are getting pretty intrusive for v3.13. If people really need these for v3.13, please yell.

Regards,

Tony

#7 lore raw

PATCH v2 1/2 ARM: dts: Add omap specific pinctrl defines to use padconf addresses

In reply to Tony Lindgren

Hi Tony,

Quoted 29 lines · Tony Lindgren
Quoted 21 lines · Laurent Pinchart

Hi Tony,

Quoted 18 lines · On Tuesday 07 January 2014 14:30:21 Tony Lindgren wrote:

Review

Quoted 13 lines · Laurent Pinchart

From: Tony Lindgren <[email protected]>

include/dt-bindings/pinctrl/omap.h +7 -0
+/*
+ * Macros to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define OMAP_IOPAD_OFFSET(pa, offset)	(((pa) & 0xffff) - (offset))
+
+#define OMAP2420_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x0030)

(val)
+#define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030)
(val)

(quoted diff) +2 -0
+#define OMAP3_CORE1_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3_CORE2_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)

Sorry for the delay on these, I'm only now getting back to looking at all the emails since the holidays :)

Quoted 6 lines
Quoted 2 lines

After looking at Nishant's omap3 pinctrl core2 patch, looks like we need to have separate OMAP3430_CORE2_IOPAD and OMAP3630_CORE2_IOPAD defines.

That was my first impression as well, but I think we actually don't need to. The OMAP3430 just has no useful registers in the 0x25a0 - 0x25d7 area, so we can make the CORE2 macro span that for both 3430 and 3630.

Quoted 9 lines

Hmm well I already did it :) In general my gut feeling is along the lines what you're saying, I think the padconf registers are all there on all omap3 SoCs, but only some of the padconf registers are used depending on the SoC revision and package.

Anyways, it should not hurt to have the padconf registers defined the same way as the documentation has them, at least we may get some extra warnings if people try to configure unused registers for 3430.

I can see one downside to this approach; if you update the revision of your processor from omap34xx to omap36xx, and if you are using pins from the overlapping range [0x25d8; 0x25fc], you will have to update all the macros, instead of simply updating the #include statement.

Let me introduce a real-life example. I am using Overo products. The processor board must be stacked onto an expansion board. I currently have only one include file for the processor board (omap3-overo.dtsi). But in reality, Gumstix is currently selling 14 models, with pin-compatible processors (omap35x3, dm3730, am3703) [1].

So I #include omap34xx.dtsi (to be compatible with the omap35x3 models). The range [0x25d8; 0x25fc] defines a number of used features (hsusb2, gpios). To update to newer versions, I have to change the #include, but also all the OMAP3430_CORE2_IOPAD() macros spread across the expansion boards (omap3-tobi + future expansion boards, see my series from today). Even if the newer models do not use the omap36xx-specific features.

Obviously, I currently do not have a straightforward way to support all the models/revisions with one single file. But if a solution is found in the future, it will be far easier if the expansions boards do not depend on the exact processor with such macros.

Regards,

Florian

[1] https://store.gumstix.com/index.php/category/33/

author
#8 lore raw

PATCH v2 2/2 ARM: omap3: Split the pinmux core device

In reply to Laurent Pinchart

The omap3_pmx_core pinmux device in the device tree handles the system controller module (SCM) PADCONFS fonction. Its control registers are split in two distinct areas, with other SCM registers in-between. Those other registers can't thus be requested by other drivers as the memory region gets reserved by the pinmux driver.

Split the omap3_pmx_core device tree node in two for the two memory regions. The second region address and size depends on the SoC model.

The change in omap3.dtsi fixes an "external abort on non-linefetch" when doing

cat /sys/kernel/debug/pinctrl/.../pins

on a Nokia N900.

Signed-off-by Laurent Pinchart <[email protected]>
Acked-by Sebastian Reichel <[email protected]>
---
 arch/arm/boot/dts/omap3-beagle-xm.dts | 40 +++++++++++++++++----------
 arch/arm/boot/dts/omap3-beagle.dts    | 40 +++++++++++++++++----------
 arch/arm/boot/dts/omap3-igep.dtsi     |  2 --
 arch/arm/boot/dts/omap3-igep0020.dts  | 52 +++++++++++++++++++----------------
 arch/arm/boot/dts/omap3-igep0030.dts  | 10 ++++---
 arch/arm/boot/dts/omap3-zoom3.dts     | 23 ++++++++++------
 arch/arm/boot/dts/omap3.dtsi          | 13 ++++++++-
 7 files changed, 114 insertions(+), 66 deletions(-)
arch/arm/boot/dts/omap3-beagle-xm.dts +26 -14
index df33a50..093c33c 100644
@@ -99,7 +99,7 @@
 &omap3_pmx_core {
 	pinctrl-names = "default";
 	pinctrl-0 = <
-			&hsusbb2_pins
+			&hsusb2_pins
 	>;
 
 	uart3_pins: pinmux_uart3_pins {

@@ -109,20 +109,32 @@
 		>;
 	};
 
-	hsusbb2_pins: pinmux_hsusbb2_pins {
+	hsusb2_pins: pinmux_hsusb2_pins {
 		pinctrl-single,pins = <
-			0x5c0 (PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
-			0x5c2 (PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
-			0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
-			0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
-			0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
-			0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
-			0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
-			0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
-			0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
-			0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_somi.hsusb2_data5 */
-			0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs0.hsusb2_data6 */
-			0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs1.hsusb2_data3 */
+			OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
+			OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
+			OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
+			OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_somi.hsusb2_data5 */
+			OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs0.hsusb2_data6 */
+			OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs1.hsusb2_data3 */
+		>;
+	};
+};
+
+&omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&hsusb2_2_pins
+	>;
+
+	hsusb2_2_pins: pinmux_hsusb2_2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
+			OMAP3_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
+			OMAP3_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
+			OMAP3_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
+			OMAP3_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
+			OMAP3_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
 		>;
 	};
 };
arch/arm/boot/dts/omap3-beagle.dts +26 -14
index 3ba4a62..4034fd2 100644
@@ -93,23 +93,17 @@
 &omap3_pmx_core {
 	pinctrl-names = "default";
 	pinctrl-0 = <
-			&hsusbb2_pins
+			&hsusb2_pins
 	>;
 
-	hsusbb2_pins: pinmux_hsusbb2_pins {
+	hsusb2_pins: pinmux_hsusb2_pins {
 		pinctrl-single,pins = <
-			0x5c0 (PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
-			0x5c2 (PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
-			0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
-			0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
-			0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
-			0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
-			0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
-			0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
-			0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
-			0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_somi.hsusb2_data5 */
-			0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs0.hsusb2_data6 */
-			0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs1.hsusb2_data3 */
+			OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
+			OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
+			OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
+			OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_somi.hsusb2_data5 */
+			OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs0.hsusb2_data6 */
+			OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs1.hsusb2_data3 */
 		>;
 	};
 

@@ -121,6 +115,24 @@
 	};
 };
 
+&omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&hsusb2_2_pins
+	>;
+
+	hsusb2_2_pins: pinmux_hsusb2_2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
+			OMAP3_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
+			OMAP3_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
+			OMAP3_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
+			OMAP3_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
+			OMAP3_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
+		>;
+	};
+};
+
 &i2c1 {
 	clock-frequency = <2600000>;
arch/arm/boot/dts/omap3-igep.dtsi +0 -2
index 165aaf7..c1700932 100644
@@ -133,8 +133,6 @@
 			0x194 (PIN_INPUT | MUX_MODE0)   /* i2c3_sda.i2c3_sda */
 		>;
 	};
-
-	leds_pins: pinmux_leds_pins { };
 };
 
 &i2c1 {
arch/arm/boot/dts/omap3-igep0020.dts +29 -23

69 lines not on this page · raw message

arch/arm/boot/dts/omap3-igep0030.dts +6 -4
index 02a23f8..4425ae8 100644
@@ -46,10 +46,12 @@
 	};
 };
 
-&leds_pins {
-	pinctrl-single,pins = <
-		0x5b0 (PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
-	>;
+&omap3_pmx_core2 {
+	leds_pins: pinmux_leds_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
+		>;
+	};
 };
 
 &gpmc {
arch/arm/boot/dts/omap3-zoom3.dts +15 -8
index 15eb9fe..417111c 100644
@@ -80,13 +80,8 @@
 
 	mmc3_pins: pinmux_mmc3_pins {
 		pinctrl-single,pins = <
-			0x168 (PIN_INPUT | MUX_MODE4)	/* mcbsp1_clkx.gpio_162 WLAN IRQ */
-			0x1a0 (PIN_INPUT_PULLUP | MUX_MODE3)	/* mcspi1_cs1.sdmmc3_cmd */
-			0x5a8 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_clk.sdmmc3_clk */
-			0x5b4 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d4.sdmmc3_dat0 */
-			0x5b6 (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
-			0x5b8 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d6.sdmmc3_dat2 */
-			0x5b2 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d3.sdmmc3_dat3 */
+			OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE4)	/* mcbsp1_clkx.gpio_162 WLAN IRQ */
+			OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3)	/* mcspi1_cs1.sdmmc3_cmd */
 		>;
 	};
 

@@ -125,6 +120,18 @@
 	};
 };
 
+&omap3_pmx_core2 {
+	mmc3_2_pins: pinmux_mmc3_2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_clk.sdmmc3_clk */
+			OMAP3_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d4.sdmmc3_dat0 */
+			OMAP3_CORE2_IOPAD(0x25e6, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
+			OMAP3_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d6.sdmmc3_dat2 */
+			OMAP3_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d3.sdmmc3_dat3 */
+		>;
+	};
+};
+
 &omap3_pmx_wkup {
 	wlan_host_wkup: pinmux_wlan_host_wkup_pins {
 		pinctrl-single,pins = <

@@ -187,7 +194,7 @@
 	bus-width = <4>;
 	cap-power-off-card;
 	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins>;
+	pinctrl-0 = <&mmc3_pins &mmc3_2_pins>;
 };
 
 &uart1 {
arch/arm/boot/dts/omap3.dtsi +12 -1
index daabf99..d2bba78 100644
@@ -117,7 +117,18 @@
 
 		omap3_pmx_core: pinmux@48002030 {
 			compatible = "ti,omap3-padconf", "pinctrl-single";
-			reg = <0x48002030 0x05cc>;
+			reg = <0x48002030 0x0238>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			pinctrl-single,register-width = <16>;
+			pinctrl-single,function-mask = <0xff1f>;
+		};
+
+		omap3_pmx_core2: pinmux@480025a0 {
+			compatible = "ti,omap3-padconf", "pinctrl-single";
+			reg = <0x480025a0 0x005c>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			#interrupt-cells = <1>;
Signature · 1 line
1.8.3.2
#9 lore raw

PATCH v2 2/2 ARM: omap3: Split the pinmux core device

Quoted 12 lines · Laurent Pinchart
arch/arm/boot/dts/omap3.dtsi +5 -1
@@ -117,7 +117,18 @@
 
 		omap3_pmx_core: pinmux at 48002030 {
 			compatible = "ti,omap3-padconf", "pinctrl-single";
-			reg = <0x48002030 0x05cc>;
+			reg = <0x48002030 0x0238>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-controller;

arch/arm/boot/dts/omap3.dtsi line 134

Quoted 10 lines
arch/arm/boot/dts/omap3.dtsi +7 -0
+			pinctrl-single,register-width = <16>;
+			pinctrl-single,function-mask = <0xff1f>;
+		};
+
+		omap3_pmx_core2: pinmux at 480025a0 {
+			compatible = "ti,omap3-padconf", "pinctrl-single";
+			reg = <0x480025a0 0x005c>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			#interrupt-cells = <1>;

Looking at Nishant's similar patch, we need to have separate omap3_pmx_core2 for 3430 and 3630. I've updated the patch accordingly with the related parts from Nishant's patch and committed it into omap-for-v3.14/dt branch.

Regards,

Tony

8< ------------------------------
From: Laurent Pinchart <[email protected]>
Date: Tue, 7 Jan 2014 14:01:39 -0800
Subject: [PATCH] ARM: dts: Split omap3 pinmux core device

The omap3_pmx_core pinmux device in the device tree handles the system controller module (SCM) PADCONFS fonction. Its control registers are split in two distinct areas, with other SCM registers in-between. Those other registers can't thus be requested by other drivers as the memory region gets reserved by the pinmux driver.

Split the omap3_pmx_core device tree node in two for the two memory regions. The second region address and size depends on the SoC model.

The change in omap3.dtsi fixes an "external abort on non-linefetch" when doing

cat /sys/kernel/debug/pinctrl/.../pins

on a Nokia N900.

Note that the core2 padconf region is different for 3430 vs 3630, and does not exist on 3517 as noted by Nishanth Menon <[email protected]>.

Reported-by Tomi Valkeinen <[email protected]>
Signed-off-by Laurent Pinchart <[email protected]>
Acked-by Sebastian Reichel <[email protected]>
Signed-off-by Nishanth Menon <[email protected]>
[tony at atomide.com: updated for 3430 vs 3630 core2 based on Nishant's patch]
Signed-off-by Tony Lindgren <[email protected]>
arch/arm/boot/dts/omap3-beagle-xm.dts +26 -14
index df33a50..447e714 100644
@@ -99,7 +99,7 @@
 &omap3_pmx_core {
 	pinctrl-names = "default";
 	pinctrl-0 = <
-			&hsusbb2_pins
+			&hsusb2_pins
 	>;
 
 	uart3_pins: pinmux_uart3_pins {

@@ -109,20 +109,32 @@
 		>;
 	};
 
-	hsusbb2_pins: pinmux_hsusbb2_pins {
+	hsusb2_pins: pinmux_hsusb2_pins {
 		pinctrl-single,pins = <
-			0x5c0 (PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
-			0x5c2 (PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
-			0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
-			0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
-			0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
-			0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
-			0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
-			0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
-			0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
-			0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_somi.hsusb2_data5 */
-			0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs0.hsusb2_data6 */
-			0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs1.hsusb2_data3 */
+			OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
+			OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
+			OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
+			OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_somi.hsusb2_data5 */
+			OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs0.hsusb2_data6 */
+			OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs1.hsusb2_data3 */
+		>;
+	};
+};
+
+&omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&hsusb2_2_pins
+	>;
+
+	hsusb2_2_pins: pinmux_hsusb2_2_pins {
+		pinctrl-single,pins = <
+			OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
+			OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
+			OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
+			OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
+			OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
+			OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
 		>;
 	};
 };
arch/arm/boot/dts/omap3-beagle.dts +26 -14
index 3ba4a62..5053766 100644
@@ -93,23 +93,17 @@
 &omap3_pmx_core {
 	pinctrl-names = "default";
 	pinctrl-0 = <
-			&hsusbb2_pins
+			&hsusb2_pins
 	>;
 
-	hsusbb2_pins: pinmux_hsusbb2_pins {
+	hsusb2_pins: pinmux_hsusb2_pins {
 		pinctrl-single,pins = <
-			0x5c0 (PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
-			0x5c2 (PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
-			0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
-			0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
-			0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
-			0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
-			0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
-			0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
-			0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
-			0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_somi.hsusb2_data5 */
-			0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs0.hsusb2_data6 */
-			0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs1.hsusb2_data3 */
+			OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
+			OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
+			OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
+			OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_somi.hsusb2_data5 */
+			OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs0.hsusb2_data6 */
+			OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs1.hsusb2_data3 */
 		>;
 	};
 

@@ -121,6 +115,24 @@
 	};
 };
 
+&omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <
+			&hsusb2_2_pins
+	>;
+
+	hsusb2_2_pins: pinmux_hsusb2_2_pins {
+		pinctrl-single,pins = <
+			OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)		/* etk_d10.hsusb2_clk */
+			OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)		/* etk_d11.hsusb2_stp */
+			OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
+			OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
+			OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
+			OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
+		>;
+	};
+};
+
 &i2c1 {
 	clock-frequency = <2600000>;
arch/arm/boot/dts/omap3-igep.dtsi +0 -2
index 165aaf7..c1700932 100644
@@ -133,8 +133,6 @@
 			0x194 (PIN_INPUT | MUX_MODE0)   /* i2c3_sda.i2c3_sda */
 		>;
 	};
-
-	leds_pins: pinmux_leds_pins { };
 };
 
 &i2c1 {
arch/arm/boot/dts/omap3-igep0020.dts +29 -23

69 lines not on this page · raw message

arch/arm/boot/dts/omap3-igep0030.dts +6 -4
index 02a23f8..145c58c 100644
@@ -46,10 +46,12 @@
 	};
 };
 
-&leds_pins {
-	pinctrl-single,pins = <
-		0x5b0 (PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
-	>;
+&omap3_pmx_core2 {
+	leds_pins: pinmux_leds_pins {
+		pinctrl-single,pins = <
+			OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
+		>;
+	};
 };
 
 &gpmc {
arch/arm/boot/dts/omap3-zoom3.dts +15 -8
index 15eb9fe..6644f51 100644
@@ -80,13 +80,8 @@
 
 	mmc3_pins: pinmux_mmc3_pins {
 		pinctrl-single,pins = <
-			0x168 (PIN_INPUT | MUX_MODE4)	/* mcbsp1_clkx.gpio_162 WLAN IRQ */
-			0x1a0 (PIN_INPUT_PULLUP | MUX_MODE3)	/* mcspi1_cs1.sdmmc3_cmd */
-			0x5a8 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_clk.sdmmc3_clk */
-			0x5b4 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d4.sdmmc3_dat0 */
-			0x5b6 (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
-			0x5b8 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d6.sdmmc3_dat2 */
-			0x5b2 (PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d3.sdmmc3_dat3 */
+			OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE4)	/* mcbsp1_clkx.gpio_162 WLAN IRQ */
+			OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3)	/* mcspi1_cs1.sdmmc3_cmd */
 		>;
 	};
 

@@ -125,6 +120,18 @@
 	};
 };
 
+&omap3_pmx_core2 {
+	mmc3_2_pins: pinmux_mmc3_2_pins {
+		pinctrl-single,pins = <
+			OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_clk.sdmmc3_clk */
+			OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d4.sdmmc3_dat0 */
+			OMAP3630_CORE2_IOPAD(0x25e6, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
+			OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d6.sdmmc3_dat2 */
+			OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d3.sdmmc3_dat3 */
+		>;
+	};
+};
+
 &omap3_pmx_wkup {
 	wlan_host_wkup: pinmux_wlan_host_wkup_pins {
 		pinctrl-single,pins = <

@@ -187,7 +194,7 @@
 	bus-width = <4>;
 	cap-power-off-card;
 	pinctrl-names = "default";
-	pinctrl-0 = <&mmc3_pins>;
+	pinctrl-0 = <&mmc3_pins &mmc3_2_pins>;
 };
 
 &uart1 {
arch/arm/boot/dts/omap3.dtsi +1 -1
index daabf99..427395c 100644
@@ -117,7 +117,7 @@
 
 		omap3_pmx_core: pinmux at 48002030 {
 			compatible = "ti,omap3-padconf", "pinctrl-single";
-			reg = <0x48002030 0x05cc>;
+			reg = <0x48002030 0x0238>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			#interrupt-cells = <1>;
arch/arm/boot/dts/omap34xx.dtsi +13 -0
index 5355d61..77d1246 100644
@@ -25,4 +25,17 @@
 			clock-latency = <300000>; /* From legacy driver */
 		};
 	};
+
+	ocp {
+		omap3_pmx_core2: pinmux at 480025d8 {
+			compatible = "ti,omap3-padconf", "pinctrl-single";
+			reg = <0x480025d8 0x24>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			pinctrl-single,register-width = <16>;
+			pinctrl-single,function-mask = <0xff1f>;
+		};
+	};
 };
arch/arm/boot/dts/omap36xx.dtsi +11 -0
index 380c22e..b7c7bd9 100644
@@ -38,5 +38,16 @@
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
 		};
+
+		omap3_pmx_core2: pinmux at 480025a0 {
+			compatible = "ti,omap3-padconf", "pinctrl-single";
+			reg = <0x480025a0 0x5c>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			pinctrl-single,register-width = <16>;
+			pinctrl-single,function-mask = <0xff1f>;
+		};
 	};
 };