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Add usb ethernet support for Arndale

PATCH New Inderpal Singh 2 participants 4 messages Jan 8, 2014 – Jan 13, 2014

Subsystems (4)
Arm (32-bit) USB Arm Samsung Exynos USB ehci driver
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Inderpal Singh

author
#0 lore raw

v3 cover Add usb ethernet support for Arndale

Arndale board has AX88760, which is USB 2.0 Hub & USB 2.0 Ethernet Combo controller, connected to HSIC Phy of USB host controller via USB3503 hub.

This patchset adds support for this usb ethernet controllor.

Changes in v2:
- removed setting preboot environment in patch 2
Changes in v3:
- used generic board_usb_init

Inderpal Singh (2):
usb: ehci: exynos: set/reset hsic phys
usb: exynos5: arndale: Add network support

 arch/arm/include/asm/arch-exynos/ehci.h |   14 +++++++++++
 board/samsung/arndale/arndale.c         |   21 ++++++++++++++++
 drivers/usb/host/ehci-exynos.c          |   41 +++++++++++++++++++++++++++++++
 include/configs/arndale.h               |    4 +++
 4 files changed, 80 insertions(+)
Signature · 1 line
1.7.9.5
author
#1 lore raw

PATCH v3 1/2 usb: ehci: exynos: set/reset hsic phys

From: Inderpal Singh <[email protected]>

The controller has 3 ports. The port0 is for USB 2.0 Phy, port1 and port2 are for HSIC phys. The usb 2.0 phy is already being setup. This patch sets up the hsic phys.

Signed-off-by Inderpal Singh <[email protected]>
---
 arch/arm/include/asm/arch-exynos/ehci.h |   14 +++++++++++
 drivers/usb/host/ehci-exynos.c          |   39 +++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+)
arch/arm/include/asm/arch-exynos/ehci.h +14 -0
index d79f25c..d2d70bd 100644
@@ -29,6 +29,20 @@
 #define EHCICTRL_ENAINCR8			(1 << 27)
 #define EHCICTRL_ENAINCR16			(1 << 26)
 
+#define HSIC_CTRL_REFCLKSEL                     (0x2)
+#define HSIC_CTRL_REFCLKSEL_MASK                (0x3)
+#define HSIC_CTRL_REFCLKSEL_SHIFT               (23)
+
+#define HSIC_CTRL_REFCLKDIV_12                  (0x24)
+#define HSIC_CTRL_REFCLKDIV_MASK                (0x7f)
+#define HSIC_CTRL_REFCLKDIV_SHIFT               (16)
+
+#define HSIC_CTRL_SIDDQ                         (0x1 << 6)
+#define HSIC_CTRL_FORCESLEEP                    (0x1 << 5)
+#define HSIC_CTRL_FORCESUSPEND                  (0x1 << 4)
+#define HSIC_CTRL_UTMISWRST                     (0x1 << 2)
+#define HSIC_CTRL_PHYSWRST                      (0x1 << 0)
+
 /* Register map for PHY control */
 struct exynos_usb_phy {
 	unsigned int usbphyctrl0;
drivers/usb/host/ehci-exynos.c +39 -0
index 66b4de0..88e6466 100644
@@ -88,6 +88,8 @@ static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
 /* Setup the EHCI host controller. */
 static void setup_usb_phy(struct exynos_usb_phy *usb)
 {
+	u32 hsic_ctrl;
+
 	set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
 
 	set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);

@@ -112,6 +114,32 @@ static void setup_usb_phy(struct exynos_usb_phy *usb)
 	clrbits_le32(&usb->usbphyctrl0,
 			HOST_CTRL0_LINKSWRST |
 			HOST_CTRL0_UTMISWRST);
+
+	/* HSIC Phy Setting */
+	hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
+			HSIC_CTRL_FORCESLEEP |
+			HSIC_CTRL_SIDDQ);
+
+	clrbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
+	clrbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
+
+	hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK)
+				<< HSIC_CTRL_REFCLKDIV_SHIFT)
+			| ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK)
+				<< HSIC_CTRL_REFCLKSEL_SHIFT)
+			| HSIC_CTRL_UTMISWRST);
+
+	setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
+	setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
+
+	udelay(10);
+
+	clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST |
+					HSIC_CTRL_UTMISWRST);
+
+	clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST |
+					HSIC_CTRL_UTMISWRST);
+
 	udelay(20);
 
 	/* EHCI Ctrl setting */

@@ -125,6 +153,8 @@ static void setup_usb_phy(struct exynos_usb_phy *usb)
 /* Reset the EHCI host controller. */
 static void reset_usb_phy(struct exynos_usb_phy *usb)
 {
+	u32 hsic_ctrl;
+
 	/* HOST_PHY reset */
 	setbits_le32(&usb->usbphyctrl0,
 			HOST_CTRL0_PHYSWRST |

@@ -133,6 +163,15 @@ static void reset_usb_phy(struct exynos_usb_phy *usb)
 			HOST_CTRL0_FORCESUSPEND |
 			HOST_CTRL0_FORCESLEEP);
 
+	/* HSIC Phy reset */
+	hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
+			HSIC_CTRL_FORCESLEEP |
+			HSIC_CTRL_SIDDQ |
+			HSIC_CTRL_PHYSWRST);
+
+	setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
+	setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
+
 	set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
 }
Signature · 1 line
1.7.9.5
author
#2 lore raw

PATCH v3 2/2 usb: exynos5: arndale: Add network support

In reply to Inderpal Singh

Arndale board has AX88760, which is USB 2.0 Hub & USB 2.0 Ethernet Combo controller, connected to HSIC Phy of USB host controller via USB3503 hub.

This patch uses board specific board_usb_init function to perform reset sequence for USB3503 hub and enables the relevant config options for network to work.

Signed-off-by Inderpal Singh <[email protected]>
Signed-off-by Chander Kashyap <[email protected]>
---
 board/samsung/arndale/arndale.c |   21 +++++++++++++++++++++
 drivers/usb/host/ehci-exynos.c  |    2 ++
 include/configs/arndale.h       |    4 ++++
 3 files changed, 27 insertions(+)
board/samsung/arndale/arndale.c +21 -0
index 052fecd..9efc355 100644
@@ -5,12 +5,33 @@
  */
 
 #include <common.h>
+#include <usb.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/dwmmc.h>
+#include <asm/arch/gpio.h>
 #include <asm/arch/power.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_USB_EHCI_EXYNOS
+int board_usb_init(int index, enum usb_init_type init)
+{
+	struct exynos5_gpio_part1 *gpio = (struct exynos5_gpio_part1 *)
+						samsung_get_base_gpio_part1();
+
+	/* Configure gpios for usb 3503 hub:
+	 * disconnect, toggle reset and connect
+	 */
+	s5p_gpio_direction_output(&gpio->d1, 7, 0);
+	s5p_gpio_direction_output(&gpio->x3, 5, 0);
+
+	s5p_gpio_direction_output(&gpio->x3, 5, 1);
+	s5p_gpio_direction_output(&gpio->d1, 7, 1);
+
+	return 0;
+}
+#endif
+
 int board_init(void)
 {
 	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
drivers/usb/host/ehci-exynos.c +2 -0
index 88e6466..9356878 100644
@@ -203,6 +203,8 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 
 	setup_usb_phy(ctx->usb);
 
+	board_usb_init(index, init);
+
 	*hccr = ctx->hcd;
 	*hcor = (struct ehci_hcor *)((uint32_t) *hccr
 				+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
include/configs/arndale.h +4 -0
index b7fb29e..eda0e4f 100644
@@ -116,6 +116,10 @@
 #define CONFIG_USB_EHCI_EXYNOS
 #define CONFIG_USB_STORAGE
 
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
 /* MMC SPL */
 #define CONFIG_EXYNOS_SPL
 #define CONFIG_SPL
Signature · 1 line
1.7.9.5
Applied
#3 lore raw

v3 cover Add usb ethernet support for Arndale

In reply to Inderpal Singh
Quoted 14 lines · Inderpal Singh

Arndale board has AX88760, which is USB 2.0 Hub & USB 2.0 Ethernet Combo controller, connected to HSIC Phy of USB host controller via USB3503 hub.

This patchset adds support for this usb ethernet controllor.

Changes in v2:
- removed setting preboot environment in patch 2
Changes in v3:
- used generic board_usb_init

Inderpal Singh (2):
usb: ehci: exynos: set/reset hsic phys
usb: exynos5: arndale: Add network support

Quoted 6 lines
 arch/arm/include/asm/arch-exynos/ehci.h |   14 +++++++++++
 board/samsung/arndale/arndale.c         |   21 ++++++++++++++++
 drivers/usb/host/ehci-exynos.c          |   41
+++++++++++++++++++++++++++++++ include/configs/arndale.h               | 
  4 +++
 4 files changed, 80 insertions(+)

Applied both, thanks.

Best regards,
Marek Vasut