ARM: sunxi: rename DT clock node names to clk@N
Subsystems (4)
v3 cover ARM: sunxi: rename DT clock node names to clk@N
This is v3 of the clock node renaming patch series, which renames the clock nodes in sunxi dts to conform to device tree naming conventions, i.e. clk at N. Dummy clocks that will be renamed/removed later, or clocks sharing registers are not renamed.
Renamed clock nodes have clock-output-names properties added to desginate their names. Support for this is added in the first patch.
Changes since v2:
* Dropped Cubietruck dts i2c controller patch. Maxime has taken it.
* Changed ARM in commit messages to uppercase.
* Add pll5, pll6 clock names to factors_data tied to compatible strings.
* Dropped pll5 output name in dts due to the previous change.
* Added dts binding documentation for "clock-output-names", as well as examples.
Changes since v1:
* Fixed pll5, pll6 divs clock name handling
Cheers
ChenYu
Chen-Yu Tsai (8):
clk: sunxi: add clock-output-names dt property support
clk: sunxi: update clock-output-names dt binding documentation
clk: sunxi: add names for pll5, pll6 parent clocks to factors_data
clk: sunxi: get divs parent clock name from parent factor clock
ARM: dts: sun4i: rename clock node names to clk at N
ARM: dts: sun5i: rename clock node names to clk at N
ARM: dts: sun6i: rename clock node names to clk at N
ARM: dts: sun7i: rename clock node names to clk at N
Documentation/devicetree/bindings/clock/sunxi.txt | 36 +++++++++++++++++++---- arch/arm/boot/dts/sun4i-a10.dtsi | 24 ++++++++------- arch/arm/boot/dts/sun5i-a10s.dtsi | 24 ++++++++------- arch/arm/boot/dts/sun5i-a13.dtsi | 24 ++++++++------- arch/arm/boot/dts/sun6i-a31.dtsi | 12 ++++---- arch/arm/boot/dts/sun7i-a20.dtsi | 19 +++++++----- drivers/clk/sunxi/clk-sunxi.c | 36 ++++++++++++++++------- 7 files changed, 117 insertions(+), 58 deletions(-)
Signature · 1 line
1.8.5.2
PATCH v3 1/8 clk: sunxi: add clock-output-names dt property support
sunxi clock drivers use dt node name as clock name, but clock nodes should be named clk at X, so the names would be the same. Let the drivers read clock names from dt clock-output-names property.
--- drivers/clk/sunxi/clk-sunxi.c | 6 ++++++ 1 file changed, 6 insertions(+)
drivers/clk/sunxi/clk-sunxi.c +6 -0
@@ -53,6 +53,8 @@ static void __init sun4i_osc_clk_setup(struct device_node *node)if (of_property_read_u32 (node,"clock-frequency" , &rate))return ; +of_property_read_string (node,"clock-output-names" , &clk_name); +/* set up gate and fixed rate properties */ gate->reg =of_iomap (node,0 ); gate->bit_idx =SUNXI_OSC24M_GATE ;
@@ -595,6 +597,8 @@ static void __init sunxi_mux_clk_setup(struct device_node *node, (parents[i] = of_clk_get_parent_name(node, i)) != NULL) i++; +of_property_read_string (node,"clock-output-names" , &clk_name); + clk = clk_register_mux(NULL, clk_name, parents, i, CLK_SET_RATE_NO_REPARENT, reg, data->shift, SUNXI_MUX_GATE_WIDTH,
@@ -654,6 +658,8 @@ static void __init sunxi_divider_clk_setup(struct device_node *node, clk_parent =of_clk_get_parent_name (node,0 ); +of_property_read_string (node,"clock-output-names" , &clk_name); + clk = clk_register_divider(NULL, clk_name, clk_parent, 0, reg, data->shift, data->width, data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
Signature · 1 line
1.8.5.2
PATCH v3 1/8 clk: sunxi: add clock-output-names dt property support
Quoted 6 lines · Chen-Yu Tsai
sunxi clock drivers use dt node name as clock name, but clock nodes should be named clk at X, so the names would be the same. Let the drivers read clock names from dt clock-output-names property.
Signed-off-by Chen-Yu Tsai <[email protected]>
Thanks!
Maxime
Signature · 10 lines
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PATCH v3 2/8 clk: sunxi: update clock-output-names dt binding documentation
In reply to Chen-Yu Tsaiclock-output-names is now required for most of sunxi clock nodes, to provide the name of the corresponding clock. Add the new requirements, exceptions, as well as examples.
--- Documentation/devicetree/bindings/clock/sunxi.txt | 36 +++++++++++++++++++---- 1 file changed, 31 insertions(+), 5 deletions(-)
Documentation/devicetree/bindings/clock/sunxi.txt +31 -5
@@ -44,10 +44,18 @@ Required properties for all clocks: multiplexed clocks, the list order must match the hardware programming order. - #clock-cells : from common clock binding; shall be set to 0 except for - "allwinner,*-gates-clk" where it shall be set to 1 + "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and + "allwinner,sun4i-pll6-clk" where it shall be set to 1 -Additionally, "allwinner,*-gates-clk" clocks require: -- clock-output-names : the corresponding gate names that the clock controls +Additionally, most clocks require "clock-output-names": +- "allwinner,*-gates-clk" : the corresponding gate names that the clock controls +- "allwinner,sun4i-pll5-clk" : "pll5_ddr", "pll5_mbus" +- "allwinner,sun4i-pll6-clk" : "pll6_sata", "pll6_other" +- "allwinner,sun4i-cpu-clk", "allwinner,sun4i-axi-clk", + "allwinner,sun4i-ahb-clk", "allwinner,sun4i-ahb-clk", + "allwinner,sun4i-apb1-mux-clk", "allwinner,sun4i-apb1-clk" + do not need "clock-output-names" +- all others clocks : the corresponding module name of that clock Clock consumers should specify the desired clocks they use with a "clocks" phandle cell. Consumers that are using a gated clock should
@@ -56,18 +64,28 @@ offset of the bit controlling this particular gate in the register. For example: -osc24M: osc24M at 01c20050 { +osc24M: clk at 01c20050 { #clock-cells = <0>; compatible = "allwinner,sun4i-osc-clk"; reg = <0x01c20050 0x4>; clocks = <&osc24M_fixed>; + clock-output-names = "osc24M"; }; -pll1: pll1 at 01c20000 { +pll1: clk at 01c20000 { #clock-cells = <0>; compatible = "allwinner,sun4i-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; + clock-output-names = "pll1"; +}; + +pll5: clk at 01c20020 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll5-clk"; + reg = <0x01c20020 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll5_ddr", "pll5_other"; }; cpu: cpu at 01c20054 {
@@ -76,3 +94,11 @@ cpu: cpu at 01c20054 { reg = <0x01c20054 0x4>; clocks = <&osc32k>, <&osc24M>, <&pll1>; }; + +mmc0_clk: clk at 01c20088 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc0"; +};
Signature · 1 line
1.8.5.2
PATCH v3 2/8 clk: sunxi: update clock-output-names dt binding documentation
Quoted 5 lines · Chen-Yu Tsai
clock-output-names is now required for most of sunxi clock nodes, to provide the name of the corresponding clock. Add the new requirements, exceptions, as well as examples.
Signed-off-by Chen-Yu Tsai <[email protected]>
Thanks!
Maxime
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140115/815be5d1/attachment.sig>
Emilio López
maintainerPATCH v3 2/8 clk: sunxi: update clock-output-names dt binding documentation
In reply to Chen-Yu TsaiHi,
El 09/01/14 05:52, Chen-Yu Tsai escribi?:
Quoted 22 lines
clock-output-names is now required for most of sunxi clock nodes, to provide the name of the corresponding clock. Add the new requirements, exceptions, as well as examples.
Signed-off-by Chen-Yu Tsai <[email protected]>--- Documentation/devicetree/bindings/clock/sunxi.txt | 36 +++++++++++++++++++---- 1 file changed, 31 insertions(+), 5 deletions(-)Documentation/devicetree/bindings/clock/sunxi.txt +2
-2@@ -44,10 +44,18 @@ Required properties for all clocks: multiplexed clocks, the list order must match the hardware programming order. - #clock-cells : from common clock binding; shall be set to 0 except for - "allwinner,*-gates-clk" where it shall be set to 1 + "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and + "allwinner,sun4i-pll6-clk" where it shall be set to 1 -Additionally, "allwinner,*-gates-clk" clocks require:
Documentation/devicetree/bindings/clock/sunxi.txt Required properties for all clocks: · line 58
Quoted 10 lines
Documentation/devicetree/bindings/clock/sunxi.txt +9
-1-- clock-output-names : the corresponding gate names that the clock controls +Additionally, most clocks require "clock-output-names": +- "allwinner,*-gates-clk" : the corresponding gate names that the clock controls +- "allwinner,sun4i-pll5-clk" : "pll5_ddr", "pll5_mbus" +- "allwinner,sun4i-pll6-clk" : "pll6_sata", "pll6_other" +- "allwinner,sun4i-cpu-clk", "allwinner,sun4i-axi-clk", + "allwinner,sun4i-ahb-clk", "allwinner,sun4i-ahb-clk", + "allwinner,sun4i-apb1-mux-clk", "allwinner,sun4i-apb1-clk" + do not need "clock-output-names" +- all others clocks : the corresponding module name of that clock
As we discussed on IRC, I wonder if such verbosity is actually needed. Maybe we should dictate that all clocks must list their corresponding outputs on clock-output-names (with it being the module name if it only has one output).
Cheers,
Emilio
PATCH v3 2/8 clk: sunxi: update clock-output-names dt binding documentation
Hi Maxime,
Quoted 38 lines · Emilio L?pez
Hi,
El 09/01/14 05:52, Chen-Yu Tsai escribi?:
Quoted 34 lines
clock-output-names is now required for most of sunxi clock nodes, to provide the name of the corresponding clock. Add the new requirements, exceptions, as well as examples.
Signed-off-by Chen-Yu Tsai <[email protected]>--- Documentation/devicetree/bindings/clock/sunxi.txt | 36 +++++++++++++++++++---- 1 file changed, 31 insertions(+), 5 deletions(-)Documentation/devicetree/bindings/clock/sunxi.txt +2
-3@@ -44,10 +44,18 @@ Required properties for all clocks: multiplexed clocks, the list order must match the hardware programming order. - #clock-cells : from common clock binding; shall be set to 0 except for - "allwinner,*-gates-clk" where it shall be set to 1 + "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and + "allwinner,sun4i-pll6-clk" where it shall be set to 1 -Additionally, "allwinner,*-gates-clk" clocks require: -- clock-output-names : the corresponding gate names that the clockcontrols
+Additionally, most clocks require "clock-output-names":
+- "allwinner,*-gates-clk" : the corresponding gate names that the clock controls+- "allwinner,sun4i-pll5-clk" : "pll5_ddr", "pll5_mbus" +- "allwinner,sun4i-pll6-clk" : "pll6_sata", "pll6_other" +- "allwinner,sun4i-cpu-clk", "allwinner,sun4i-axi-clk",Documentation/devicetree/bindings/clock/sunxi.txt +2
-0+ "allwinner,sun4i-ahb-clk", "allwinner,sun4i-ahb-clk", + "allwinner,sun4i-apb1-mux-clk", "allwinner,sun4i-apb1-clk"
Quoted 8 lines
Quoted 2 lines
+ do not need "clock-output-names"
+- all others clocks : the corresponding module name of that clockAs we discussed on IRC, I wonder if such verbosity is actually needed. Maybe we should dictate that all clocks must list their corresponding outputs on clock-output-names (with it being the module name if it only has one output).
Maxime, could we get your input on this?
Thanks
ChenYu
PATCH v3 2/8 clk: sunxi: update clock-output-names dt binding documentation
Hi Chen-Yu,
Quoted 50 lines · Chen-Yu Tsai
Hi Maxime,
Quoted 38 lines · Emilio L?pez
Hi,
El 09/01/14 05:52, Chen-Yu Tsai escribi?:
Quoted 34 lines
clock-output-names is now required for most of sunxi clock nodes, to provide the name of the corresponding clock. Add the new requirements, exceptions, as well as examples.
Signed-off-by Chen-Yu Tsai <[email protected]>--- Documentation/devicetree/bindings/clock/sunxi.txt | 36 +++++++++++++++++++---- 1 file changed, 31 insertions(+), 5 deletions(-)Documentation/devicetree/bindings/clock/sunxi.txt +2
-3@@ -44,10 +44,18 @@ Required properties for all clocks: multiplexed clocks, the list order must match the hardware programming order. - #clock-cells : from common clock binding; shall be set to 0 except for - "allwinner,*-gates-clk" where it shall be set to 1 + "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and + "allwinner,sun4i-pll6-clk" where it shall be set to 1 -Additionally, "allwinner,*-gates-clk" clocks require: -- clock-output-names : the corresponding gate names that the clockcontrols
+Additionally, most clocks require "clock-output-names":
+- "allwinner,*-gates-clk" : the corresponding gate names that the clock controls+- "allwinner,sun4i-pll5-clk" : "pll5_ddr", "pll5_mbus" +- "allwinner,sun4i-pll6-clk" : "pll6_sata", "pll6_other" +- "allwinner,sun4i-cpu-clk", "allwinner,sun4i-axi-clk",Documentation/devicetree/bindings/clock/sunxi.txt +2
-0+ "allwinner,sun4i-ahb-clk", "allwinner,sun4i-ahb-clk", + "allwinner,sun4i-apb1-mux-clk", "allwinner,sun4i-apb1-clk"Quoted 8 lines
Quoted 2 lines
+ do not need "clock-output-names"
+- all others clocks : the corresponding module name of that clockAs we discussed on IRC, I wonder if such verbosity is actually needed. Maybe we should dictate that all clocks must list their corresponding outputs on clock-output-names (with it being the module name if it only has one output).
Quoted 1 line
Maxime, could we get your input on this?
I didn't get it was a question for me. But I'm fine with both. If making clock-output-names mandatory makes our life easier, let's do it.
Maxime
Signature · 10 lines
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PATCH v3 3/8 clk: sunxi: add names for pll5, pll6 parent clocks to factors_data
In reply to Chen-Yu TsaiSome factor clocks, such as the parent clock of pll5 and pll6, have multiple output names. Add the corresponding names to factors_data tied to compatible string.
--- drivers/clk/sunxi/clk-sunxi.c | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-)
drivers/clk/sunxi/clk-sunxi.c +18 -9
@@ -383,6 +383,7 @@ struct factors_data {int mux;struct clk_factors_config *table;void (*getter) (u32 *rate,u32 parent_rate,u8 *n,u8 *k,u8 *m,u8 *p); +const char *name; };static struct clk_factors_config sun4i_pll1_config = {
@@ -451,6 +452,14 @@ static const struct factors_data sun4i_pll5_data __initconst = { .enable = 31, .table = &sun4i_pll5_config, .getter = sun4i_get_pll5_factors, + .name = "pll5", +}; + +static const struct factors_data sun4i_pll6_data__initconst = { + .enable =31 , + .table = &sun4i_pll5_config, + .getter = sun4i_get_pll5_factors, + .name ="pll6" , };static const struct factors_data sun4i_apb1_data__initconst = {
@@ -493,14 +502,14 @@ static struct clk * __init sunxi_factors_clk_setup(struct device_node *node, (parents[i] = of_clk_get_parent_name(node, i)) != NULL) i++; -/* Nodes should be providing the name via clock-output-names -* but originally our dts didn't, and so we used node->name. -* The new, better nodes look like clk at deadbeef, so we pull the -* name just in this case */ -if (!strcmp ("clk" , clk_name)) { -of_property_read_string_index (node,"clock-output-names" , -0 , &clk_name); - } +/* +* some factor clocks, such as pll5 and pll6, may have multiple +* outputs, and have their name designated in factors_data +*/ +if (data->name) + clk_name = data->name; +else +of_property_read_string (node,"clock-output-names" , &clk_name); factors =kzalloc (sizeof (struct clk_factors ),GFP_KERNEL );if (!factors)
@@ -832,7 +841,7 @@ static const struct divs_data pll5_divs_data __initconst = { };static const struct divs_data pll6_divs_data__initconst = { - .factors = &sun4i_pll5_data, + .factors = &sun4i_pll6_data, .div = { { .shift =0 , .table = pll6_sata_tbl, .gate =14 },/* M, SATA */ { .fixed =2 },/* P, other */
Signature · 1 line
1.8.5.2
PATCH v3 3/8 clk: sunxi: add names for pll5, pll6 parent clocks to factors_data
Hi,
Quoted 5 lines · Chen-Yu Tsai
Some factor clocks, such as the parent clock of pll5 and pll6, have multiple output names. Add the corresponding names to
factors_datatied to compatible string.Signed-off-by Chen-Yu Tsai <[email protected]>
Thanks!
Maxime
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140115/086d0cfd/attachment.sig>
PATCH v3 4/8 clk: sunxi: get divs parent clock name from parent factor clock
In reply to Chen-Yu TsaiDivs clocks consist of a parent factor clock with multiple outputs, and seperate clocks for each output. Get the name of the parent clock from the parent factor clock, instead of the DT node name.
--- drivers/clk/sunxi/clk-sunxi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/clk/sunxi/clk-sunxi.c +2 -1
@@ -863,7 +863,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, struct divs_data *data) {struct clk_onecell_data *clk_data; -const char *parent = node->name; +const char *parent;const char *clk_name;struct clk **clks, *pclk;struct clk_hw *gate_hw, *rate_hw;
@@ -877,6 +877,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,/* Set up factor clock that we will be dividing */ pclk =sunxi_factors_clk_setup (node, data->factors); + parent =__clk_get_name (pclk); reg =of_iomap (node,0 );
Signature · 1 line
1.8.5.2
PATCH v3 5/8 ARM: dts: sun4i: rename clock node names to clk@N
In reply to Chen-Yu TsaiDevice tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match.
Also add the output name for pll5 to use as the clock name.
--- arch/arm/boot/dts/sun4i-a10.dtsi | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-)
arch/arm/boot/dts/sun4i-a10.dtsi +14 -10
@@ -50,34 +50,38 @@ clock-frequency = <0>; }; - osc24M: osc24M at 01c20050 { + osc24M: clk at 01c20050 { #clock-cells = <0>; compatible = "allwinner,sun4i-osc-clk"; reg = <0x01c20050 0x4>; clock-frequency = <24000000>; + clock-output-names = "osc24M"; }; - osc32k: osc32k { + osc32k: clk at 0 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; + clock-output-names = "osc32k"; }; - pll1: pll1 at 01c20000 { + pll1: clk at 01c20000 { #clock-cells = <0>; compatible = "allwinner,sun4i-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; + clock-output-names = "pll1"; }; - pll4: pll4 at 01c20018 { + pll4: clk at 01c20018 { #clock-cells = <0>; compatible = "allwinner,sun4i-pll1-clk"; reg = <0x01c20018 0x4>; clocks = <&osc24M>; + clock-output-names = "pll4"; }; - pll5: pll5 at 01c20020 { + pll5: clk at 01c20020 { #clock-cells = <1>; compatible = "allwinner,sun4i-pll5-clk"; reg = <0x01c20020 0x4>;
@@ -85,7 +89,7 @@ clock-output-names = "pll5_ddr", "pll5_other"; }; - pll6: pll6 at 01c20028 { + pll6: clk at 01c20028 { #clock-cells = <1>; compatible = "allwinner,sun4i-pll6-clk"; reg = <0x01c20028 0x4>;
@@ -108,7 +112,7 @@ clocks = <&cpu>; }; - axi_gates: axi_gates at 01c2005c { + axi_gates: clk at 01c2005c { #clock-cells = <1>; compatible = "allwinner,sun4i-axi-gates-clk"; reg = <0x01c2005c 0x4>;
@@ -123,7 +127,7 @@ clocks = <&axi>; }; - ahb_gates: ahb_gates at 01c20060 { + ahb_gates: clk at 01c20060 { #clock-cells = <1>; compatible = "allwinner,sun4i-ahb-gates-clk"; reg = <0x01c20060 0x8>;
@@ -148,7 +152,7 @@ clocks = <&ahb>; }; - apb0_gates: apb0_gates at 01c20068 { + apb0_gates: clk at 01c20068 { #clock-cells = <1>; compatible = "allwinner,sun4i-apb0-gates-clk"; reg = <0x01c20068 0x4>;
@@ -172,7 +176,7 @@ clocks = <&apb1_mux>; }; - apb1_gates: apb1_gates at 01c2006c { + apb1_gates: clk at 01c2006c { #clock-cells = <1>; compatible = "allwinner,sun4i-apb1-gates-clk"; reg = <0x01c2006c 0x4>;
Signature · 1 line
1.8.5.2
PATCH v3 6/8 ARM: dts: sun5i: rename clock node names to clk@N
In reply to Chen-Yu TsaiDevice tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match.
Also add the output name for pll5 to use as the clock name.
--- arch/arm/boot/dts/sun5i-a10s.dtsi | 24 ++++++++++++++---------- arch/arm/boot/dts/sun5i-a13.dtsi | 24 ++++++++++++++---------- 2 files changed, 28 insertions(+), 20 deletions(-)
arch/arm/boot/dts/sun5i-a10s.dtsi +14 -10
@@ -47,34 +47,38 @@ clock-frequency = <0>; }; - osc24M: osc24M at 01c20050 { + osc24M: clk at 01c20050 { #clock-cells = <0>; compatible = "allwinner,sun4i-osc-clk"; reg = <0x01c20050 0x4>; clock-frequency = <24000000>; + clock-output-names = "osc24M"; }; - osc32k: osc32k { + osc32k: clk at 0 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; + clock-output-names = "osc32k"; }; - pll1: pll1 at 01c20000 { + pll1: clk at 01c20000 { #clock-cells = <0>; compatible = "allwinner,sun4i-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; + clock-output-names = "pll1"; }; - pll4: pll4 at 01c20018 { + pll4: clk at 01c20018 { #clock-cells = <0>; compatible = "allwinner,sun4i-pll1-clk"; reg = <0x01c20018 0x4>; clocks = <&osc24M>; + clock-output-names = "pll4"; }; - pll5: pll5 at 01c20020 { + pll5: clk at 01c20020 { #clock-cells = <1>; compatible = "allwinner,sun4i-pll5-clk"; reg = <0x01c20020 0x4>;
@@ -82,7 +86,7 @@ clock-output-names = "pll5_ddr", "pll5_other"; }; - pll6: pll6 at 01c20028 { + pll6: clk at 01c20028 { #clock-cells = <1>; compatible = "allwinner,sun4i-pll6-clk"; reg = <0x01c20028 0x4>;
@@ -105,7 +109,7 @@ clocks = <&cpu>; }; - axi_gates: axi_gates at 01c2005c { + axi_gates: clk at 01c2005c { #clock-cells = <1>; compatible = "allwinner,sun4i-axi-gates-clk"; reg = <0x01c2005c 0x4>;
@@ -120,7 +124,7 @@ clocks = <&axi>; }; - ahb_gates: ahb_gates at 01c20060 { + ahb_gates: clk at 01c20060 { #clock-cells = <1>; compatible = "allwinner,sun5i-a10s-ahb-gates-clk"; reg = <0x01c20060 0x8>;
@@ -141,7 +145,7 @@ clocks = <&ahb>; }; - apb0_gates: apb0_gates at 01c20068 { + apb0_gates: clk at 01c20068 { #clock-cells = <1>; compatible = "allwinner,sun5i-a10s-apb0-gates-clk"; reg = <0x01c20068 0x4>;
@@ -164,7 +168,7 @@ clocks = <&apb1_mux>; }; - apb1_gates: apb1_gates at 01c2006c { + apb1_gates: clk at 01c2006c { #clock-cells = <1>; compatible = "allwinner,sun5i-a10s-apb1-gates-clk"; reg = <0x01c2006c 0x4>;
arch/arm/boot/dts/sun5i-a13.dtsi +14 -10
@@ -47,34 +47,38 @@ clock-frequency = <0>; }; - osc24M: osc24M at 01c20050 { + osc24M: clk at 01c20050 { #clock-cells = <0>; compatible = "allwinner,sun4i-osc-clk"; reg = <0x01c20050 0x4>; clock-frequency = <24000000>; + clock-output-names = "osc24M"; }; - osc32k: osc32k { + osc32k: clk at 0 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; + clock-output-names = "osc32k"; }; - pll1: pll1 at 01c20000 { + pll1: clk at 01c20000 { #clock-cells = <0>; compatible = "allwinner,sun4i-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; + clock-output-names = "pll1"; }; - pll4: pll4 at 01c20018 { + pll4: clk at 01c20018 { #clock-cells = <0>; compatible = "allwinner,sun4i-pll1-clk"; reg = <0x01c20018 0x4>; clocks = <&osc24M>; + clock-output-names = "pll4"; }; - pll5: pll5 at 01c20020 { + pll5: clk at 01c20020 { #clock-cells = <1>; compatible = "allwinner,sun4i-pll5-clk"; reg = <0x01c20020 0x4>;
@@ -82,7 +86,7 @@ clock-output-names = "pll5_ddr", "pll5_other"; }; - pll6: pll6 at 01c20028 { + pll6: clk at 01c20028 { #clock-cells = <1>; compatible = "allwinner,sun4i-pll6-clk"; reg = <0x01c20028 0x4>;
@@ -105,7 +109,7 @@ clocks = <&cpu>; }; - axi_gates: axi_gates at 01c2005c { + axi_gates: clk at 01c2005c { #clock-cells = <1>; compatible = "allwinner,sun4i-axi-gates-clk"; reg = <0x01c2005c 0x4>;
@@ -120,7 +124,7 @@ clocks = <&axi>; }; - ahb_gates: ahb_gates at 01c20060 { + ahb_gates: clk at 01c20060 { #clock-cells = <1>; compatible = "allwinner,sun5i-a13-ahb-gates-clk"; reg = <0x01c20060 0x8>;
@@ -140,7 +144,7 @@ clocks = <&ahb>; }; - apb0_gates: apb0_gates at 01c20068 { + apb0_gates: clk at 01c20068 { #clock-cells = <1>; compatible = "allwinner,sun5i-a13-apb0-gates-clk"; reg = <0x01c20068 0x4>;
@@ -162,7 +166,7 @@ clocks = <&apb1_mux>; }; - apb1_gates: apb1_gates at 01c2006c { + apb1_gates: clk at 01c2006c { #clock-cells = <1>; compatible = "allwinner,sun5i-a13-apb1-gates-clk"; reg = <0x01c2006c 0x4>;
Signature · 1 line
1.8.5.2
PATCH v3 7/8 ARM: dts: sun6i: rename clock node names to clk@N
In reply to Chen-Yu TsaiDevice tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match.
--- arch/arm/boot/dts/sun6i-a31.dtsi | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-)
arch/arm/boot/dts/sun6i-a31.dtsi +7 -5
@@ -60,17 +60,19 @@ clock-frequency = <24000000>; }; - osc32k: osc32k { + osc32k: clk at 0 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; + clock-output-names = "osc32k"; }; - pll1: pll1 at 01c20000 { + pll1: clk at 01c20000 { #clock-cells = <0>; compatible = "allwinner,sun6i-a31-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; + clock-output-names = "pll1"; }; /*
@@ -120,7 +122,7 @@ clocks = <&ahb1_mux>; }; - ahb1_gates: ahb1_gates at 01c20060 { + ahb1_gates: clk at 01c20060 { #clock-cells = <1>; compatible = "allwinner,sun6i-a31-ahb1-gates-clk"; reg = <0x01c20060 0x8>;
@@ -148,7 +150,7 @@ clocks = <&ahb1>; }; - apb1_gates: apb1_gates at 01c20060 { + apb1_gates: clk at 01c20068 { #clock-cells = <1>; compatible = "allwinner,sun6i-a31-apb1-gates-clk"; reg = <0x01c20068 0x4>;
@@ -172,7 +174,7 @@ clocks = <&apb2_mux>; }; - apb2_gates: apb2_gates at 01c2006c { + apb2_gates: clk at 01c2006c { #clock-cells = <1>; compatible = "allwinner,sun6i-a31-apb2-gates-clk"; reg = <0x01c2006c 0x4>;
Signature · 1 line
1.8.5.2
PATCH v3 8/8 ARM: dts: sun7i: rename clock node names to clk@N
In reply to Chen-Yu TsaiDevice tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match.
Also add the output name for pll5 to use as the clock name.
--- arch/arm/boot/dts/sun7i-a20.dtsi | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-)
arch/arm/boot/dts/sun7i-a20.dtsi +11 -8
@@ -46,11 +46,12 @@ #size-cells = <1>; ranges; - osc24M: osc24M at 01c20050 { + osc24M: clk at 01c20050 { #clock-cells = <0>; compatible = "allwinner,sun4i-osc-clk"; reg = <0x01c20050 0x4>; clock-frequency = <24000000>; + clock-output-names = "osc24M"; }; osc32k: clk at 0 {
@@ -60,21 +61,23 @@ clock-output-names = "osc32k"; }; - pll1: pll1 at 01c20000 { + pll1: clk at 01c20000 { #clock-cells = <0>; compatible = "allwinner,sun4i-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; + clock-output-names = "pll1"; }; - pll4: pll4 at 01c20018 { + pll4: clk at 01c20018 { #clock-cells = <0>; compatible = "allwinner,sun4i-pll1-clk"; reg = <0x01c20018 0x4>; clocks = <&osc24M>; + clock-output-names = "pll4"; }; - pll5: pll5 at 01c20020 { + pll5: clk at 01c20020 { #clock-cells = <1>; compatible = "allwinner,sun4i-pll5-clk"; reg = <0x01c20020 0x4>;
@@ -82,7 +85,7 @@ clock-output-names = "pll5_ddr", "pll5_other"; }; - pll6: pll6 at 01c20028 { + pll6: clk at 01c20028 { #clock-cells = <1>; compatible = "allwinner,sun4i-pll6-clk"; reg = <0x01c20028 0x4>;
@@ -111,7 +114,7 @@ clocks = <&axi>; }; - ahb_gates: ahb_gates at 01c20060 { + ahb_gates: clk at 01c20060 { #clock-cells = <1>; compatible = "allwinner,sun7i-a20-ahb-gates-clk"; reg = <0x01c20060 0x8>;
@@ -138,7 +141,7 @@ clocks = <&ahb>; }; - apb0_gates: apb0_gates at 01c20068 { + apb0_gates: clk at 01c20068 { #clock-cells = <1>; compatible = "allwinner,sun7i-a20-apb0-gates-clk"; reg = <0x01c20068 0x4>;
@@ -163,7 +166,7 @@ clocks = <&apb1_mux>; }; - apb1_gates: apb1_gates at 01c2006c { + apb1_gates: clk at 01c2006c { #clock-cells = <1>; compatible = "allwinner,sun7i-a20-apb1-gates-clk"; reg = <0x01c2006c 0x4>;
Signature · 1 line
1.8.5.2
Emilio López
maintainerv3 cover ARM: sunxi: rename DT clock node names to clk@N
In reply to Chen-Yu TsaiHi,
El 09/01/14 05:52, Chen-Yu Tsai escribi?:
Quoted 35 lines
This is v3 of the clock node renaming patch series, which renames the clock nodes in sunxi dts to conform to device tree naming conventions, i.e. clk at N. Dummy clocks that will be renamed/removed later, or clocks sharing registers are not renamed.
Renamed clock nodes have clock-output-names properties added to desginate their names. Support for this is added in the first patch.
Changes since v2:
* Dropped Cubietruck dts i2c controller patch. Maxime has taken it.
* Changed ARM in commit messages to uppercase.
* Add pll5, pll6 clock names tofactors_datatied to compatible strings.
* Dropped pll5 output name in dts due to the previous change.
* Added dts binding documentation for "clock-output-names", as well as examples.Changes since v1:
* Fixed pll5, pll6 divs clock name handling
Cheers
ChenYuChen-Yu Tsai (8):
clk: sunxi: add clock-output-names dt property support
clk: sunxi: update clock-output-names dt binding documentation
clk: sunxi: add names for pll5, pll6 parent clocks tofactors_data
clk: sunxi: get divs parent clock name from parent factor clock
ARM: dts: sun4i: rename clock node names to clk at N
ARM: dts: sun5i: rename clock node names to clk at N
ARM: dts: sun6i: rename clock node names to clk at N
ARM: dts: sun7i: rename clock node names to clk at N
Quoted 8 lines
Documentation/devicetree/bindings/clock/sunxi.txt | 36 +++++++++++++++++++---- arch/arm/boot/dts/sun4i-a10.dtsi | 24 ++++++++------- arch/arm/boot/dts/sun5i-a10s.dtsi | 24 ++++++++------- arch/arm/boot/dts/sun5i-a13.dtsi | 24 ++++++++------- arch/arm/boot/dts/sun6i-a31.dtsi | 12 ++++---- arch/arm/boot/dts/sun7i-a20.dtsi | 19 +++++++----- drivers/clk/sunxi/clk-sunxi.c | 36 ++++++++++++++++------- 7 files changed, 117 insertions(+), 58 deletions(-)
The series looks good to me, other than the comment I made. Once that's settled, and if Mike, Maxime or anyone else have no further comments, I'll queue 1-4 for 3.15.
Cheers, and thanks for working on this!
Emilio
v3 cover ARM: sunxi: rename DT clock node names to clk@N
Quoting Emilio L?pez (2014-01-16 19:06:15)
Quoted 47 lines
Hi,
El 09/01/14 05:52, Chen-Yu Tsai escribi?:
Quoted 35 lines
This is v3 of the clock node renaming patch series, which renames the clock nodes in sunxi dts to conform to device tree naming conventions, i.e. clk at N. Dummy clocks that will be renamed/removed later, or clocks sharing registers are not renamed.
Renamed clock nodes have clock-output-names properties added to desginate their names. Support for this is added in the first patch.
Changes since v2:
* Dropped Cubietruck dts i2c controller patch. Maxime has taken it.
* Changed ARM in commit messages to uppercase.
* Add pll5, pll6 clock names tofactors_datatied to compatible strings.
* Dropped pll5 output name in dts due to the previous change.
* Added dts binding documentation for "clock-output-names", as well as examples.Changes since v1:
* Fixed pll5, pll6 divs clock name handling
Cheers
ChenYuChen-Yu Tsai (8):
clk: sunxi: add clock-output-names dt property support
clk: sunxi: update clock-output-names dt binding documentation
clk: sunxi: add names for pll5, pll6 parent clocks tofactors_data
clk: sunxi: get divs parent clock name from parent factor clock
ARM: dts: sun4i: rename clock node names to clk at N
ARM: dts: sun5i: rename clock node names to clk at N
ARM: dts: sun6i: rename clock node names to clk at N
ARM: dts: sun7i: rename clock node names to clk at NQuoted 8 lines
Documentation/devicetree/bindings/clock/sunxi.txt | 36 +++++++++++++++++++---- arch/arm/boot/dts/sun4i-a10.dtsi | 24 ++++++++------- arch/arm/boot/dts/sun5i-a10s.dtsi | 24 ++++++++------- arch/arm/boot/dts/sun5i-a13.dtsi | 24 ++++++++------- arch/arm/boot/dts/sun6i-a31.dtsi | 12 ++++---- arch/arm/boot/dts/sun7i-a20.dtsi | 19 +++++++----- drivers/clk/sunxi/clk-sunxi.c | 36 ++++++++++++++++------- 7 files changed, 117 insertions(+), 58 deletions(-)
Quoted 3 lines
The series looks good to me, other than the comment I made. Once that's settled, and if Mike, Maxime or anyone else have no further comments, I'll queue 1-4 for 3.15.
Ack for patches 1-4.
Regards,
Mike
Quoted 4 lines
Cheers, and thanks for working on this!
Emilio