Skip to contentSkip to conversation

ARM: tegra20: Add a missing entry in the pullid enum

PATCH New Alban Bedel 2 participants 3 messages Jan 15, 2014 – Jan 20, 2014

Subsystems (2)
Arm (32-bit) Tegra architecture support
lore
Share & tools
lore

Alban Bedel

author
#0 lore raw

PATCH 1/1 ARM: tegra20: Add a missing entry in the pullid enum

It seems two entries were merged in one when this file has been created. The GPSLXAU entries is obviously a mix of GPU and SLXA which are next to each other according to the datasheet. Moreover it can be noticed because the APB_MISC_PP_PULLUPDOWN_REG_B_0 register only have 15 entries instead of 16.

Also fix the pin group descriptions that were using these buggy entries. In particular SLXA that needed to used CRTP to actually write the SLXA register.

Signed-off-by Alban Bedel <[email protected]>
---
 arch/arm/cpu/tegra20-common/pinmux.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
arch/arm/cpu/tegra20-common/pinmux.c +4 -4
index a65e991..5c80ed9 100644
@@ -190,7 +190,8 @@ enum pmux_pullid {
 
 	PUCTL_SPDI,
 	PUCTL_SPDO,
-	PUCTL_GPSLXAU,
+	PUCTL_GPU,
+	PUCTL_SLXA,
 	PUCTL_CRTP,
 	PUCTL_SLXC,
 	PUCTL_SLXD,

@@ -333,8 +334,7 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
 	PIN(DTD,  VI,    RSVD,   SDIO2,  VI,        RSVD,        RSVD1),
 	PIN(DTE,  VI,    RSVD,   RSVD,   VI,        SPI1,        RSVD1),
 
-	PINP(GPU, UART,  PWM,    UARTA,  GMI,       RSVD,        RSVD4,
-		GPSLXAU),
+	PIN(GPU,  UART,  PWM,    UARTA,  GMI,       RSVD,        RSVD4),
 	PIN(GPV,  SD,    PCIE,   RSVD,   RSVD,      RSVD,        PCIE),
 	PIN(I2CP, SYS,   I2C,    RSVD,   RSVD,      RSVD,        RSVD4),
 	PIN(IRTX, UART,  UARTA,  UARTB,  GMI,       SPI4,        UARTB),

@@ -356,7 +356,7 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
 	PIN(SDC,  SD,    PWM,    TWC,    SDIO3,     SPI3,        TWC),
 	PIN(SDD,  SD,    UARTA,  PWM,    SDIO3,     SPI3,        PWM),
 	PIN_RESERVED,
-	PINP(SLXA, SD,   PCIE,   SPI4,   SDIO3,     SPI2,        PCIE, CRTP),
+	PIN(SLXA, SD,    PCIE,   SPI4,   SDIO3,     SPI2,        PCIE),
 	PIN(SLXC, SD,    SPDIF,  SPI4,   SDIO3,     SPI2,        SPI4),
 	PIN(SLXD, SD,    SPDIF,  SPI4,   SDIO3,     SPI2,        SPI4),
 	PIN(SLXK, SD,    PCIE,   SPI4,   SDIO3,     SPI2,        PCIE),
Signature · 1 line
1.8.5.2
#1 lore raw

PATCH 1/1 ARM: tegra20: Add a missing entry in the pullid enum

Quoted 9 lines · Alban Bedel

It seems two entries were merged in one when this file has been created. The GPSLXAU entries is obviously a mix of GPU and SLXA which are next to each other according to the datasheet. Moreover it can be noticed because the APB_MISC_PP_PULLUPDOWN_REG_B_0 register only have 15 entries instead of 16.

Also fix the pin group descriptions that were using these buggy entries. In particular SLXA that needed to used CRTP to actually write the SLXA register.

This does appear to match the kernel's pinctrl driver, so,

Acked-by Stephen Warren <[email protected]>

I wonder how many more similar issues there are. Did you check the whole file for this kind of issue, or just debug a problem with one particular pin/group?

author
#2 lore raw

PATCH 1/1 ARM: tegra20: Add a missing entry in the pullid enum

Quoted 11 lines · On Wed, 15 Jan 2014 11:36:03 -0700 Stephen Warren <[email protected]> wrote:
Quoted 9 lines · Alban Bedel

It seems two entries were merged in one when this file has been created. The GPSLXAU entries is obviously a mix of GPU and SLXA which are next to each other according to the datasheet. Moreover it can be noticed because the APB_MISC_PP_PULLUPDOWN_REG_B_0 register only have 15 entries instead of 16.

Also fix the pin group descriptions that were using these buggy entries. In particular SLXA that needed to used CRTP to actually write the SLXA register.

Quoted 6 lines

This does appear to match the kernel's pinctrl driver, so,

Acked-by Stephen Warren <[email protected]>

I wonder how many more similar issues there are. Did you check the whole file for this kind of issue, or just debug a problem with one particular pin/group?

I found this while trying to get the internal pull up enabled on UARTD. Afterwards I checked the whole enum and the table but everything else seems to be correct.

Alban