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drm/i915: Enable 5.4Ghz (HBR2) link rate for Displayport 1.2-capable devices

PATCH Superseded Todd Previte 4 participants 15 messages Jan 17, 2014 – Jan 21, 2014

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DRM drivers Intel i915
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Todd Previte

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#0 lore raw

PATCH 1/1 drm/i915: Enable 5.4Ghz (HBR2) link rate for Displayport 1.2-capable devices

For HSW+ platforms, enable the 5.4Ghz (HBR2) link rate for devices that support it. The sink device must report that is supports Displayport 1.2 and the HBR2 bit rate in the DPCD in order to use HBR2.

---
 drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +15 -6
index 7df5085..f92d1c0 100644
@@ -102,7 +102,10 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
 	case DP_LINK_BW_2_7:
 		break;
 	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
-		max_link_bw = DP_LINK_BW_2_7;
+        if (intel_dp->dpcd[DP_DPCD_REV] == 0x12)
+            max_link_bw = DP_LINK_BW_5_4;
+        else
+            max_link_bw = DP_LINK_BW_2_7;
 		break;
 	default:
 		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",

@@ -805,9 +808,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
 	int lane_count, clock;
 	int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
-	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
+    /* Conveniently, the link BW constants become indices with a shift...*/
+    int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
 	int bpp, mode_rate;
-	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
+	static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
 	int link_avail, link_clock;
 
 	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)

@@ -2621,10 +2625,15 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 	bool channel_eq = false;
 	int tries, cr_tries;
 	uint32_t DP = intel_dp->DP;
+    uint32_t training_pattern = DP_TRAINING_PATTERN_2;
+
+    /* Training Pattern 3 for HBR2 */
+    if (intel_dp->link_bw == DP_LINK_BW_5_4)
+        training_pattern = DP_TRAINING_PATTERN_3;
 
 	/* channel equalization */
 	if (!intel_dp_set_link_train(intel_dp, &DP,
-				     DP_TRAINING_PATTERN_2 |
+				     training_pattern |
 				     DP_LINK_SCRAMBLING_DISABLE)) {
 		DRM_ERROR("failed to start channel equalization\n");
 		return;

@@ -2652,7 +2661,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
 			intel_dp_start_link_train(intel_dp);
 			intel_dp_set_link_train(intel_dp, &DP,
-						DP_TRAINING_PATTERN_2 |
+						training_pattern |
 						DP_LINK_SCRAMBLING_DISABLE);
 			cr_tries++;
 			continue;

@@ -2668,7 +2677,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 			intel_dp_link_down(intel_dp);
 			intel_dp_start_link_train(intel_dp);
 			intel_dp_set_link_train(intel_dp, &DP,
-						DP_TRAINING_PATTERN_2 |
+						training_pattern |
 						DP_LINK_SCRAMBLING_DISABLE);
 			tries = 0;
 			cr_tries++;
Signature · 1 line
1.8.1.2
#1 lore raw
Quoted 3 lines · Todd Previte

For HSW+ platforms, enable the 5.4Ghz (HBR2) link rate for devices that support it. The sink device must report that is supports Displayport 1.2 and the HBR2 bit rate in the DPCD in order to use HBR2.

sob line missing.

Quoted 9 lines
---
 drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +0 -0
index 7df5085..f92d1c0 100644

drivers/gpu/drm/i915/intel_dp.c intel_dp_max_link_bw(struct intel_dp *intel_dp) · line 108

Quoted 8 lines
drivers/gpu/drm/i915/intel_dp.c +4 -1
@@ -102,7 +102,10 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
        case DP_LINK_BW_2_7:
                break;
        case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
-               max_link_bw = DP_LINK_BW_2_7;
+        if (intel_dp->dpcd[DP_DPCD_REV] == 0x12)
+            max_link_bw = DP_LINK_BW_5_4;
+        else
+            max_link_bw = DP_LINK_BW_2_7;

Is this really required, i.e. do we have dp 1.1 machines in the wild which advertise 5.4 but can't? In any case you also need to have a IS_HSW || IS_BDW check here, since only those two platforms support 5.4 GHz.

Quoted 17 lines
drivers/gpu/drm/i915/intel_dp.c +3 -2
                break;
        default:
                WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",

@@ -805,9 +808,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
        struct intel_connector *intel_connector = intel_dp->attached_connector;
        int lane_count, clock;
        int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
-       int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
+    /* Conveniently, the link BW constants become indices with a shift...*/
+    int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
        int bpp, mode_rate;
-       static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
+       static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
        int link_avail, link_clock;
 
        if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)

drivers/gpu/drm/i915/intel_dp.c intel_dp_complete_link_train(struct intel_dp *intel_dp) · line 2632

Quoted 8 lines
drivers/gpu/drm/i915/intel_dp.c +5 -0
@@ -2621,10 +2625,15 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
        bool channel_eq = false;
        int tries, cr_tries;
        uint32_t DP = intel_dp->DP;
+    uint32_t training_pattern = DP_TRAINING_PATTERN_2;
+
+    /* Training Pattern 3 for HBR2 */
+    if (intel_dp->link_bw == DP_LINK_BW_5_4)
+        training_pattern = DP_TRAINING_PATTERN_3;

Hm, I've thought that with 5.4 we're supposed to do both pattern 2&3. But tbh I didn't bother to dig out the spec ;-) Does it hurt not to? Also, is there any harm in using pattern 3 for all dp 1.2 capable sinks? I've thought that it should give us more reliable link training, so might be beneficial not just for 5.4 mode. -Daniel

Quoted 32 lines
drivers/gpu/drm/i915/intel_dp.c +3 -4
        /* channel equalization */
        if (!intel_dp_set_link_train(intel_dp, &DP,
-                                    DP_TRAINING_PATTERN_2 |
+                                    training_pattern |
                                     DP_LINK_SCRAMBLING_DISABLE)) {
                DRM_ERROR("failed to start channel equalization\n");
                return;

@@ -2652,7 +2661,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
                if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
                        intel_dp_start_link_train(intel_dp);
                        intel_dp_set_link_train(intel_dp, &DP,
-                                               DP_TRAINING_PATTERN_2 |
+                                               training_pattern |
                                                DP_LINK_SCRAMBLING_DISABLE);
                        cr_tries++;
                        continue;

@@ -2668,7 +2677,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
                        intel_dp_link_down(intel_dp);
                        intel_dp_start_link_train(intel_dp);
                        intel_dp_set_link_train(intel_dp, &DP,
-                                               DP_TRAINING_PATTERN_2 |
+                                               training_pattern |
                                                DP_LINK_SCRAMBLING_DISABLE);
                        tries = 0;
                        cr_tries++;
--

1.8.1.2

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Signature · 3 lines
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
author
#2 lore raw
Quoted 5 lines · Daniel Vetter
Quoted 3 lines · Todd Previte

For HSW+ platforms, enable the 5.4Ghz (HBR2) link rate for devices that support it. The sink device must report that is supports Displayport 1.2 and the HBR2 bit rate in the DPCD in order to use HBR2.

sob line missing.

Oops. I'll add

Signed-off-by Todd Previte <[email protected]>

to the next revision.

Quoted 14 lines
Quoted 14 lines
---
  drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++------
  1 file changed, 15 insertions(+), 6 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +0 -1
index 7df5085..f92d1c0 100644
@@ -102,7 +102,10 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
         case DP_LINK_BW_2_7:
                 break;
         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
-               max_link_bw = DP_LINK_BW_2_7;
Quoted 8 lines

drivers/gpu/drm/i915/intel_dp.c intel_dp_max_link_bw(struct intel_dp *intel_dp) · line 108

Quoted 4 lines
drivers/gpu/drm/i915/intel_dp.c +4 -0
+        if (intel_dp->dpcd[DP_DPCD_REV] == 0x12)
+            max_link_bw = DP_LINK_BW_5_4;
+        else
+            max_link_bw = DP_LINK_BW_2_7;

Is this really required, i.e. do we have dp 1.1 machines in the wild which advertise 5.4 but can't? In any case you also need to have a IS_HSW || IS_BDW check here, since only those two platforms support 5.4 GHz.

I've not seen a case where a 1.1a capable device advertises HBR2, no. I *have* seen the case where the sink reports that it only supports RBR (1.62Ghz) but is in fact capable of 2.7Ghz. This is more of a safety measure to eliminate potential training problems, but is not strictly necessary to support HBR2. It does need the IS_HSW || IS_BDW though, so I'll fix that and resend.

Quoted 15 lines
Quoted 15 lines
drivers/gpu/drm/i915/intel_dp.c +3 -2
                 break;
         default:
                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",

@@ -805,9 +808,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
         struct intel_connector *intel_connector = intel_dp->attached_connector;
         int lane_count, clock;
         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
-       int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
+    /* Conveniently, the link BW constants become indices with a shift...*/
+    int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
         int bpp, mode_rate;
-       static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
+       static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
         int link_avail, link_clock;
Quoted 16 lines

drivers/gpu/drm/i915/intel_dp.c intel_dp_complete_link_train(struct intel_dp *intel_dp) · line 2632

Quoted 10 lines
drivers/gpu/drm/i915/intel_dp.c +5 -0
         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)

@@ -2621,10 +2625,15 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
         bool channel_eq = false;
         int tries, cr_tries;
         uint32_t DP = intel_dp->DP;
+    uint32_t training_pattern = DP_TRAINING_PATTERN_2;
+
+    /* Training Pattern 3 for HBR2 */
+    if (intel_dp->link_bw == DP_LINK_BW_5_4)
+        training_pattern = DP_TRAINING_PATTERN_3;

Hm, I've thought that with 5.4 we're supposed to do both pattern 2&3. But tbh I didn't bother to dig out the spec ;-) Does it hurt not to? Also, is there any harm in using pattern 3 for all dp 1.2 capable sinks? I've thought that it should give us more reliable link training, so might be beneficial not just for 5.4 mode. -Daniel

Nope. For 5.4Ghz the source is supposed to use TPS3 in place of TPS2 in the channel equalization phase. I think it would cause problems if we try to use both TPS2 and TPS3. I suspect the sink device would simple not lock onto the pattern from TPS2 since it's expecting pattern 3 when set for HBR2. So all that would do is effectively delay link training until such time as TPS3 was being transmitted.

There is a bit in the DPCD (bit 6, DPCD 0x002) that indicates whether or not a sink device supports TPS3. For these devices, we should be using TPS3 instead of TPS2 for the channel equalization phase, yes. The code doesn't currently check this bit but it should. I'll add that into the configuration computation to enable TPS3 for 1.2 devices that support it.

Quoted 34 lines
Quoted 32 lines
drivers/gpu/drm/i915/intel_dp.c +3 -4
         /* channel equalization */
         if (!intel_dp_set_link_train(intel_dp, &DP,
-                                    DP_TRAINING_PATTERN_2 |
+                                    training_pattern |
                                      DP_LINK_SCRAMBLING_DISABLE)) {
                 DRM_ERROR("failed to start channel equalization\n");
                 return;

@@ -2652,7 +2661,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
                         intel_dp_start_link_train(intel_dp);
                         intel_dp_set_link_train(intel_dp, &DP,
-                                               DP_TRAINING_PATTERN_2 |
+                                               training_pattern |
                                                 DP_LINK_SCRAMBLING_DISABLE);
                         cr_tries++;
                         continue;

@@ -2668,7 +2677,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
                         intel_dp_link_down(intel_dp);
                         intel_dp_start_link_train(intel_dp);
                         intel_dp_set_link_train(intel_dp, &DP,
-                                               DP_TRAINING_PATTERN_2 |
+                                               training_pattern |
                                                 DP_LINK_SCRAMBLING_DISABLE);
                         tries = 0;
                         cr_tries++;
--

1.8.1.2

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

#3 lore raw
Quoted 17 lines · Todd Previte
Quoted 9 lines
Quoted 9 lines
drivers/gpu/drm/i915/intel_dp.c +0 -1
index 7df5085..f92d1c0 100644
@@ -102,7 +102,10 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
        case DP_LINK_BW_2_7:
                break;
        case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
-               max_link_bw = DP_LINK_BW_2_7;
Quoted 8 lines

drivers/gpu/drm/i915/intel_dp.c intel_dp_max_link_bw(struct intel_dp *intel_dp) · line 108

Quoted 4 lines
drivers/gpu/drm/i915/intel_dp.c +4 -0
+        if (intel_dp->dpcd[DP_DPCD_REV] == 0x12)
+            max_link_bw = DP_LINK_BW_5_4;
+        else
+            max_link_bw = DP_LINK_BW_2_7;

Is this really required, i.e. do we have dp 1.1 machines in the wild which advertise 5.4 but can't? In any case you also need to have a IS_HSW || IS_BDW check here, since only those two platforms support 5.4 GHz.

Quoted 6 lines

I've not seen a case where a 1.1a capable device advertises HBR2, no. I *have* seen the case where the sink reports that it only supports RBR (1.62Ghz) but is in fact capable of 2.7Ghz. This is more of a safety measure to eliminate potential training problems, but is not strictly necessary to support HBR2. It does need the IS_HSW || IS_BDW though, so I'll fix that and resend.

Can we make it IS_HSW || INTEL_INFO(dev)->gen >= 8, we can't quite predict the future but new platforms supporting what old platforms do support is a bet we take elsewere.

Signature · 1 line
Damien
author
#4 lore raw
Quoted 24 lines · Damien Lespiau
Quoted 17 lines · Todd Previte
Quoted 9 lines
Quoted 9 lines
drivers/gpu/drm/i915/intel_dp.c +0 -1
index 7df5085..f92d1c0 100644
@@ -102,7 +102,10 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
         case DP_LINK_BW_2_7:
                 break;
         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
-               max_link_bw = DP_LINK_BW_2_7;
Quoted 8 lines

drivers/gpu/drm/i915/intel_dp.c intel_dp_max_link_bw(struct intel_dp *intel_dp) · line 108

Quoted 4 lines
drivers/gpu/drm/i915/intel_dp.c +4 -0
+        if (intel_dp->dpcd[DP_DPCD_REV] == 0x12)
+            max_link_bw = DP_LINK_BW_5_4;
+        else
+            max_link_bw = DP_LINK_BW_2_7;

Is this really required, i.e. do we have dp 1.1 machines in the wild which advertise 5.4 but can't? In any case you also need to have a IS_HSW || IS_BDW check here, since only those two platforms support 5.4 GHz.

Quoted 6 lines

I've not seen a case where a 1.1a capable device advertises HBR2, no. I *have* seen the case where the sink reports that it only supports RBR (1.62Ghz) but is in fact capable of 2.7Ghz. This is more of a safety measure to eliminate potential training problems, but is not strictly necessary to support HBR2. It does need the IS_HSW || IS_BDW though, so I'll fix that and resend.

Quoted 4 lines

Can we make it IS_HSW || INTEL_INFO(dev)->gen >= 8, we can't quite predict the future but new platforms supporting what old platforms do support is a bet we take elsewere.

Sounds like a better solution. I should have that integrated shortly.

-T

#5 lore raw
In reply to Todd Previte
Quoted 12 lines · Todd Previte

For HSW+ platforms, enable the 5.4Ghz (HBR2) link rate for devices that support it. The sink device must report that is supports Displayport 1.2 and the HBR2 bit rate in the DPCD in order to use HBR2.

---
 drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +0 -0
index 7df5085..f92d1c0 100644

drivers/gpu/drm/i915/intel_dp.c intel_dp_max_link_bw(struct intel_dp *intel_dp) · line 109

Quoted 9 lines
drivers/gpu/drm/i915/intel_dp.c +4 -1
@@ -102,7 +102,10 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
 	case DP_LINK_BW_2_7:
 		break;
 	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
-		max_link_bw = DP_LINK_BW_2_7;
+        if (intel_dp->dpcd[DP_DPCD_REV] == 0x12)
+            max_link_bw = DP_LINK_BW_5_4;
+        else
+            max_link_bw = DP_LINK_BW_2_7;
 		break;

I see spaces instead of tabs. You can use the useful checkpatch.pl script on patches to catch those pesky style issues (from within a linux tree):

$ ./scripts/checkpatch.pl 0001-drm-i915-Enable-5.4Ghz-HBR2-link-rate-for-Displaypor.patch

[...]

total: 6 errors, 9 warnings, 55 lines checked

Signature · 1 line
Damien
maintainer
#6 lore raw
Quoted 9 lines · Damien Lespiau

I see spaces instead of tabs. You can use the useful checkpatch.pl script on patches to catch those pesky style issues (from within a linux tree):

$ ./scripts/checkpatch.pl 0001-drm-i915-Enable-5.4Ghz-HBR2-link-rate-for-Displaypor.patch

[...]

total: 6 errors, 9 warnings, 55 lines checked

Should anyone find this useful, I have these to check branches in my local repos directly:

alias checkpatch='/path/to/checkpatch.pl -q --emacs --strict'

checkbranch()

{
    local commit
    local range

    if [ -z "$1" ]; then
	range="origin..HEAD"
    elif [ -n "`echo $1 | grep '\.\.'`" ]; then
	range="$1"
    else
	range="$1..HEAD"
    fi

    for commit in `git rev-list --reverse $range`; do
	git --no-pager log --oneline -1 $commit
	git format-patch --stdout -1 $commit | checkpatch -
    done
}

Then I can do:

Check local patches against origin:

$ checkbranch

Check local patches against drm-intel/drm-intel-nightly:

$ checkbranch drm-intel/drm-intel-nightly

Check a revision range:

$ checkbranch commit1..commit2

Do note that checkpatch is not the law. But it helps you get some of the little things straight.

HTH,
Jani.

Signature · 1 line
Jani Nikula, Intel Open Source Technology Center
author
#7 lore raw
Quoted 43 lines · Jani Nikula
Quoted 9 lines · Damien Lespiau

I see spaces instead of tabs. You can use the useful checkpatch.pl script on patches to catch those pesky style issues (from within a linux tree):

$ ./scripts/checkpatch.pl 0001-drm-i915-Enable-5.4Ghz-HBR2-link-rate-for-Displaypor.patch

[...]

total: 6 errors, 9 warnings, 55 lines checked

Should anyone find this useful, I have these to check branches in my local repos directly:

alias checkpatch='/path/to/checkpatch.pl -q --emacs --strict'

checkbranch()

{
     local commit
     local range

     if [ -z "$1" ]; then
	range="origin..HEAD"
     elif [ -n "`echo $1 | grep '\.\.'`" ]; then
	range="$1"
     else
	range="$1..HEAD"
     fi

     for commit in `git rev-list --reverse $range`; do
	git --no-pager log --oneline -1 $commit
	git format-patch --stdout -1 $commit | checkpatch -
     done
}

Then I can do:

Check local patches against origin:

$ checkbranch

Check local patches against drm-intel/drm-intel-nightly:

$ checkbranch drm-intel/drm-intel-nightly

Check a revision range:

Quoted 11 lines
$ checkbranch commit1..commit2

Do note that checkpatch is not the law. But it helps you get some of the little things straight.

HTH,
Jani.

Cool thanks Jani. I'll give that a try.

-T

author
#8 lore raw
In reply to Damien Lespiau
Quoted 26 lines · Damien Lespiau
Quoted 12 lines · Todd Previte

For HSW+ platforms, enable the 5.4Ghz (HBR2) link rate for devices that support it. The sink device must report that is supports Displayport 1.2 and the HBR2 bit rate in the DPCD in order to use HBR2.

---
  drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++------
  1 file changed, 15 insertions(+), 6 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +0 -0
index 7df5085..f92d1c0 100644

drivers/gpu/drm/i915/intel_dp.c intel_dp_max_link_bw(struct intel_dp *intel_dp) · line 109

Quoted 9 lines
drivers/gpu/drm/i915/intel_dp.c +4 -1
@@ -102,7 +102,10 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
  	case DP_LINK_BW_2_7:
  		break;
  	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
-		max_link_bw = DP_LINK_BW_2_7;
+        if (intel_dp->dpcd[DP_DPCD_REV] == 0x12)
+            max_link_bw = DP_LINK_BW_5_4;
+        else
+            max_link_bw = DP_LINK_BW_2_7;
  		break;

I see spaces instead of tabs. You can use the useful checkpatch.pl script on patches to catch those pesky style issues (from within a linux tree):

Quoted 6 lines
$ ./scripts/checkpatch.pl 0001-drm-i915-Enable-5.4Ghz-HBR2-link-rate-for-Displaypor.patch

[...]

total: 6 errors, 9 warnings, 55 lines checked

Gah. That's what happens when I make changes with different editors. I'll fix those in the next revision.

-T

author
#10 lore raw

PATCH 1/1 drm/i915: Enable 5.4Ghz (HBR2) link rate for Displayport 1.2-capable devices

For HSW+ platforms, enable the 5.4Ghz (HBR2) link rate for devices that support it. The sink device must report that is supports Displayport 1.2 and the HBR2 bit rate in the DPCD in order to use HBR2.

V2:
- Added training pattern 3 flag to intel_dp struct
- Added check for appropriate hardware to 5.4Ghz link rate configuration
- Added a check for TPS3 supprt in the DPCD read
- Adjusted channel equalization to use TPS3 when appropriate
- Cleaned up whitespace

Signed-off-by Todd Previte <[email protected]>
---
 drivers/gpu/drm/i915/intel_dp.c  | 30 ++++++++++++++++++++++++------
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 25 insertions(+), 6 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +24 -6
index 7df5085..fd87c37 100644
@@ -102,7 +102,11 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
 	case DP_LINK_BW_2_7:
 		break;
 	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
-		max_link_bw = DP_LINK_BW_2_7;
+		if ((IS_HSW(dev) || (INTEL_INFO(dev)->gen >= 8)) &&
+		   (intel_dp->dpcd[DP_DPCD_REV] >= 0x12))
+			max_link_bw = DP_LINK_BW_5_4;
+		else
+			max_link_bw = DP_LINK_BW_2_7;
 		break;
 	default:
 		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",

@@ -805,9 +809,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
 	int lane_count, clock;
 	int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
-	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
+    /* Conveniently, the link BW constants become indices with a shift...*/
+	int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
 	int bpp, mode_rate;
-	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
+	static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
 	int link_avail, link_clock;
 
 	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)

@@ -2621,10 +2626,15 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 	bool channel_eq = false;
 	int tries, cr_tries;
 	uint32_t DP = intel_dp->DP;
+	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
+
+    /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
+	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
+		training_pattern = DP_TRAINING_PATTERN_3;
 
 	/* channel equalization */
 	if (!intel_dp_set_link_train(intel_dp, &DP,
-				     DP_TRAINING_PATTERN_2 |
+				     training_pattern |
 				     DP_LINK_SCRAMBLING_DISABLE)) {
 		DRM_ERROR("failed to start channel equalization\n");
 		return;

@@ -2652,7 +2662,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
 			intel_dp_start_link_train(intel_dp);
 			intel_dp_set_link_train(intel_dp, &DP,
-						DP_TRAINING_PATTERN_2 |
+						training_pattern |
 						DP_LINK_SCRAMBLING_DISABLE);
 			cr_tries++;
 			continue;

@@ -2668,7 +2678,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 			intel_dp_link_down(intel_dp);
 			intel_dp_start_link_train(intel_dp);
 			intel_dp_set_link_train(intel_dp, &DP,
-						DP_TRAINING_PATTERN_2 |
+						training_pattern |
 						DP_LINK_SCRAMBLING_DISABLE);
 			tries = 0;
 			cr_tries++;

@@ -2810,6 +2820,14 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 		}
 	}
 
+	/* Training Pattern 3 support */
+	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
+		intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
+		intel_dp->use_tps3 = true;
+		DRM_DEBUG_KMS("Displayport TPS3 supported");
+	} else
+		intel_dp->use_tps3 = false;
+
 	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
 	      DP_DWN_STRM_PORT_PRESENT))
 		return true; /* native DP sink */
drivers/gpu/drm/i915/intel_drv.h +1 -0
index 9841f78..e934d8d 100644
@@ -488,6 +488,7 @@ struct intel_dp {
 	struct delayed_work panel_vdd_work;
 	bool want_panel_vdd;
 	bool psr_setup_done;
+	bool use_tps3;
 	struct intel_connector *attached_connector;
 };
Signature · 1 line
1.8.1.2
#11 lore raw

Looks good imo, just a bit patch polish. And maybe wait for Ville's confirmation about the stuff we're discussing in private. -Daniel

Quoted 10 lines · Todd Previte

For HSW+ platforms, enable the 5.4Ghz (HBR2) link rate for devices that support it. The sink device must report that is supports Displayport 1.2 and the HBR2 bit rate in the DPCD in order to use HBR2.

V2:
- Added training pattern 3 flag to intel_dp struct
- Added check for appropriate hardware to 5.4Ghz link rate configuration
- Added a check for TPS3 supprt in the DPCD read
- Adjusted channel equalization to use TPS3 when appropriate
- Cleaned up whitespace

Commit message shouldn't be indented (git will do that when displaying a patch automatically) and should be limited to about 70 chars (for to have a bit of space in 80 char mails when replying). Also a white line before the sob-section.

Quoted 11 lines
Signed-off-by Todd Previte <[email protected]>
---
 drivers/gpu/drm/i915/intel_dp.c  | 30 ++++++++++++++++++++++++------
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 25 insertions(+), 6 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +0 -0
index 7df5085..fd87c37 100644

drivers/gpu/drm/i915/intel_dp.c intel_dp_max_link_bw(struct intel_dp *intel_dp) · line 106

Quoted 6 lines
drivers/gpu/drm/i915/intel_dp.c +2 -1
@@ -102,7 +102,11 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
 	case DP_LINK_BW_2_7:
 		break;
 	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
-		max_link_bw = DP_LINK_BW_2_7;
+		if ((IS_HSW(dev) || (INTEL_INFO(dev)->gen >= 8)) &&
+		   (intel_dp->dpcd[DP_DPCD_REV] >= 0x12))

Checkpatch is still a bit unhappy about the alignment of the 2-line condition here, and I concur - imo doing this as suggest helps readiblity quite a bit.

Quoted 20 lines
drivers/gpu/drm/i915/intel_dp.c +6 -2
+			max_link_bw = DP_LINK_BW_5_4;
+		else
+			max_link_bw = DP_LINK_BW_2_7;
 		break;
 	default:
 		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",

@@ -805,9 +809,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
 	int lane_count, clock;
 	int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
-	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
+    /* Conveniently, the link BW constants become indices with a shift...*/
+	int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
 	int bpp, mode_rate;
-	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
+	static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
 	int link_avail, link_clock;
 
 	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)

drivers/gpu/drm/i915/intel_dp.c intel_dp_complete_link_train(struct intel_dp *intel_dp) · line 2631

Quoted 6 lines
drivers/gpu/drm/i915/intel_dp.c +3 -0
@@ -2621,10 +2626,15 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 	bool channel_eq = false;
 	int tries, cr_tries;
 	uint32_t DP = intel_dp->DP;
+	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
+
+    /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/

Indentation of the comment.

Quoted 29 lines
drivers/gpu/drm/i915/intel_dp.c +5 -3
+	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
+		training_pattern = DP_TRAINING_PATTERN_3;
 
 	/* channel equalization */
 	if (!intel_dp_set_link_train(intel_dp, &DP,
-				     DP_TRAINING_PATTERN_2 |
+				     training_pattern |
 				     DP_LINK_SCRAMBLING_DISABLE)) {
 		DRM_ERROR("failed to start channel equalization\n");
 		return;

@@ -2652,7 +2662,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
 			intel_dp_start_link_train(intel_dp);
 			intel_dp_set_link_train(intel_dp, &DP,
-						DP_TRAINING_PATTERN_2 |
+						training_pattern |
 						DP_LINK_SCRAMBLING_DISABLE);
 			cr_tries++;
 			continue;

@@ -2668,7 +2678,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 			intel_dp_link_down(intel_dp);
 			intel_dp_start_link_train(intel_dp);
 			intel_dp_set_link_train(intel_dp, &DP,
-						DP_TRAINING_PATTERN_2 |
+						training_pattern |
 						DP_LINK_SCRAMBLING_DISABLE);
 			tries = 0;
 			cr_tries++;

drivers/gpu/drm/i915/intel_dp.c intel_dp_get_dpcd(struct intel_dp *intel_dp) · line 2825

Quoted 6 lines
drivers/gpu/drm/i915/intel_dp.c +3 -0
@@ -2810,6 +2820,14 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 		}
 	}
 
+	/* Training Pattern 3 support */
+	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
+		intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {

Another 2-line condition which should be aligned.

Quoted 27 lines
drivers/gpu/drm/i915/intel_dp.c +5 -0
+		intel_dp->use_tps3 = true;
+		DRM_DEBUG_KMS("Displayport TPS3 supported");
+	} else
+		intel_dp->use_tps3 = false;
+
 	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
 	      DP_DWN_STRM_PORT_PRESENT))
 		return true; /* native DP sink */
drivers/gpu/drm/i915/intel_drv.h +1 -0
index 9841f78..e934d8d 100644
@@ -488,6 +488,7 @@ struct intel_dp {
 	struct delayed_work panel_vdd_work;
 	bool want_panel_vdd;
 	bool psr_setup_done;
+	bool use_tps3;
 	struct intel_connector *attached_connector;
 };
Signature · 6 lines
1.8.1.2

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Signature · 3 lines
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
author
#12 lore raw

PATCH v3 1/1 drm/i915: Enable 5.4Ghz (HBR2) link rate for Displayport 1.2-capable devices

In reply to Todd Previte

More whitepsace cleanup.

One caveat with this patch: current link policy dictates that the driver will train the "wide and slow", i.e. max lanes at low speed. It will increase lanes and speed when the specified resolution demands greater bandwidth. Consequently, the resolution will need to be set such that the data rate exceeds the bandwidth provided by 4 lanes @ 2.4Ghz before the driver will use the new 5.4Ghz rate.

author
#13 lore raw

PATCH v3 1/1 drm/i915: Enable 5.4Ghz (HBR2) link rate for Displayport 1.2-capable devices

For HSW+ platforms, enable the 5.4Ghz (HBR2) link rate for devices that support it. The sink device must report that is supports Displayport 1.2 and the HBR2 bit rate in the DPCD in order to use HBR2.

Signed-off-by Todd Previte <[email protected]>
---
 drivers/gpu/drm/i915/intel_dp.c  | 31 +++++++++++++++++++++++++------
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 26 insertions(+), 6 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +25 -6
index 7df5085..7fb02f6 100644
@@ -96,13 +96,18 @@ static int
 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 {
 	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
+	struct drm_device *dev = intel_dp->attached_connector->base.dev;
 
 	switch (max_link_bw) {
 	case DP_LINK_BW_1_62:
 	case DP_LINK_BW_2_7:
 		break;
 	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
-		max_link_bw = DP_LINK_BW_2_7;
+		if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
+		    intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
+			max_link_bw = DP_LINK_BW_5_4;
+		else
+			max_link_bw = DP_LINK_BW_2_7;
 		break;
 	default:
 		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",

@@ -805,9 +810,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
 	int lane_count, clock;
 	int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
-	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
+	/* Conveniently, the link BW constants become indices with a shift...*/
+	int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
 	int bpp, mode_rate;
-	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
+	static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
 	int link_avail, link_clock;
 
 	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)

@@ -2621,10 +2627,15 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 	bool channel_eq = false;
 	int tries, cr_tries;
 	uint32_t DP = intel_dp->DP;
+	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
+
+	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
+	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
+		training_pattern = DP_TRAINING_PATTERN_3;
 
 	/* channel equalization */
 	if (!intel_dp_set_link_train(intel_dp, &DP,
-				     DP_TRAINING_PATTERN_2 |
+				     training_pattern |
 				     DP_LINK_SCRAMBLING_DISABLE)) {
 		DRM_ERROR("failed to start channel equalization\n");
 		return;

@@ -2652,7 +2663,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
 			intel_dp_start_link_train(intel_dp);
 			intel_dp_set_link_train(intel_dp, &DP,
-						DP_TRAINING_PATTERN_2 |
+						training_pattern |
 						DP_LINK_SCRAMBLING_DISABLE);
 			cr_tries++;
 			continue;

@@ -2668,7 +2679,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 			intel_dp_link_down(intel_dp);
 			intel_dp_start_link_train(intel_dp);
 			intel_dp_set_link_train(intel_dp, &DP,
-						DP_TRAINING_PATTERN_2 |
+						training_pattern |
 						DP_LINK_SCRAMBLING_DISABLE);
 			tries = 0;
 			cr_tries++;

@@ -2810,6 +2821,14 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 		}
 	}
 
+	/* Training Pattern 3 support */
+	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
+	    intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
+		intel_dp->use_tps3 = true;
+		DRM_DEBUG_KMS("Displayport TPS3 supported");
+	} else
+		intel_dp->use_tps3 = false;
+
 	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
 	      DP_DWN_STRM_PORT_PRESENT))
 		return true; /* native DP sink */
drivers/gpu/drm/i915/intel_drv.h +1 -0
index 9841f78..e934d8d 100644
@@ -488,6 +488,7 @@ struct intel_dp {
 	struct delayed_work panel_vdd_work;
 	bool want_panel_vdd;
 	bool psr_setup_done;
+	bool use_tps3;
 	struct intel_connector *attached_connector;
 };
Signature · 1 line
1.8.1.2
#14 lore raw
Quoted 5 lines · Todd Previte

For HSW+ platforms, enable the 5.4Ghz (HBR2) link rate for devices that support it. The sink device must report that is supports Displayport 1.2 and the HBR2 bit rate in the DPCD in order to use HBR2.

Signed-off-by Todd Previte <[email protected]>

As mentioned on irc, please add a per-patch changelog before the sob section in the future. Queued for -next, thanks for the patch. -Daniel

Quoted 111 lines
---
 drivers/gpu/drm/i915/intel_dp.c  | 31 +++++++++++++++++++++++++------
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 26 insertions(+), 6 deletions(-)
drivers/gpu/drm/i915/intel_dp.c +25 -6
index 7df5085..7fb02f6 100644
@@ -96,13 +96,18 @@ static int
 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 {
 	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
+	struct drm_device *dev = intel_dp->attached_connector->base.dev;
 
 	switch (max_link_bw) {
 	case DP_LINK_BW_1_62:
 	case DP_LINK_BW_2_7:
 		break;
 	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
-		max_link_bw = DP_LINK_BW_2_7;
+		if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
+		    intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
+			max_link_bw = DP_LINK_BW_5_4;
+		else
+			max_link_bw = DP_LINK_BW_2_7;
 		break;
 	default:
 		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",

@@ -805,9 +810,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
 	int lane_count, clock;
 	int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
-	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
+	/* Conveniently, the link BW constants become indices with a shift...*/
+	int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
 	int bpp, mode_rate;
-	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
+	static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
 	int link_avail, link_clock;
 
 	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)

@@ -2621,10 +2627,15 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 	bool channel_eq = false;
 	int tries, cr_tries;
 	uint32_t DP = intel_dp->DP;
+	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
+
+	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
+	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
+		training_pattern = DP_TRAINING_PATTERN_3;
 
 	/* channel equalization */
 	if (!intel_dp_set_link_train(intel_dp, &DP,
-				     DP_TRAINING_PATTERN_2 |
+				     training_pattern |
 				     DP_LINK_SCRAMBLING_DISABLE)) {
 		DRM_ERROR("failed to start channel equalization\n");
 		return;

@@ -2652,7 +2663,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
 			intel_dp_start_link_train(intel_dp);
 			intel_dp_set_link_train(intel_dp, &DP,
-						DP_TRAINING_PATTERN_2 |
+						training_pattern |
 						DP_LINK_SCRAMBLING_DISABLE);
 			cr_tries++;
 			continue;

@@ -2668,7 +2679,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 			intel_dp_link_down(intel_dp);
 			intel_dp_start_link_train(intel_dp);
 			intel_dp_set_link_train(intel_dp, &DP,
-						DP_TRAINING_PATTERN_2 |
+						training_pattern |
 						DP_LINK_SCRAMBLING_DISABLE);
 			tries = 0;
 			cr_tries++;

@@ -2810,6 +2821,14 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 		}
 	}
 
+	/* Training Pattern 3 support */
+	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
+	    intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
+		intel_dp->use_tps3 = true;
+		DRM_DEBUG_KMS("Displayport TPS3 supported");
+	} else
+		intel_dp->use_tps3 = false;
+
 	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
 	      DP_DWN_STRM_PORT_PRESENT))
 		return true; /* native DP sink */
drivers/gpu/drm/i915/intel_drv.h +1 -0
index 9841f78..e934d8d 100644
@@ -488,6 +488,7 @@ struct intel_dp {
 	struct delayed_work panel_vdd_work;
 	bool want_panel_vdd;
 	bool psr_setup_done;
+	bool use_tps3;
 	struct intel_connector *attached_connector;
 };
Signature · 6 lines
1.8.1.2

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Signature · 3 lines
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch