Skip to contentSkip to conversation

DRA7: add ABB setup for MPU voltage domain

PATCH In review Nishanth Menon 2 participants 3 messages Jan 14, 2014 – Jan 24, 2014 Arm (32-bit)

lore
Share & tools
lore
#0 lore raw

PATCH 1/1 DRA7: add ABB setup for MPU voltage domain

Patch adds modification to shared omap5 abb_setup() function, and proper registers definitions needed for ABB setup sequence. ABB is initialized for MPU voltage domain at OPP_NOM.

---

 arch/arm/cpu/armv7/omap5/abb.c         |   13 ++++++++++---
 arch/arm/cpu/armv7/omap5/prcm-regs.c   |    8 ++++++++
 arch/arm/include/asm/arch-omap5/omap.h |    2 ++
 3 files changed, 20 insertions(+), 3 deletions(-)
arch/arm/cpu/armv7/omap5/abb.c +10 -3
index 31b6795..3bf8897 100644
@@ -28,18 +28,25 @@
 s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
 {
 	u32 vset;
+	u32 fuse_enable_mask = OMAP5_ABB_FUSE_ENABLE_MASK;
+	u32 fuse_vset_mask = OMAP5_ABB_FUSE_VSET_MASK;
 
+	if (!is_omap54xx()) {
+		/* DRA7 */
+		fuse_enable_mask = DRA7_ABB_FUSE_ENABLE_MASK;
+		fuse_vset_mask = DRA7_ABB_FUSE_VSET_MASK;
+	}
 	/*
 	 * ABB parameters must be properly fused
 	 * otherwise ABB should be disabled
 	 */
 	vset = readl(fuse);
-	if (!(vset & OMAP5_ABB_FUSE_ENABLE_MASK))
+	if (!(vset & fuse_enable_mask))
 		return -1;
 
 	/* prepare VSET value for LDOVBB mux register */
-	vset &= OMAP5_ABB_FUSE_VSET_MASK;
-	vset >>= ffs(OMAP5_ABB_FUSE_VSET_MASK) - 1;
+	vset &= fuse_vset_mask;
+	vset >>= ffs(fuse_vset_mask) - 1;
 	vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1;
 	vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK;
 
arch/arm/cpu/armv7/omap5/prcm-regs.c +8 -0
index 77c428b..ff32807 100644
@@ -432,11 +432,13 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
 	.control_srcomp_code_latch		= 0x4A002E84,
 	.control_ddr_control_ext_0		= 0x4A002E88,
 	.control_padconf_core_base		= 0x4A003400,
+	.control_std_fuse_opp_vdd_mpu_2		= 0x4A003B24,
 	.control_port_emif1_sdram_config	= 0x4AE0C110,
 	.control_port_emif1_lpddr2_nvm_config	= 0x4AE0C114,
 	.control_port_emif2_sdram_config	= 0x4AE0C118,
 	.control_emif1_sdram_config_ext		= 0x4AE0C144,
 	.control_emif2_sdram_config_ext		= 0x4AE0C148,
+	.control_wkup_ldovbb_mpu_voltage_ctrl	= 0x4AE0C158,
 	.control_padconf_mode			= 0x4AE0C5A0,
 	.control_xtal_oscillator		= 0x4AE0C5A4,
 	.control_i2c_2				= 0x4AE0C5A8,
@@ -807,6 +809,9 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_dsp_clkstctrl			= 0x4a005400,
 	.cm_dsp_dsp_clkctrl			= 0x4a005420,
 
+	/* prm irqstatus regs */
+	.prm_irqstatus_mpu_2			= 0x4ae06014,
+
 	/* cm2.ckgen */
 	.cm_clksel_usb_60mhz			= 0x4a008104,
 	.cm_clkmode_dpll_per			= 0x4a008140,
@@ -967,4 +972,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.prm_vc_val_bypass			= 0x4ae07da0,
 	.prm_vc_cfg_i2c_mode			= 0x4ae07db4,
 	.prm_vc_cfg_i2c_clk			= 0x4ae07db8,
+
+	.prm_abbldo_mpu_setup			= 0x4AE07DDC,
+	.prm_abbldo_mpu_ctrl			= 0x4AE07DE0,
 };
arch/arm/include/asm/arch-omap5/omap.h +2 -0
index 34f6fc5..19fdece 100644
@@ -205,6 +205,8 @@ struct s32ktimer {
 /* ABB efuse masks */
 #define OMAP5_ABB_FUSE_VSET_MASK		(0x1F << 24)
 #define OMAP5_ABB_FUSE_ENABLE_MASK		(0x1 << 29)
+#define DRA7_ABB_FUSE_VSET_MASK			(0x1F << 20)
+#define DRA7_ABB_FUSE_ENABLE_MASK		(0x1 << 25)
 #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK	(0x1 << 10)
 #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK	(0x1f << 0)
 
Signature · 1 line
1.7.9.5
#1 lore raw

PATCH 1/1 DRA7: add ABB setup for MPU voltage domain

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Quoted 11 lines · Nishanth Menon

Patch adds modification to shared omap5 abb_setup() function, and proper registers definitions needed for ABB setup sequence. ABB is initialized for MPU voltage domain at OPP_NOM.

arch/arm/cpu/armv7/omap5/abb.c         |   13 ++++++++++--- 
arch/arm/cpu/armv7/omap5/prcm-regs.c   |    8 ++++++++ 
arch/arm/include/asm/arch-omap5/omap.h |    2 ++ 3 files changed,

20 insertions(+), 3 deletions(-)

Quoted 7 lines
(quoted diff) +0 -0

b/arch/arm/cpu/armv7/omap5/abb.c index 31b6795..3bf8897 100644 --- a/arch/arm/cpu/armv7/omap5/abb.c +++ b/arch/arm/cpu/armv7/omap5/abb.c @@ -28,18 +28,25 @@ s8
abb_setup_ldovbb(u32 fuse, u32 ldovbb) { u32 vset; + u32
fuse_enable_mask = OMAP5_ABB_FUSE_ENABLE_MASK; + u32 fuse_vset_mask
= OMAP5_ABB_FUSE_VSET_MASK;

My only concern, which I know the answer to I think, is shouldn't we just have no default values here, and case in the right one for omap5/dra74x and then dra72x in the future, etc, etc. But we don't know enough really to know if future SoCs will need a different statement here, so it's good enough for now.

- --
Tom
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

iQIcBAEBAgAGBQJS1YqfAAoJENk4IS6UOR1WG6YP/3p2A28HH96gnagf/Rd64OKS TpHF9bduHMyiu1BBSfoYuw2pWAhVrnTCTyhFRy6P+xFcU6+V7k+IK8D4CjOTdvvL udgY5fm9tYBJvr8j3GRE5VLoBo/tXFkeKkEhhXh5tNJ0ag5KmKiHqF/0zWkJmj0Y YRmKtrRudl29Ot2vX+zStg/0cdJm37e9/0VDMJnoM+Sc06jlc3MLulh2c+D23gkO IxSdAFHVlFn2YHoxYlE6Vhys49op6Wr41QryxRoLvzSRoTj80oJq9+rMLWul2jpA mjCsslUdOMGm7WaipcjulBTZvLV3Qz1XNgCwUdidBXrpQxhe2VmkTMGzyU49gAC+ QrT+wgXWTKpAIsvLIRZJQ9GJ3I9ZnDrHwRw4mbUX++ey5fwahR7DtafT2DgRxRwb zLU0JpCBh2W98sTzNBfuGda3kYVDoNWu4nGZDB3H2wSn1r+dFNbQPmyWqAzMdFYa aN9G+GeunOi0sU5W9pCXXMbjjA3Iq/SE0zUNqERPOoBusCrUpzo0u6n64iFGfq8i r0EM6Lf5OxCyvqGdUbuDwe1D/fKceInqFglVuFppz87dRunTbU0gr5iGw29i5nkX iSaSoaGHlOlJhF9x5lr2cyTpxdNO6SYsgjr6d57VP8KPs0BMosVQoQ9N+3Y4SwIa S2gO/eIMTP9oA+3PcUPY
=v4DC
-----END PGP SIGNATURE-----

#2 lore raw
In reply to Nishanth Menon
Quoted 6 lines · Nishanth Menon

Patch adds modification to shared omap5 abb_setup() function, and proper registers definitions needed for ABB setup sequence. ABB is initialized for MPU voltage domain at OPP_NOM.

Applied to u-boot-ti/master, thanks!

Signature · 8 lines
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 836 bytes
Desc: Digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20140124/8b2d57ab/attachment.pgp>