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arm64: add DSB after icache flush in __flush_icache_all()

PATCH New Vinayak Kale 3 participants 5 messages Jan 27, 2014 – Jan 28, 2014 arm64

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Vinayak Kale

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#0 lore raw

PATCH 1/1 arm64: add DSB after icache flush in __flush_icache_all()

Add DSB after icache flush operation.

Signed-off-by Vinayak Kale <[email protected]>
---
 arch/arm64/include/asm/cacheflush.h |    1 +
 1 file changed, 1 insertion(+)
arch/arm64/include/asm/cacheflush.h +1 -0
index fea9ee3..88932498 100644
@@ -116,6 +116,7 @@ extern void flush_dcache_page(struct page *);
 static inline void __flush_icache_all(void)
 {
 	asm("ic	ialluis");
+	dsb();
 }
 
 #define flush_dcache_mmap_lock(mapping) \
Signature · 1 line
1.7.9.5
#1 lore raw

PATCH 1/1 arm64: add DSB after icache flush in __flush_icache_all()

Hi Vinayak,

Quoted 1 line · Vinayak Kale

Add DSB after icache flush operation.

Please elaborate a bit on what this achieves (i.e. completion of the maintenance operation).

arch/arm64/include/asm/cacheflush.h extern void flush_dcache_page(struct page *); · line 118

Quoted 13 lines
Signed-off-by Vinayak Kale <[email protected]>
---
 arch/arm64/include/asm/cacheflush.h |    1 +
 1 file changed, 1 insertion(+)
arch/arm64/include/asm/cacheflush.h +0 -0
index fea9ee3..88932498 100644
@@ -116,6 +116,7 @@ extern void flush_dcache_page(struct page *);
 static inline void __flush_icache_all(void)
 {
 	asm("ic	ialluis");

This needs a "memory" clobber to prevent re-ordering by GCC. We should probably check the rest of the code for other occurrences of this too.

arch/arm64/include/asm/cacheflush.h extern void flush_dcache_page(struct page *); · line 119

Quoted 1 line
arch/arm64/include/asm/cacheflush.h +1 -0
+	dsb();

Can you make a corresponding change for arch/arm/ too, please? I think we're missing the barrier there as well.

Will

author
#2 lore raw

PATCH 1/1 arm64: add DSB after icache flush in __flush_icache_all()

Quoted 7 lines · Will Deacon

Hi Vinayak,

Quoted 1 line · Vinayak Kale

Add DSB after icache flush operation.

Please elaborate a bit on what this achieves (i.e. completion of the maintenance operation).

Okay.

Quoted 6 lines
Quoted 6 lines
Signed-off-by Vinayak Kale <[email protected]>
---
 arch/arm64/include/asm/cacheflush.h |    1 +
 1 file changed, 1 insertion(+)
Quoted 11 lines

arch/arm64/include/asm/cacheflush.h extern void flush_dcache_page(struct page *); · line 118

Quoted 8 lines
arch/arm64/include/asm/cacheflush.h +0 -0
index fea9ee3..88932498 100644
@@ -116,6 +116,7 @@ extern void flush_dcache_page(struct page *);
 static inline void __flush_icache_all(void)
 {
      asm("ic ialluis");

This needs a "memory" clobber to prevent re-ordering by GCC. We should probably check the rest of the code for other occurrences of this too.

Okay.

Quoted 5 lines

arch/arm64/include/asm/cacheflush.h extern void flush_dcache_page(struct page *); · line 119

Quoted 2 lines
arch/arm64/include/asm/cacheflush.h +1 -0
+     dsb();

Can you make a corresponding change for arch/arm/ too, please? I think we're missing the barrier there as well.

I could have, but I don't have hardware to test it on.

Quoted 2 lines

Will

maintainer
#3 lore raw

PATCH 1/1 arm64: add DSB after icache flush in __flush_icache_all()

In reply to Vinayak Kale
Quoted 3 lines · Vinayak Kale

Add DSB after icache flush operation.

Signed-off-by Vinayak Kale <[email protected]>

I think we should also mention that this function is used for user addresses and an ISB is not required because of an exception return before executing user instructions.

Signature · 1 line
Catalin
author
#4 lore raw

PATCH 1/1 arm64: add DSB after icache flush in __flush_icache_all()

Quoted 8 lines · Catalin Marinas
Quoted 3 lines · Vinayak Kale

Add DSB after icache flush operation.

Signed-off-by Vinayak Kale <[email protected]>

I think we should also mention that this function is used for user addresses and an ISB is not required because of an exception return before executing user instructions.

Okay, will mention this. Thanks.

Quoted 3 lines

--
Catalin