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drm/i915: enable HiZ Raw Stall Optimization

PATCH In review Chia-I Wu 4 participants 12 messages Jan 27, 2014 – Jan 30, 2014

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DRM drivers Intel i915
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Chia-I Wu

author
#0 lore raw

PATCH 1/1 drm/i915: enable HiZ Raw Stall Optimization

From: Chia-I Wu <[email protected]>

The optimization is available on Ivy Bridge and later, and is disabled by default. Enabling it helps certain workloads such as GLBenchmark TRex test.

Signed-off-by Chia-I Wu <[email protected]>
Cc Ian Romanick <[email protected]>
Cc Chad Versace <[email protected]>
---
 drivers/gpu/drm/i915/i915_reg.h     | 2 ++
 drivers/gpu/drm/i915/i915_suspend.c | 9 +++++++--
 drivers/gpu/drm/i915/intel_pm.c     | 8 ++++++++
 3 files changed, 17 insertions(+), 2 deletions(-)
drivers/gpu/drm/i915/i915_reg.h +2 -0
index ee27421..bd90ef3 100644
@@ -930,6 +930,8 @@
 #define   ECO_GATING_CX_ONLY	(1<<3)
 #define   ECO_FLIP_DONE		(1<<0)
 
+#define CACHE_MODE_0_GEN7	0x7000 /* IVB+ */
+#define   HIZ_RAW_STALL_OPT_DISABLE (1<<2)
 #define CACHE_MODE_1		0x7004 /* IVB+ */
 #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
drivers/gpu/drm/i915/i915_suspend.c +7 -2
index 98790c7..13fefbd 100644
@@ -398,7 +398,9 @@ int i915_save_state(struct drm_device *dev)
 	intel_disable_gt_powersave(dev);
 
 	/* Cache mode state */
-	if (INTEL_INFO(dev)->gen < 7)
+	if (INTEL_INFO(dev)->gen >= 7)
+		dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0_GEN7);
+	else
 		dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 
 	/* Memory Arbitration state */

@@ -448,7 +450,10 @@ int i915_restore_state(struct drm_device *dev)
 	}
 
 	/* Cache mode state */
-	if (INTEL_INFO(dev)->gen < 7)
+	if (INTEL_INFO(dev)->gen >= 7)
+		I915_WRITE(CACHE_MODE_0_GEN7, dev_priv->regfile.saveCACHE_MODE_0 |
+			   0xffff0000);
+	else
 		I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
 			   0xffff0000);
drivers/gpu/drm/i915/intel_pm.c +8 -0
index 26c29c1..d6ddc39 100644
@@ -5355,6 +5355,10 @@ static void haswell_init_clock_gating(struct drm_device *dev)
 	/* WaVSRefCountFullforceMissDisable:hsw */
 	gen7_setup_fixed_func_scheduler(dev_priv);
 
+	/* enable HiZ Raw Stall Optimization */
+	I915_WRITE(CACHE_MODE_0_GEN7,
+		   _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
+
 	/* WaDisable4x2SubspanOptimization:hsw */
 	I915_WRITE(CACHE_MODE_1,
 		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));

@@ -5445,6 +5449,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 	/* WaVSRefCountFullforceMissDisable:ivb */
 	gen7_setup_fixed_func_scheduler(dev_priv);
 
+	/* enable HiZ Raw Stall Optimization */
+	I915_WRITE(CACHE_MODE_0_GEN7,
+		   _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
+
 	/* WaDisable4x2SubspanOptimization:ivb */
 	I915_WRITE(CACHE_MODE_1,
 		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
Signature · 1 line
1.8.5.3
author
#1 lore raw

[Additional comments, and copy Ian and Chad for real]

Quoted 4 lines · Chia-I Wu

From: Chia-I Wu <[email protected]>

The optimization is available on Ivy Bridge and later, and is disabled by default. Enabling it helps certain workloads such as GLBenchmark TRex test.

With the patch applied, GLB27_TRex_C24Z16_FixedTimeStep goes from 99fps to 109fps on my Haswell, and from 60fps to 65fps on my Ivy Bridge. No piglit regression on both GENs.

I had a non-recoverable system hang once with the patch applied. I was not sure if it is because of the patch or drm-intel-nightly (which I checkout out some weeks ago). I did my tests today against latest drm-intel-next, and did not have any hang. Since the optimization is disabled by default, I am curious if there is any caveat before enabling it.

Quoted 80 lines
Signed-off-by Chia-I Wu <[email protected]>
Cc Ian Romanick <[email protected]>
Cc Chad Versace <[email protected]>
---
 drivers/gpu/drm/i915/i915_reg.h     | 2 ++
 drivers/gpu/drm/i915/i915_suspend.c | 9 +++++++--
 drivers/gpu/drm/i915/intel_pm.c     | 8 ++++++++
 3 files changed, 17 insertions(+), 2 deletions(-)
drivers/gpu/drm/i915/i915_reg.h +2 -0
index ee27421..bd90ef3 100644
@@ -930,6 +930,8 @@
 #define   ECO_GATING_CX_ONLY   (1<<3)
 #define   ECO_FLIP_DONE                (1<<0)
 
+#define CACHE_MODE_0_GEN7      0x7000 /* IVB+ */
+#define   HIZ_RAW_STALL_OPT_DISABLE (1<<2)
 #define CACHE_MODE_1           0x7004 /* IVB+ */
 #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
drivers/gpu/drm/i915/i915_suspend.c +7 -2
index 98790c7..13fefbd 100644
@@ -398,7 +398,9 @@ int i915_save_state(struct drm_device *dev)
        intel_disable_gt_powersave(dev);
 
        /* Cache mode state */
-       if (INTEL_INFO(dev)->gen < 7)
+       if (INTEL_INFO(dev)->gen >= 7)
+               dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0_GEN7);
+       else
                dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 
        /* Memory Arbitration state */

@@ -448,7 +450,10 @@ int i915_restore_state(struct drm_device *dev)
        }
 
        /* Cache mode state */
-       if (INTEL_INFO(dev)->gen < 7)
+       if (INTEL_INFO(dev)->gen >= 7)
+               I915_WRITE(CACHE_MODE_0_GEN7, dev_priv->regfile.saveCACHE_MODE_0 |
+                          0xffff0000);
+       else
                I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
                           0xffff0000);
drivers/gpu/drm/i915/intel_pm.c +8 -1
index 26c29c1..d6ddc39 100644
@@ -5355,6 +5355,10 @@ static void haswell_init_clock_gating(struct drm_device *dev)
        /* WaVSRefCountFullforceMissDisable:hsw */
        gen7_setup_fixed_func_scheduler(dev_priv);
 
+       /* enable HiZ Raw Stall Optimization */
+       I915_WRITE(CACHE_MODE_0_GEN7,
+                  _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
+
        /* WaDisable4x2SubspanOptimization:hsw */
        I915_WRITE(CACHE_MODE_1,
                   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));

@@ -5445,6 +5449,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
        /* WaVSRefCountFullforceMissDisable:ivb */
        gen7_setup_fixed_func_scheduler(dev_priv);
 
+       /* enable HiZ Raw Stall Optimization */
+       I915_WRITE(CACHE_MODE_0_GEN7,
+                  _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
+
        /* WaDisable4x2SubspanOptimization:ivb */
        I915_WRITE(CACHE_MODE_1,
                   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
--

1.8.5.3

Signature · 1 line
[email protected]
#2 lore raw
Quoted 11 lines · Chia-I Wu

[Additional comments, and copy Ian and Chad for real]

Quoted 4 lines · Chia-I Wu

From: Chia-I Wu <[email protected]>

The optimization is available on Ivy Bridge and later, and is disabled by default. Enabling it helps certain workloads such as GLBenchmark TRex test.

With the patch applied, GLB27_TRex_C24Z16_FixedTimeStep goes from 99fps to 109fps on my Haswell, and from 60fps to 65fps on my Ivy Bridge. No piglit regression on both GENs.

Quoted 6 lines

I had a non-recoverable system hang once with the patch applied. I was not sure if it is because of the patch or drm-intel-nightly (which I checkout out some weeks ago). I did my tests today against latest drm-intel-next, and did not have any hang. Since the optimization is disabled by default, I am curious if there is any caveat before enabling it.

Chad's still missing ;-) Also the hang might just be ppgtt fallout, there's still a few regressions with that.
-Daniel

Signature · 3 lines
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
#3 lore raw
In reply to Chia-I Wu
Quoted 4 lines · Chia-I Wu

From: Chia-I Wu <[email protected]>

The optimization is available on Ivy Bridge and later, and is disabled by default. Enabling it helps certain workloads such as GLBenchmark TRex test.

Actually BSpec even goes as far as saying that this optimization must be enabled on HSW+.

So it seems you should enable it for BDW as well. I'm not sure about VLV. The description of the bit says nothing about VLV, even though the documented default value is specified to have it set for VLV as well. I guess someone should just try it and see what happens.

Might make sense to split the patch into per-platforms patches. That way we could more easily revert eg. just the IVB part if it causes problems.

Quoted 40 lines
Signed-off-by Chia-I Wu <[email protected]>
Cc Ian Romanick <[email protected]>
Cc Chad Versace <[email protected]>
---
 drivers/gpu/drm/i915/i915_reg.h     | 2 ++
 drivers/gpu/drm/i915/i915_suspend.c | 9 +++++++--
 drivers/gpu/drm/i915/intel_pm.c     | 8 ++++++++
 3 files changed, 17 insertions(+), 2 deletions(-)
drivers/gpu/drm/i915/i915_reg.h +2 -0
index ee27421..bd90ef3 100644
@@ -930,6 +930,8 @@
 #define   ECO_GATING_CX_ONLY	(1<<3)
 #define   ECO_FLIP_DONE		(1<<0)
 
+#define CACHE_MODE_0_GEN7	0x7000 /* IVB+ */
+#define   HIZ_RAW_STALL_OPT_DISABLE (1<<2)
 #define CACHE_MODE_1		0x7004 /* IVB+ */
 #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
drivers/gpu/drm/i915/i915_suspend.c +3 -1
index 98790c7..13fefbd 100644
@@ -398,7 +398,9 @@ int i915_save_state(struct drm_device *dev)
 	intel_disable_gt_powersave(dev);
 
 	/* Cache mode state */
-	if (INTEL_INFO(dev)->gen < 7)
+	if (INTEL_INFO(dev)->gen >= 7)
+		dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0_GEN7);
+	else
 		dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 
 	/* Memory Arbitration state */

drivers/gpu/drm/i915/i915_suspend.c int i915_restore_state(struct drm_device *dev) · line 458

Quoted 10 lines
drivers/gpu/drm/i915/i915_suspend.c +4 -1
@@ -448,7 +450,10 @@ int i915_restore_state(struct drm_device *dev)
 	}
 
 	/* Cache mode state */
-	if (INTEL_INFO(dev)->gen < 7)
+	if (INTEL_INFO(dev)->gen >= 7)
+		I915_WRITE(CACHE_MODE_0_GEN7, dev_priv->regfile.saveCACHE_MODE_0 |
+			   0xffff0000);
+	else
 		I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
 			   0xffff0000);

These hunks are material for a separate patch.

Quoted 34 lines
drivers/gpu/drm/i915/intel_pm.c +8 -0
index 26c29c1..d6ddc39 100644
@@ -5355,6 +5355,10 @@ static void haswell_init_clock_gating(struct drm_device *dev)
 	/* WaVSRefCountFullforceMissDisable:hsw */
 	gen7_setup_fixed_func_scheduler(dev_priv);
 
+	/* enable HiZ Raw Stall Optimization */
+	I915_WRITE(CACHE_MODE_0_GEN7,
+		   _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
+
 	/* WaDisable4x2SubspanOptimization:hsw */
 	I915_WRITE(CACHE_MODE_1,
 		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));

@@ -5445,6 +5449,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 	/* WaVSRefCountFullforceMissDisable:ivb */
 	gen7_setup_fixed_func_scheduler(dev_priv);
 
+	/* enable HiZ Raw Stall Optimization */
+	I915_WRITE(CACHE_MODE_0_GEN7,
+		   _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
+
 	/* WaDisable4x2SubspanOptimization:ivb */
 	I915_WRITE(CACHE_MODE_1,
 		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
Signature · 6 lines
1.8.5.3

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Signature · 2 lines
Ville Syrjälä
Intel OTC
#4 lore raw
Quoted 59 lines · Ville Syrjälä
Quoted 4 lines · Chia-I Wu

From: Chia-I Wu <[email protected]>

The optimization is available on Ivy Bridge and later, and is disabled by default. Enabling it helps certain workloads such as GLBenchmark TRex test.

Actually BSpec even goes as far as saying that this optimization must be enabled on HSW+.

So it seems you should enable it for BDW as well. I'm not sure about VLV. The description of the bit says nothing about VLV, even though the documented default value is specified to have it set for VLV as well. I guess someone should just try it and see what happens.

Might make sense to split the patch into per-platforms patches. That way we could more easily revert eg. just the IVB part if it causes problems.

Quoted 42 lines
Signed-off-by Chia-I Wu <[email protected]>
Cc Ian Romanick <[email protected]>
Cc Chad Versace <[email protected]>
---
 drivers/gpu/drm/i915/i915_reg.h     | 2 ++
 drivers/gpu/drm/i915/i915_suspend.c | 9 +++++++--
 drivers/gpu/drm/i915/intel_pm.c     | 8 ++++++++
 3 files changed, 17 insertions(+), 2 deletions(-)
drivers/gpu/drm/i915/i915_reg.h +2 -0
index ee27421..bd90ef3 100644
@@ -930,6 +930,8 @@
 #define   ECO_GATING_CX_ONLY	(1<<3)
 #define   ECO_FLIP_DONE		(1<<0)
 
+#define CACHE_MODE_0_GEN7	0x7000 /* IVB+ */
+#define   HIZ_RAW_STALL_OPT_DISABLE (1<<2)
 #define CACHE_MODE_1		0x7004 /* IVB+ */
 #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
drivers/gpu/drm/i915/i915_suspend.c +3 -1
index 98790c7..13fefbd 100644
@@ -398,7 +398,9 @@ int i915_save_state(struct drm_device *dev)
 	intel_disable_gt_powersave(dev);
 
 	/* Cache mode state */
-	if (INTEL_INFO(dev)->gen < 7)
+	if (INTEL_INFO(dev)->gen >= 7)
+		dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0_GEN7);
+	else
 		dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 
 	/* Memory Arbitration state */

@@ -448,7 +450,10 @@ int i915_restore_state(struct drm_device *dev)
 	}
Quoted 10 lines

drivers/gpu/drm/i915/i915_suspend.c int i915_restore_state(struct drm_device *dev) · line 458

Quoted 8 lines
drivers/gpu/drm/i915/i915_suspend.c +4 -1
 	/* Cache mode state */
-	if (INTEL_INFO(dev)->gen < 7)
+	if (INTEL_INFO(dev)->gen >= 7)
+		I915_WRITE(CACHE_MODE_0_GEN7, dev_priv->regfile.saveCACHE_MODE_0 |
+			   0xffff0000);
+	else
 		I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
 			   0xffff0000);

These hunks are material for a separate patch.

Also they shouldn't be required. On all modern platforms our setup code (init_clock_gating callback) which runs both at driver load time and resume time should take care of all these bits and registers. If we miss some of them, we need to add them. So please drop this hunk for v2. -Daniel

Quoted 43 lines
Quoted 35 lines
drivers/gpu/drm/i915/intel_pm.c +8 -0
index 26c29c1..d6ddc39 100644
@@ -5355,6 +5355,10 @@ static void haswell_init_clock_gating(struct drm_device *dev)
 	/* WaVSRefCountFullforceMissDisable:hsw */
 	gen7_setup_fixed_func_scheduler(dev_priv);
 
+	/* enable HiZ Raw Stall Optimization */
+	I915_WRITE(CACHE_MODE_0_GEN7,
+		   _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
+
 	/* WaDisable4x2SubspanOptimization:hsw */
 	I915_WRITE(CACHE_MODE_1,
 		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));

@@ -5445,6 +5449,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 	/* WaVSRefCountFullforceMissDisable:ivb */
 	gen7_setup_fixed_func_scheduler(dev_priv);
 
+	/* enable HiZ Raw Stall Optimization */
+	I915_WRITE(CACHE_MODE_0_GEN7,
+		   _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
+
 	/* WaDisable4x2SubspanOptimization:ivb */
 	I915_WRITE(CACHE_MODE_1,
 		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
Signature · 6 lines
1.8.5.3

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Signature · 6 lines
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Signature · 3 lines
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
author
#5 lore raw
In reply to Ville Syrjälä
Quoted 8 lines · Ville Syrjälä
Quoted 4 lines · Chia-I Wu

From: Chia-I Wu <[email protected]>

The optimization is available on Ivy Bridge and later, and is disabled by default. Enabling it helps certain workloads such as GLBenchmark TRex test.

Actually BSpec even goes as far as saying that this optimization must be enabled on HSW+.

The public documentation actually says if you want the optimization, you must enable it. Kind of stating the obvious. :)

Quoted 7 lines

So it seems you should enable it for BDW as well. I'm not sure about VLV. The description of the bit says nothing about VLV, even though the documented default value is specified to have it set for VLV as well. I guess someone should just try it and see what happens.

Might make sense to split the patch into per-platforms patches. That way we could more easily revert eg. just the IVB part if it causes problems.

Will do. Though I will leave BDW/VLV out as I do not have the hardware.

Quoted 91 lines
Quoted 40 lines
Signed-off-by Chia-I Wu <[email protected]>
Cc Ian Romanick <[email protected]>
Cc Chad Versace <[email protected]>
---
 drivers/gpu/drm/i915/i915_reg.h     | 2 ++
 drivers/gpu/drm/i915/i915_suspend.c | 9 +++++++--
 drivers/gpu/drm/i915/intel_pm.c     | 8 ++++++++
 3 files changed, 17 insertions(+), 2 deletions(-)
drivers/gpu/drm/i915/i915_reg.h +2 -0
index ee27421..bd90ef3 100644
@@ -930,6 +930,8 @@
 #define   ECO_GATING_CX_ONLY (1<<3)
 #define   ECO_FLIP_DONE              (1<<0)
 
+#define CACHE_MODE_0_GEN7    0x7000 /* IVB+ */
+#define   HIZ_RAW_STALL_OPT_DISABLE (1<<2)
 #define CACHE_MODE_1         0x7004 /* IVB+ */
 #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
drivers/gpu/drm/i915/i915_suspend.c +3 -1
index 98790c7..13fefbd 100644
@@ -398,7 +398,9 @@ int i915_save_state(struct drm_device *dev)
      intel_disable_gt_powersave(dev);
 
      /* Cache mode state */
-     if (INTEL_INFO(dev)->gen < 7)
+     if (INTEL_INFO(dev)->gen >= 7)
+             dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0_GEN7);
+     else
              dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 
      /* Memory Arbitration state */

drivers/gpu/drm/i915/i915_suspend.c int i915_restore_state(struct drm_device *dev) · line 458

Quoted 10 lines
drivers/gpu/drm/i915/i915_suspend.c +4 -1
@@ -448,7 +450,10 @@ int i915_restore_state(struct drm_device *dev)
      }
 
      /* Cache mode state */
-     if (INTEL_INFO(dev)->gen < 7)
+     if (INTEL_INFO(dev)->gen >= 7)
+             I915_WRITE(CACHE_MODE_0_GEN7, dev_priv->regfile.saveCACHE_MODE_0 |
+                        0xffff0000);
+     else
              I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
                         0xffff0000);

These hunks are material for a separate patch.

Quoted 30 lines
drivers/gpu/drm/i915/intel_pm.c +8 -1
index 26c29c1..d6ddc39 100644
@@ -5355,6 +5355,10 @@ static void haswell_init_clock_gating(struct drm_device *dev)
      /* WaVSRefCountFullforceMissDisable:hsw */
      gen7_setup_fixed_func_scheduler(dev_priv);
 
+     /* enable HiZ Raw Stall Optimization */
+     I915_WRITE(CACHE_MODE_0_GEN7,
+                _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
+
      /* WaDisable4x2SubspanOptimization:hsw */
      I915_WRITE(CACHE_MODE_1,
                 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));

@@ -5445,6 +5449,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
      /* WaVSRefCountFullforceMissDisable:ivb */
      gen7_setup_fixed_func_scheduler(dev_priv);
 
+     /* enable HiZ Raw Stall Optimization */
+     I915_WRITE(CACHE_MODE_0_GEN7,
+                _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
+
      /* WaDisable4x2SubspanOptimization:ivb */
      I915_WRITE(CACHE_MODE_1,
                 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
--

1.8.5.3

Quoted 4 lines

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

--
Ville Syrjälä
Intel OTC

Signature · 5 lines
[email protected]
_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
author
#6 lore raw

PATCH 1/2 drm/i915: enable HiZ Raw Stall Optimization on HSW

In reply to Chia-I Wu

From: Chia-I Wu <[email protected]>

The optimization is available on Ivy Bridge and later, and is disabled by default. Enabling it helps certain workloads such as GLBenchmark TRex test.

No piglit regression.

v2
- no need to save the register before suspend as init_clock_gating can correctly program it after resume
- split IVB change to another commit

Signed-off-by Chia-I Wu <[email protected]>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 ++
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 2 files changed, 6 insertions(+)
drivers/gpu/drm/i915/i915_reg.h +2 -0
index 76126e0..c74bc28 100644
@@ -934,6 +934,8 @@
 #define   ECO_GATING_CX_ONLY	(1<<3)
 #define   ECO_FLIP_DONE		(1<<0)
 
+#define CACHE_MODE_0_GEN7	0x7000 /* IVB+ */
+#define   HIZ_RAW_STALL_OPT_DISABLE (1<<2)
 #define CACHE_MODE_1		0x7004 /* IVB+ */
 #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
drivers/gpu/drm/i915/intel_pm.c +4 -0
index d77cc81..c535e5c 100644
@@ -4789,6 +4789,10 @@ static void haswell_init_clock_gating(struct drm_device *dev)
 	/* WaVSRefCountFullforceMissDisable:hsw */
 	gen7_setup_fixed_func_scheduler(dev_priv);
 
+	/* enable HiZ Raw Stall Optimization */
+	I915_WRITE(CACHE_MODE_0_GEN7,
+		   _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
+
 	/* WaDisable4x2SubspanOptimization:hsw */
 	I915_WRITE(CACHE_MODE_1,
 		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
Signature · 1 line
1.8.3.1
author
#7 lore raw

PATCH 2/2 drm/i915: enable HiZ Raw Stall Optimization on IVB

From: Chia-I Wu <[email protected]>

The optimization helps IVB too. No piglit regression.

Signed-off-by Chia-I Wu <[email protected]>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 1 file changed, 4 insertions(+)
drivers/gpu/drm/i915/intel_pm.c +4 -0
index c535e5c..58aba3e 100644
@@ -4881,6 +4881,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 	/* WaVSRefCountFullforceMissDisable:ivb */
 	gen7_setup_fixed_func_scheduler(dev_priv);
 
+	/* enable HiZ Raw Stall Optimization */
+	I915_WRITE(CACHE_MODE_0_GEN7,
+		   _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
+
 	/* WaDisable4x2SubspanOptimization:ivb */
 	I915_WRITE(CACHE_MODE_1,
 		   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
Signature · 1 line
1.8.3.1
#8 lore raw

Re: [PATCH 1/2] drm/i915: enable HiZ Raw Stall Optimization on HSW

In reply to Chia-I Wu
Quoted 5 lines · Chia-I Wu

From: Chia-I Wu <[email protected]>

The optimization is available on Ivy Bridge and later, and is disabled by default. Enabling it helps certain workloads such as GLBenchmark TRex test.

Quoted 8 lines

No piglit regression.

v2
- no need to save the register before suspend as init_clock_gating can correctly program it after resume
- split IVB change to another commit

Signed-off-by Chia-I Wu <[email protected]>

What about byt?
-Daniel

Signature · 3 lines
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
#9 lore raw

Re: [PATCH 1/2] drm/i915: enable HiZ Raw Stall Optimization on HSW

Quoted 13 lines · Daniel Vetter
Quoted 12 lines · Chia-I Wu

From: Chia-I Wu <[email protected]>

The optimization is available on Ivy Bridge and later, and is disabled by default. Enabling it helps certain workloads such as GLBenchmark TRex test.

No piglit regression.

v2
- no need to save the register before suspend as init_clock_gating can correctly program it after resume
- split IVB change to another commit

Quoted 4 lines
Quoted 1 line
Signed-off-by Chia-I Wu <[email protected]>

What about byt?
-Daniel

In the previous thread, Ville pointed out that the documentation doesn't say anything about BYT for this bit, so it's unknown whether it's supported, and Chia-I said

Quoted 1 line

Though I will leave BDW/VLV out as I do not have the hardware.

I do have BYT, so I'll check it out, but this patch can go in without it that information, since Chia-I took Ville's advice and split the patches into per-generation hunks.

#10 lore raw

Re: [PATCH 1/2] drm/i915: enable HiZ Raw Stall Optimization on HSW

Quoted 23 lines · Matt Turner
Quoted 13 lines · Daniel Vetter
Quoted 12 lines · Chia-I Wu

From: Chia-I Wu <[email protected]>

The optimization is available on Ivy Bridge and later, and is disabled by default. Enabling it helps certain workloads such as GLBenchmark TRex test.

No piglit regression.

v2
- no need to save the register before suspend as init_clock_gating can correctly program it after resume
- split IVB change to another commit

Quoted 4 lines
Quoted 1 line
Signed-off-by Chia-I Wu <[email protected]>

What about byt?
-Daniel

In the previous thread, Ville pointed out that the documentation doesn't say anything about BYT for this bit, so it's unknown whether it's supported, and Chia-I said

Quoted 5 lines
Quoted 1 line

Though I will leave BDW/VLV out as I do not have the hardware.

I do have BYT, so I'll check it out, but this patch can go in without it that information, since Chia-I took Ville's advice and split the patches into per-generation hunks.

Make sense. Patches merged and I'll happily pull in the byt update if that one checks out ok.
-Daniel

Signature · 3 lines
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
#11 lore raw

Re: [PATCH 1/2] drm/i915: enable HiZ Raw Stall Optimization on HSW

Quoted 24 lines · Daniel Vetter
Quoted 23 lines · Matt Turner
Quoted 13 lines · Daniel Vetter
Quoted 12 lines · Chia-I Wu

From: Chia-I Wu <[email protected]>

The optimization is available on Ivy Bridge and later, and is disabled by default. Enabling it helps certain workloads such as GLBenchmark TRex test.

No piglit regression.

v2
- no need to save the register before suspend as init_clock_gating can correctly program it after resume
- split IVB change to another commit

Quoted 4 lines
Quoted 1 line
Signed-off-by Chia-I Wu <[email protected]>

What about byt?
-Daniel

In the previous thread, Ville pointed out that the documentation doesn't say anything about BYT for this bit, so it's unknown whether it's supported, and Chia-I said

Quoted 8 lines
Quoted 5 lines
Quoted 1 line

Though I will leave BDW/VLV out as I do not have the hardware.

I do have BYT, so I'll check it out, but this patch can go in without it that information, since Chia-I took Ville's advice and split the patches into per-generation hunks.

Make sense. Patches merged and I'll happily pull in the byt update if that one checks out ok.

and bdw also needs this (bspec says hsw+)

Signature · 2 lines
Ville Syrjälä
Intel OTC