clk: shmobile rcar-gen2 fixes
Subsystems (3)
cover clk: shmobile rcar-gen2 fixes
Hello,
These two patches fix the clock parents and qspi clock divisor in the rcar-gen2 clock driver.
Geert, could you please verify that the series fixes your QSPI clock issues with the Koelsch board ?
Laurent Pinchart (2):
clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocks
clk: shmobile: rcar-gen2: Fix qspi divisor
drivers/clk/shmobile/clk-rcar-gen2.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)
Signature · 3 lines
Regards, Laurent Pinchart
PATCH 1/2 clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocks
The lb, qspi, sdh, sd0 and sd1 clocks have the PLL1 (divided by 2) as their parent, not the main clock. Fix it.
--- drivers/clk/shmobile/clk-rcar-gen2.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)
drivers/clk/shmobile/clk-rcar-gen2.c +9 -1
@@ -186,7 +186,7 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg, const char *name) {const struct clk_div_table *table =NULL ; -const char *parent_name ="main" ; +const char *parent_name;unsigned int shift;unsigned int mult =1 ;unsigned int div =1 ;
@@ -201,23 +201,31 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,* the multiplier value. */ u32 value =clk_readl (cpg->reg +CPG_PLL0CR ); + parent_name ="main" ; mult = ((value >>24 ) & ((1 <<7 ) -1 )) +1 ; }else if (!strcmp (name,"pll1" )) { + parent_name ="main" ; mult = config->pll1_mult /2 ; }else if (!strcmp (name,"pll3" )) { + parent_name ="main" ; mult = config->pll3_mult; }else if (!strcmp (name,"lb" )) { + parent_name ="pll1_div2" ; div = cpg_mode &BIT (18 ) ?36 :24 ; }else if (!strcmp (name,"qspi" )) { + parent_name ="pll1_div2" ; div = (cpg_mode & (BIT (3 ) |BIT (2 ) |BIT (1 ))) ==BIT (2 ) ?16 :20 ; }else if (!strcmp (name,"sdh" )) { + parent_name ="pll1_div2" ; table = cpg_sdh_div_table; shift =8 ; }else if (!strcmp (name,"sd0" )) { + parent_name ="pll1_div2" ; table = cpg_sd01_div_table; shift =4 ; }else if (!strcmp (name,"sd1" )) { + parent_name ="pll1_div2" ; table = cpg_sd01_div_table; shift =0 ; }else if (!strcmp (name,"z" )) {
Signature · 1 line
1.8.3.2
PATCH 1/2 clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocks
Quoted 2 lines · Laurent Pinchart
The lb, qspi, sdh, sd0 and sd1 clocks have the PLL1 (divided by 2) as their parent, not the main clock. Fix it.
William Towle has already sent a patch to move this to device tree which I think is a better solution for this. Any chance of commenting on which to take please.
Quoted 52 lines
Reported-by Geert Uytterhoeven <[email protected]>Signed-off-by Laurent Pinchart <[email protected]>--- drivers/clk/shmobile/clk-rcar-gen2.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)drivers/clk/shmobile/clk-rcar-gen2.c +9
-1@@ -186,7 +186,7 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg, const char *name) {const struct clk_div_table *table =NULL ; -const char *parent_name ="main" ; +const char *parent_name;unsigned int shift;unsigned int mult =1 ;unsigned int div =1 ;@@ -201,23 +201,31 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,* the multiplier value. */ u32 value =clk_readl (cpg->reg +CPG_PLL0CR ); + parent_name ="main" ; mult = ((value >>24 ) & ((1 <<7 ) -1 )) +1 ; }else if (!strcmp (name,"pll1" )) { + parent_name ="main" ; mult = config->pll1_mult /2 ; }else if (!strcmp (name,"pll3" )) { + parent_name ="main" ; mult = config->pll3_mult; }else if (!strcmp (name,"lb" )) { + parent_name ="pll1_div2" ; div = cpg_mode &BIT (18 ) ?36 :24 ; }else if (!strcmp (name,"qspi" )) { + parent_name ="pll1_div2" ; div = (cpg_mode & (BIT (3 ) |BIT (2 ) |BIT (1 ))) ==BIT (2 ) ?16 :20 ; }else if (!strcmp (name,"sdh" )) { + parent_name ="pll1_div2" ; table = cpg_sdh_div_table; shift =8 ; }else if (!strcmp (name,"sd0" )) { + parent_name ="pll1_div2" ; table = cpg_sd01_div_table; shift =4 ; }else if (!strcmp (name,"sd1" )) { + parent_name ="pll1_div2" ; table = cpg_sd01_div_table; shift =0 ; }else if (!strcmp (name,"z" )) {
Signature · 2 lines
Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius
PATCH 1/2 clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocks
Hi Ben,
Quoted 6 lines · On Wednesday 05 February 2014 10:34:49 Ben Dooks wrote:
Quoted 2 lines · Laurent Pinchart
The lb, qspi, sdh, sd0 and sd1 clocks have the PLL1 (divided by 2) as their parent, not the main clock. Fix it.
William Towle has already sent a patch to move this to device tree which I think is a better solution for this.
I actually disagree. The CPG is an IP core that generates a bunch of clocks from a single external parent. The fact that clocks are not flat but organized as a tree internally is an internal property of the CPG, and I prefer keeping it that way instead of exposing it in the device tree.
Quoted 57 lines
Any chance of commenting on which to take please.
Quoted 55 lines
Reported-by Geert Uytterhoeven <[email protected]>Signed-off-by Laurent Pinchart<[email protected]>
---drivers/clk/shmobile/clk-rcar-gen2.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)(quoted diff) +0
-0
b/drivers/clk/shmobile/clk-rcar-gen2.cindex a59ec21..8c7bcbd 100644drivers/clk/shmobile/clk-rcar-gen2.c +0
-0@@ -186,7 +186,7 @@ rcar_gen2_cpg_register_clock(struct device_node *np,struct
rcar_gen2_cpg*cpg,>
const char *name)
{
const structclk_div_table*table = NULL;drivers/clk/shmobile/clk-rcar-gen2.c +1
-1-const char *parent_name ="main" ; +const char *parent_name;unsigned int shift;unsigned int mult =1 ;unsigned int div =1 ;@@ -201,23 +201,31 @@ rcar_gen2_cpg_register_clock(struct device_node *np,struct
rcar_gen2_cpg*cpg,>
* the multiplier value.
*/
u32 value =clk_readl(cpg->reg + CPG_PLL0CR);drivers/clk/shmobile/clk-rcar-gen2.c +8
-0+ parent_name ="main" ; mult = ((value >>24 ) & ((1 <<7 ) -1 )) +1 ; }else if (!strcmp (name,"pll1" )) { + parent_name ="main" ; mult = config->pll1_mult /2 ; }else if (!strcmp (name,"pll3" )) { + parent_name ="main" ; mult = config->pll3_mult; }else if (!strcmp (name,"lb" )) { + parent_name ="pll1_div2" ; div = cpg_mode &BIT (18 ) ?36 :24 ; }else if (!strcmp (name,"qspi" )) { + parent_name ="pll1_div2" ; div = (cpg_mode & (BIT (3 ) |BIT (2 ) |BIT (1 ))) ==BIT (2 ) ?16 :20 ; }else if (!strcmp (name,"sdh" )) { + parent_name ="pll1_div2" ; table = cpg_sdh_div_table; shift =8 ; }else if (!strcmp (name,"sd0" )) { + parent_name ="pll1_div2" ; table = cpg_sd01_div_table; shift =4 ; }else if (!strcmp (name,"sd1" )) { + parent_name ="pll1_div2" ; table = cpg_sd01_div_table; shift =0 ; }else if (!strcmp (name,"z" )) {
Signature · 3 lines
Regards, Laurent Pinchart
PATCH 1/2 clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocks
Quoted 7 lines · Laurent Pinchart
Hi Ben,
Quoted 4 lines · On Wednesday 05 February 2014 10:34:49 Ben Dooks wrote:
Quoted 2 lines · Laurent Pinchart
The lb, qspi, sdh, sd0 and sd1 clocks have the PLL1 (divided by 2) as their parent, not the main clock. Fix it.
Quoted 7 lines
Quoted 2 lines
William Towle has already sent a patch to move this to device tree which I think is a better solution for this.
I actually disagree. The CPG is an IP core that generates a bunch of clocks from a single external parent. The fact that clocks are not flat but organized as a tree internally is an internal property of the CPG, and I prefer keeping it that way instead of exposing it in the device tree.
If you feel that the block is unlikely to change if it gets re-used then that'll be fine. We can always revisit the changes if needed.
Signature · 2 lines
Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius
PATCH 2/2 clk: shmobile: rcar-gen2: Fix qspi divisor
In reply to Laurent PinchartThe qspi clock divisor is incorrectly set to twice the value it should have, possibly because it has been computed based on PLL1 as the clock parent instead of PLL1 / 2 (the datasheets specifies the qspi nominal frequencies, not the divisor values). Fix it.
--- drivers/clk/shmobile/clk-rcar-gen2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/shmobile/clk-rcar-gen2.c +1 -1
@@ -215,7 +215,7 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg, }else if (!strcmp (name,"qspi" )) { parent_name ="pll1_div2" ; div = (cpg_mode & (BIT (3 ) |BIT (2 ) |BIT (1 ))) ==BIT (2 ) - ?16 :20 ; + ?8 :10 ; }else if (!strcmp (name,"sdh" )) { parent_name ="pll1_div2" ; table = cpg_sdh_div_table;
Signature · 1 line
1.8.3.2
cover clk: shmobile rcar-gen2 fixes
In reply to Laurent PinchartQuoted 6 lines · Laurent Pinchart
Geert, could you please verify that the series fixes your QSPI clock issues with the Koelsch board ?
Laurent Pinchart (2):
clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocks
clk: shmobile: rcar-gen2: Fix qspi divisor
Thanks, both:
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
cover clk: shmobile rcar-gen2 fixes
Hi Geert,
Quoted 11 lines · On Tuesday 07 January 2014 17:59:01 Geert Uytterhoeven wrote:
Quoted 6 lines · Laurent Pinchart
Geert, could you please verify that the series fixes your QSPI clock issues with the Koelsch board ?
Laurent Pinchart (2):
clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocks
clk: shmobile: rcar-gen2: Fix qspi divisorThanks, both:
Tested-by Geert Uytterhoeven <[email protected]>
Thank you.
Mike, could you please pick those patches up for v3.14 ?
Signature · 3 lines
Regards, Laurent Pinchart
cover clk: shmobile rcar-gen2 fixes
Hi Mike,
Quoted 9 lines · On Wednesday 08 January 2014 00:06:39 Laurent Pinchart wrote:
Quoted 8 lines · On Tuesday 07 January 2014 17:59:01 Geert Uytterhoeven wrote:
Quoted 6 lines · Laurent Pinchart
Geert, could you please verify that the series fixes your QSPI clock issues with the Koelsch board ?
Laurent Pinchart (2):
clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocks
clk: shmobile: rcar-gen2: Fix qspi divisor
Quoted 7 lines
Quoted 3 lines
Thanks, both:
Tested-by Geert Uytterhoeven <[email protected]>Thank you.
Mike, could you please pick those patches up for v3.14 ?
Ping ?
Signature · 3 lines
Regards, Laurent Pinchart
cover clk: shmobile rcar-gen2 fixes
Quoting Laurent Pinchart (2014-01-21 05:00:28)
Quoted 14 lines
Hi Mike,
Quoted 11 lines · On Wednesday 08 January 2014 00:06:39 Laurent Pinchart wrote:
Quoted 10 lines · On Tuesday 07 January 2014 17:59:01 Geert Uytterhoeven wrote:
Quoted 6 lines · Laurent Pinchart
Geert, could you please verify that the series fixes your QSPI clock issues with the Koelsch board ?
Laurent Pinchart (2):
clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocks
clk: shmobile: rcar-gen2: Fix qspi divisorThanks, both:
Quoted 7 lines
Quoted 5 lines
Quoted 1 line
Tested-by Geert Uytterhoeven <[email protected]>Thank you.
Mike, could you please pick those patches up for v3.14 ?
Ping ?
Hi Laurent,
I'll send these as part of my fixes tag, probably next week.
Regards,
Mike
Quoted 6 lines
Signature · 4 lines
-- Regards, Laurent Pinchart
cover clk: shmobile rcar-gen2 fixes
In reply to Laurent PinchartMike,
Ping ?
v3.14-rc1 is out, and those are bug fixes.
Quoted 16 lines · On Wednesday 08 January 2014 00:06:39 Laurent Pinchart wrote:
Quoted 11 lines · On Tuesday 07 January 2014 17:59:01 Geert Uytterhoeven wrote:
Quoted 6 lines · Laurent Pinchart
Geert, could you please verify that the series fixes your QSPI clock issues with the Koelsch board ?
Laurent Pinchart (2):
clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocks
clk: shmobile: rcar-gen2: Fix qspi divisorThanks, both:
Tested-by Geert Uytterhoeven <[email protected]>Thank you.
Mike, could you please pick those patches up for v3.14 ?
Signature · 3 lines
Regards, Laurent Pinchart
cover clk: shmobile rcar-gen2 fixes
Quoting Laurent Pinchart (2014-02-05 02:31:41)
Quoted 23 lines
Mike,
Ping ?
v3.14-rc1 is out, and those are bug fixes.
Quoted 16 lines · On Wednesday 08 January 2014 00:06:39 Laurent Pinchart wrote:
Quoted 11 lines · On Tuesday 07 January 2014 17:59:01 Geert Uytterhoeven wrote:
Quoted 6 lines · Laurent Pinchart
Geert, could you please verify that the series fixes your QSPI clock issues with the Koelsch board ?
Laurent Pinchart (2):
clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocks
clk: shmobile: rcar-gen2: Fix qspi divisorThanks, both:
Tested-by Geert Uytterhoeven <[email protected]>Thank you.
Mike, could you please pick those patches up for v3.14 ?
Taken into clk-fixes.
Thanks!
Mike
Quoted 6 lines
Signature · 4 lines
-- Regards, Laurent Pinchart
cover clk: shmobile rcar-gen2 fixes
In reply to Geert UytterhoevenQuoted 5 lines · Geert Uytterhoeven
Quoted 3 lines · Laurent Pinchart
Geert, could you please verify that the series fixes your QSPI clock issues with the Koelsch board ?
Quoted 7 lines
Quoted 3 lines
Laurent Pinchart (2):
clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocks
clk: shmobile: rcar-gen2: Fix qspi divisorThanks, both:
Tested-by Geert Uytterhoeven <[email protected]>