Add support for Keystone2 SoC and K2HK EVM

From: Vitaly Andrianov <[email protected]>

The keystone2 SOC requires to fix all 32 bit aliased addresses to their 36 physical format. This has to happen after all fdt nodes are added or modified.

Signed-off-by Vitaly Andrianov <[email protected]>

Quoted 2 lines · Murali Karicheri

From: Vitaly Andrianov <[email protected]>

Quoted 5 lines

The keystone2 SOC requires to fix all 32 bit aliased addresses to their 36 physical format. This has to happen after all fdt nodes are added or modified.

Signed-off-by Vitaly Andrianov <[email protected]>

Why can't this be done with the existing CONFIG_OF_BOARD_SETUP and 'fdt boardsetup' command?

k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer the ti/k2hk_evm/README for details on the board, build and other information.

This patch add support for keystone architecture and k2hk evm.

+++ b/arch/arm/cpu/armv7/keystone/Makefile

arch/arm/cpu/armv7/keystone/Makefile new file +7 -0

@@ -0,0 +1,18 @@
+#
+# (C) Copyright 2012-2014
+#     Texas Instruments Incorporated, <www.ti.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+

arch/arm/cpu/armv7/keystone/aemif.c new file +7 -0

+++ b/arch/arm/cpu/armv7/keystone/aemif.c

@@ -0,0 +1,79 @@
+/*
+ * Keystone2: Asynchronous EMIF Configuration
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *

(quoted diff) +1 -0

+++ b/arch/arm/cpu/armv7/keystone/clock-k2hk.c

+++ b/arch/arm/cpu/armv7/keystone/clock.c

+#include "clock-k2hk.c"

+++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c

arch/arm/cpu/armv7/keystone/cmd_clock.c new file +45 -0

@@ -0,0 +1,139 @@
+/*
+ * keystone2: commands for clocks
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/psc_defs.h>
+
+static u32 atoui(char *pstr)
+{
+	u32 res = 0;
+
+	for (; *pstr != 0; pstr++) {
+		if (*pstr < '0' || *pstr > '9')
+			break;
+
+		res = (res * 10) + (*pstr - '0');
+	}
+
+	return res;
+}
+
+struct pll_init_data cmd_pll_data = {
+	.pll			= MAIN_PLL,
+	.pll_m			= 16,
+	.pll_d			= 1,
+	.pll_od			= 2,
+};
+
+int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc != 5)
+		goto pll_cmd_usage;
+
+	if (strncmp(argv[1], "pa", 2) == 0)
+		cmd_pll_data.pll = PASS_PLL;
+	else if (strncmp(argv[1], "arm", 3) == 0)
+		cmd_pll_data.pll = TETRIS_PLL;

arch/arm/cpu/armv7/keystone/cmd_clock.c new file +7 -0

+
+	printf("Trying to set pll %d; mult %d; div %d; OD %d\n",
+	       cmd_pll_data.pll, cmd_pll_data.pll_m,
+	       cmd_pll_data.pll_d, cmd_pll_data.pll_od);
+	init_pll(&cmd_pll_data);
+
+	return 0;

arch/arm/cpu/armv7/keystone/config.mk new file +5 -0

+++ b/arch/arm/cpu/armv7/keystone/config.mk

@@ -0,0 +1,14 @@
+# (C) Copyright 2012-2014
+#     Texas Instruments Incorporated, <www.ti.com>
+# SPDX-License-Identifier:     GPL-2.0+
+#

+++ b/arch/arm/cpu/armv7/keystone/lowlevel_init.S

+++ b/board/ti/k2hk_evm/board.c

Quoted 5 lines · Murali Karicheri

k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer the ti/k2hk_evm/README for details on the board, build and other information.

Quoted 1 line

This patch add support for keystone architecture and k2hk evm.

Globally, only use
/*
* Multiline comments like this
*/

Quoted 12 lines

+++ b/arch/arm/cpu/armv7/keystone/Makefile

arch/arm/cpu/armv7/keystone/Makefile new file +10 -0

@@ -0,0 +1,18 @@
+#
+# (C) Copyright 2012-2014
+#     Texas Instruments Incorporated, <www.ti.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= aemif.o
+obj-y   += init.o
+obj-y   += psc.o

arch/arm/cpu/armv7/keystone/Makefile line 17

Quoted 7 lines

arch/arm/cpu/armv7/keystone/Makefile new file +7 -0

+obj-y   += clock.o
+obj-y   += cmd_clock.o
+obj-y   += cmd_mon.o
+obj-y   += msmc.o
+obj-y   += lowlevel_init.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-y	+= ddr3.o

Mix of space and tab, just tab it all out to line up please.

Quoted 11 lines

arch/arm/cpu/armv7/keystone/aemif.c new file +10 -0

+++ b/arch/arm/cpu/armv7/keystone/aemif.c

@@ -0,0 +1,79 @@
+/*
+ * Keystone2: Asynchronous EMIF Configuration
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+

arch/arm/cpu/armv7/keystone/aemif.c line 16

Quoted 7 lines

arch/arm/cpu/armv7/keystone/aemif.c new file +7 -0

+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+#ifdef CONFIG_SOC_K2HK
+#define ASYNC_EMIF_BASE			K2HK_ASYNC_EMIF_CNTRL_BASE
+#endif

So, does Keystone 1 have this in a different location?

arch/arm/cpu/armv7/keystone/aemif.c line 21

Quoted 4 lines

arch/arm/cpu/armv7/keystone/aemif.c new file +4 -0

+#define ASYNC_EMIF_CONFIG(cs)		(ASYNC_EMIF_BASE+0x10+(cs)*4)
+#define ASYNC_EMIF_ONENAND_CONTROL	(ASYNC_EMIF_BASE+0x5c)
+#define ASYNC_EMIF_NAND_CONTROL		(ASYNC_EMIF_BASE+0x60)
+#define ASYNC_EMIF_WAITCYCLE_CONFIG	(ASYNC_EMIF_BASE+0x4)

Register access is done over structs not define of base + offset, please rework.

Quoted 4 lines

arch/arm/cpu/armv7/keystone/aemif.c new file +4 -0

+#define CONFIG_SELECT_STROBE(v)		((v) ? 1 << 31 : 0)
+#define CONFIG_EXTEND_WAIT(v)		((v) ? 1 << 30 : 0)
+#define CONFIG_WR_SETUP(v)		(((v) & 0x0f) << 26)
+#define CONFIG_WR_STROBE(v)		(((v) & 0x3f) << 20)

arch/arm/cpu/armv7/keystone/aemif.c line 32

Quoted 6 lines

arch/arm/cpu/armv7/keystone/aemif.c new file +6 -0

+#define CONFIG_WR_HOLD(v)		(((v) & 0x07) << 17)
+#define CONFIG_RD_SETUP(v)		(((v) & 0x0f) << 13)
+#define CONFIG_RD_STROBE(v)		(((v) & 0x3f) << 7)
+#define CONFIG_RD_HOLD(v)		(((v) & 0x07) << 4)
+#define CONFIG_TURN_AROUND(v)		(((v) & 0x03) << 2)
+#define CONFIG_WIDTH(v)			(((v) & 0x03) << 0)

To avoid confusion please do AEMIF_CONFIG_... or AEMIF_CFG_... or maybe just CFG_...

Quoted 1 line

(quoted diff) +1 -0

+++ b/arch/arm/cpu/armv7/keystone/clock-k2hk.c

[snip]

arch/arm/cpu/armv7/keystone/clock-k2hk.c line 34

Quoted 5 lines

arch/arm/cpu/armv7/keystone/clock-k2hk.c new file +5 -0

+			prediv = (tmp & 0x3f) + 1;
+			mult = (((tmp & 0x7f000) >> 6) | (pllctl_reg_read(pll,
+							mult) & 0x3f)) + 1;
+			output_div = ((pllctl_reg_read(pll, secctl) >> 19) &
+				      0xf) + 1;

Please define magic numbers, check globally.

arch/arm/cpu/armv7/keystone/clock-k2hk.c line 77

Quoted 8 lines

arch/arm/cpu/armv7/keystone/clock-k2hk.c new file +7 -0

+	return ret;
+}
+
+
+
+
+unsigned long clk_get_rate(unsigned int clk)

Extra empty lines.

Quoted 1 line

+++ b/arch/arm/cpu/armv7/keystone/clock.c

[snip]

arch/arm/cpu/armv7/keystone/clock.c line 21

Quoted 5 lines

arch/arm/cpu/armv7/keystone/clock.c new file +5 -0

+static void pll_delay(unsigned int loop_count)
+{
+	while (loop_count--)
+		asm("   NOP");
+}

If we cannot use udelay yet use sdelay.

Quoted 1 line

+#include "clock-k2hk.c"

Please use function prototypes, header files and then build the right SoC clock file itself.

Quoted 1 line

+++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c

We just added a generic

Quoted 46 lines

arch/arm/cpu/armv7/keystone/cmd_clock.c new file +45 -0

@@ -0,0 +1,139 @@
+/*
+ * keystone2: commands for clocks
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/psc_defs.h>
+
+static u32 atoui(char *pstr)
+{
+	u32 res = 0;
+
+	for (; *pstr != 0; pstr++) {
+		if (*pstr < '0' || *pstr > '9')
+			break;
+
+		res = (res * 10) + (*pstr - '0');
+	}
+
+	return res;
+}
+
+struct pll_init_data cmd_pll_data = {
+	.pll			= MAIN_PLL,
+	.pll_m			= 16,
+	.pll_d			= 1,
+	.pll_od			= 2,
+};
+
+int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc != 5)
+		goto pll_cmd_usage;
+
+	if (strncmp(argv[1], "pa", 2) == 0)
+		cmd_pll_data.pll = PASS_PLL;
+	else if (strncmp(argv[1], "arm", 3) == 0)
+		cmd_pll_data.pll = TETRIS_PLL;

arch/arm/cpu/armv7/keystone/cmd_clock.c line 55

Quoted 10 lines

arch/arm/cpu/armv7/keystone/cmd_clock.c new file +10 -0

+	else if (strncmp(argv[1], "ddr3a", 5) == 0)
+		cmd_pll_data.pll = DDR3A_PLL;
+	else if (strncmp(argv[1], "ddr3b", 5) == 0)
+		cmd_pll_data.pll = DDR3B_PLL;
+	else
+		goto pll_cmd_usage;
+
+	cmd_pll_data.pll_m   = atoui(argv[2]);
+	cmd_pll_data.pll_d   = atoui(argv[3]);
+	cmd_pll_data.pll_od  = atoui(argv[4]);

Why not simple_strtoul(argv[n], NULL, 10) ?

Quoted 7 lines

arch/arm/cpu/armv7/keystone/cmd_clock.c new file +7 -0

+
+	printf("Trying to set pll %d; mult %d; div %d; OD %d\n",
+	       cmd_pll_data.pll, cmd_pll_data.pll_m,
+	       cmd_pll_data.pll_d, cmd_pll_data.pll_od);
+	init_pll(&cmd_pll_data);
+
+	return 0;

arch/arm/cpu/armv7/keystone/cmd_clock.c line 72

Quoted 10 lines

arch/arm/cpu/armv7/keystone/cmd_clock.c new file +10 -0

+
+pll_cmd_usage:
+	return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+	pllset,	5,	0,	do_pll_cmd,
+	"set pll multiplier and pre divider",
+	"<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
+);

Wolfgang, if we add another command that takes decimal not hexidecimal inputs, you're going to hit me with a ruler, aren't you? Even for a clock command?

arch/arm/cpu/armv7/keystone/cmd_clock.c line 97

Quoted 6 lines

arch/arm/cpu/armv7/keystone/cmd_clock.c new file +6 -0

+U_BOOT_CMD(
+	getclk,	2,	0,	do_getclk_cmd,
+	"get clock rate",
+	"<clk index>\n"
+	"See the 'enum clk_e' in the k2hk clock.h for clk indexes\n"
+);

This would fit with the generic clk command and 'dump' which we just added.

Quoted 6 lines

arch/arm/cpu/armv7/keystone/config.mk new file +5 -0

+++ b/arch/arm/cpu/armv7/keystone/config.mk

@@ -0,0 +1,14 @@
+# (C) Copyright 2012-2014
+#     Texas Instruments Incorporated, <www.ti.com>
+# SPDX-License-Identifier:     GPL-2.0+
+#

arch/arm/cpu/armv7/keystone/config.mk line 14

Quoted 10 lines

arch/arm/cpu/armv7/keystone/config.mk new file +10 -0

+
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
+
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
+		    $(call cc-option,-malignment-traps,))

You need to do this as:
PF_CPPFLAGS_SLB := ...
PLATFORM_RELFALGS += $(PF_CPPFLAGS_SLB)

The way you have it causes an evaluation per file and the above is a one time evaluation.

arch/arm/cpu/armv7/keystone/ddr3.c

Quoted 5 lines

arch/arm/cpu/armv7/keystone/ddr3.c new file +0 -0

new file mode 100644
index 0000000..4875db7

Part of me wonders just how close/far this is from the omap-common EMIF/DDR code. Some parts look pretty familiar (and makes me wonder if you don't have some corner-case bugs around not setting shadow registers and initially setting some of the values to max, then setting them optimally due to which bits cause a refresh cycle).

Quoted 1 line

+++ b/arch/arm/cpu/armv7/keystone/lowlevel_init.S

Is there a reason you don't use arch/arm/cpu/armv7/lowlevel_init.S and the s_init calling sequence?

Quoted 1 line

+++ b/board/ti/k2hk_evm/board.c

[snip]

arch/arm/cpu/armv7/keystone/ddr3.c

Quoted 11 lines

arch/arm/cpu/armv7/keystone/ddr3.c new file +11 -0

+/* Byte swap the 32-bit data if the device is BE */
+int cpu_to_bus(u32 *ptr, u32 length)
+{
+	u32 i;
+
+	if (device_big_endian)
+		for (i = 0; i < length; i++, ptr++)
+			*ptr = __swab32(*ptr);
+
+	return 0;
+}

cpu_to_be32() ?

arch/arm/cpu/armv7/keystone/ddr3.c

Quoted 3 lines

arch/arm/cpu/armv7/keystone/ddr3.c new file +3 -0

+int board_init(void)
+{
+	gd->bd->bi_arch_number = -1;

Just don't set it?

arch/arm/cpu/armv7/keystone/ddr3.c

Quoted 7 lines

arch/arm/cpu/armv7/keystone/ddr3.c new file +7 -0

+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+#endif
+}

This belongs in one of the arch/arm/cpu/armv7/keystone/ files

arch/arm/cpu/armv7/keystone/ddr3.c line 3

Quoted 5 lines

+++ b/drivers/i2c/keystone_i2c.c

arch/arm/cpu/armv7/keystone/ddr3.c new file +3 -0

@@ -0,0 +1,372 @@
+/*
+ * TI Keystone i2c driver
+ * Based on TI DaVinci (TMS320DM644x) I2C driver.

And how different is it really? Can we not reuse the davinci driver?

Quoted 6 lines · Tom Rini

Quoted 4 lines · Murali Karicheri

k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer the ti/k2hk_evm/README for details on the board, build and other information.

Quoted 4 lines

arch/arm/cpu/armv7/keystone/aemif.c line 16

Quoted 3 lines

arch/arm/cpu/armv7/keystone/aemif.c new file +3 -0

+#ifdef CONFIG_SOC_K2HK
+#define ASYNC_EMIF_BASE            K2HK_ASYNC_EMIF_CNTRL_BASE
+#endif

So, does Keystone 1 have this in a different location?

That is not for Keystone1. K2HK is for Hawking and Kepler SoC. The ASYNC_EMIF_BASE may be different for other SOC of the Keystone2 family.

Quoted 6 lines

arch/arm/cpu/armv7/keystone/aemif.c line 21

Quoted 4 lines

arch/arm/cpu/armv7/keystone/aemif.c new file +4 -0

+#define ASYNC_EMIF_CONFIG(cs)        (ASYNC_EMIF_BASE+0x10+(cs)*4)
+#define ASYNC_EMIF_ONENAND_CONTROL    (ASYNC_EMIF_BASE+0x5c)
+#define ASYNC_EMIF_NAND_CONTROL        (ASYNC_EMIF_BASE+0x60)
+#define ASYNC_EMIF_WAITCYCLE_CONFIG    (ASYNC_EMIF_BASE+0x4)

Register access is done over structs not define of base + offset, please rework.

This style was taken form Davinci code. Shall we rework it?

Quoted 9 lines

Quoted 1 line

+++ b/arch/arm/cpu/armv7/keystone/clock.c

[snip]

arch/arm/cpu/armv7/keystone/clock.c line 21

Quoted 5 lines

arch/arm/cpu/armv7/keystone/clock.c new file +5 -0

+static void pll_delay(unsigned int loop_count)
+{
+    while (loop_count--)
+        asm("   NOP");
+}

If we cannot use udelay yet use sdelay.

Quoted 3 lines

Quoted 1 line

+#include "clock-k2hk.c"

Please use function prototypes, header files and then build the right SoC clock file itself.

The idea was to have common clock.h for all Keystone2 family and include in to
it a specific for each SoC include file. Are you asking to remove that specific include
from the clock.h?

Quoted 11 lines

arch/arm/cpu/armv7/keystone/ddr3.c

Quoted 6 lines

arch/arm/cpu/armv7/keystone/ddr3.c new file +0 -0

new file mode 100644
index 0000000..4875db7

Part of me wonders just how close/far this is from the omap-common EMIF/DDR code. Some parts look pretty familiar (and makes me wonder if you don't have some corner-case bugs around not setting shadow registers and initially setting some of the values to max, then setting them optimally due to which bits cause a refresh cycle).

This code is based on AVV test code and is very specific to SOC DDR3 controller,
which as I know is different from OMAP.

Quoted 7 lines

arch/arm/cpu/armv7/keystone/ddr3.c line 3

Quoted 5 lines

+++ b/drivers/i2c/keystone_i2c.c

arch/arm/cpu/armv7/keystone/ddr3.c new file +3 -0

@@ -0,0 +1,372 @@
+/*
+ * TI Keystone i2c driver
+ * Based on TI DaVinci (TMS320DM644x) I2C driver.

And how different is it really? Can we not reuse the davinci driver?

It is reworked a little bit and also supports multiple ports, while davinci driver supports only one.

-----Original Message-----
From: Tom Rini [mailto:tom.rini at gmail.com] On Behalf Of Rini, Tom
Sent: Monday, February 10, 2014 4:26 PM
To: Karicheri, Muralidharan
Cc: u-boot at lists.denx.de; Sandeep at theia.denx.de; Kwok, WingMan; Nair, Sandeep; Andrianov, Vitaly
Subject: Re: [U-Boot] [U-Boot:RESEND][[PATCH 6/7] k2hk: add support for k2hk SOC and EVM

Quoted 2 lines · Murali Karicheri

k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer

the

Quoted 4 lines

ti/k2hk_evm/README for details on the board, build and other information.

This patch add support for keystone architecture and k2hk evm.

Quoted 2 lines

+++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c

We just added a generic

Quoted 18 lines

-----Original Message-----
From: Tom Rini [mailto:tom.rini at gmail.com] On Behalf Of Rini, Tom
Sent: Monday, February 10, 2014 4:26 PM
To: Karicheri, Muralidharan
Cc: u-boot at lists.denx.de; Sandeep at theia.denx.de; Kwok, WingMan; Nair, Sandeep; Andrianov, Vitaly
Subject: Re: [U-Boot] [U-Boot:RESEND][[PATCH 6/7] k2hk: add support for k2hk SOC and EVM

Quoted 2 lines · Murali Karicheri

k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer

the

Quoted 4 lines

ti/k2hk_evm/README for details on the board, build and other information.

This patch add support for keystone architecture and k2hk evm.

[snip]

Quoted 1 line

Quoted 4 lines

Quoted 1 line

+++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c

We just added a generic

Tom,
Where can I see this generic implementation?

-----Original Message-----
From: Rini, Tom
Sent: Monday, February 17, 2014 4:58 PM
To: Andrianov, Vitaly
Cc: Karicheri, Muralidharan; u-boot at lists.denx.de; Sandeep at theia.denx.de; Kwok, WingMan; Nair, Sandeep
Subject: Re: [U-Boot] [U-Boot:RESEND][[PATCH 6/7] k2hk: add support for k2hk SOC and EVM

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Quoted 5 lines · Vitaly

Quoted 5 lines

-----Original Message-----
From: Tom Rini [mailto:tom.rini at gmail.com] On Behalf Of Rini, Tom
Sent: Monday, February 10, 2014 4:26 PM
To: Karicheri, Muralidharan
Cc: u-boot at lists.denx.de; Sandeep at theia.denx.de; Kwok, WingMan;

Nair,

Quoted 7 lines

Quoted 7 lines

Sandeep; Andrianov, Vitaly
Subject: Re: [U-Boot] [U-Boot:RESEND][[PATCH 6/7] k2hk: add support for k2hk SOC and EVM

Quoted 1 line · Murali Karicheri

k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler

SoC.

Quoted 15 lines

Quoted 6 lines

Quoted 1 line

Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer

the

Quoted 4 lines

ti/k2hk_evm/README for details on the board, build and other information.

This patch add support for keystone architecture and k2hk evm.

[snip]

Quoted 5 lines

Quoted 2 lines

+++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c

We just added a generic

Quoted 2 lines

Tom,
Where can I see this generic implementation?

Start poking at common/cmd_clk.c

- --
Tom
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- Resending since I missed some in the CC

This patch series add support for keystone2 SoC and K2HK EVM.

Following patches were reviewed before in this list and v1 of the same is send with review comments incorporated:-
- tools: mkimage: add support for gpimage format
- arm: add support for arch timer
- NAND: DaVinci: allow forced disable of subpage writes

The patch below is added as a seperate patch based on comments:-
- tools: sort the entries in Makefile

Murali Karicheri (5):
tools: sort the entries in Makefile

tools: mkimage: add support for gpimage format

NAND: DaVinci: allow forced disable of subpage writes
k2hk: add support for k2hk SOC and EVM
keystone2: net: add keystone ethernet driver

Hi Murali,

Quoted 10 lines · Murali Karicheri

- Resending since I missed some in the CC

This patch series add support for keystone2 SoC and K2HK EVM.

Following patches were reviewed before in this list and v1 of the same is send with review comments incorporated:-
- tools: mkimage: add support for gpimage format
- arm: add support for arch timer
- NAND: DaVinci: allow forced disable of subpage writes

Quoted 6 lines

The patch below is added as a seperate patch based on comments:-
- tools: sort the entries in Makefile

Murali Karicheri (5):
tools: sort the entries in Makefile
tools: mkimage: add support for gpimage format

Is this image format required? Can't one of the existing image formats be used?

Quoted 3 lines

NAND: DaVinci: allow forced disable of subpage writes
k2hk: add support for k2hk SOC and EVM
keystone2: net: add keystone ethernet driver

Amicalement,

Quoted 15 lines · Albert ARIBAUD

Hi Murali,

Quoted 10 lines · Murali Karicheri

- Resending since I missed some in the CC

This patch series add support for keystone2 SoC and K2HK EVM.

Following patches were reviewed before in this list and v1 of the same is send with review comments incorporated:-
- tools: mkimage: add support for gpimage format
- arm: add support for arch timer
- NAND: DaVinci: allow forced disable of subpage writes

Quoted 8 lines

Quoted 6 lines

The patch below is added as a seperate patch based on comments:-
- tools: sort the entries in Makefile

Murali Karicheri (5):
tools: sort the entries in Makefile
tools: mkimage: add support for gpimage format

Is this image format required? Can't one of the existing image formats be used?

Alebert,

Thanks for your response.

We are actually re-using part of the OMAP image format by factoring out the common code
and re-using. So this is not a new format. Please review the code.

Murali

Hi Murali,

Quoted 28 lines · Murali Karicheri

Quoted 15 lines · Albert ARIBAUD

Hi Murali,

Quoted 10 lines · Murali Karicheri

- Resending since I missed some in the CC

This patch series add support for keystone2 SoC and K2HK EVM.

Following patches were reviewed before in this list and v1 of the same is send with review comments incorporated:-
- tools: mkimage: add support for gpimage format
- arm: add support for arch timer
- NAND: DaVinci: allow forced disable of subpage writes

Quoted 8 lines

Quoted 6 lines

The patch below is added as a seperate patch based on comments:-
- tools: sort the entries in Makefile

Murali Karicheri (5):
tools: sort the entries in Makefile
tools: mkimage: add support for gpimage format

Is this image format required? Can't one of the existing image formats be used?

Alebert,

Thanks for your response.

Quoted 3 lines

We are actually re-using part of the OMAP image format by factoring out the common code
and re-using. So this is not a new format. Please review the code.

Thanks. This describes what you do and how you do it, but it does not tell me why you are doing it and why you can't do otherwise. Let me rephrase my question since you're mentioning branching off the OMAP image format: why branch off? Why not simply use the existing OMAP image format? Or another one?

Quoted 1 line

Murali

Amicalement,

Quoted 33 lines · Albert ARIBAUD

Hi Murali,

Quoted 28 lines · Murali Karicheri

Quoted 15 lines · Albert ARIBAUD

Hi Murali,

Quoted 10 lines · Murali Karicheri

- Resending since I missed some in the CC

This patch series add support for keystone2 SoC and K2HK EVM.

Following patches were reviewed before in this list and v1 of the same is send with review comments incorporated:-
- tools: mkimage: add support for gpimage format
- arm: add support for arch timer
- NAND: DaVinci: allow forced disable of subpage writes

Quoted 8 lines

Quoted 6 lines

The patch below is added as a seperate patch based on comments:-
- tools: sort the entries in Makefile

Murali Karicheri (5):
tools: sort the entries in Makefile
tools: mkimage: add support for gpimage format

Is this image format required? Can't one of the existing image formats be used?

Alebert,

Thanks for your response.

Quoted 8 lines

Quoted 3 lines

We are actually re-using part of the OMAP image format by factoring out the common code
and re-using. So this is not a new format. Please review the code.

Thanks. This describes what you do and how you do it, but it does not tell me why you are doing it and why you can't do otherwise. Let me rephrase my question since you're mentioning branching off the OMAP image format: why branch off? Why not simply use the existing OMAP image format? Or another one?

Because the ROM bootloader in our platform (keystone2) expect the header to be in
the following format :-

<size - 4 byte> <load addr- 4 byte> <data>

OMAP uses different format
<omap header 512 bytes> <size - 4 byte> <load addr - 4 bytes>

gp header (size, loadaddr) is common between the two image formats. So that is factored out and used in our platform. Hope this is clear now.

Regards,

Murali

- Resending since I missed some in the CC

This patch series add support for keystone2 SoC and K2HK EVM.

Following patches were reviewed before in this list and v1 of the same is send with review comments incorporated:-
- tools: mkimage: add support for gpimage format
- arm: add support for arch timer
- NAND: DaVinci: allow forced disable of subpage writes

The patch below is added as a seperate patch based on comments:-
- tools: sort the entries in Makefile

Murali Karicheri (5):
tools: sort the entries in Makefile
tools: mkimage: add support for gpimage format
NAND: DaVinci: allow forced disable of subpage writes
k2hk: add support for k2hk SOC and EVM
keystone2: net: add keystone ethernet driver

Vitaly Andrianov (2):
fdt: call ft_board_setup_ex() at the end of image_setup_libfdt()
arm: add support for arch timer