ARM: defining idle states DT bindings
v4 cover ARM: defining idle states DT bindings
This is v4 of a previous posting:
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-February/231635.html
This patchset depends on the following bindings to be approved and augmented to cater for hierarchical power domains in DT:
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-January/224928.html
Changes in v4:
- Made entry-method global
- Renamed power_state parameter
- Augmented examples with retention states and node tags
- Reworded index property definition in the state node
- Changed the naming scheme for state nodes to default DT
- Defined idle_standby idle state (need not be listed)
- Clarified SBSA nomenclature and usage in the bindings
Changes in v3:
- Renamed C-states to "idle states" in patches and cover letter
- Added SBSA definitions
- Added power_state parameter to PSCI
- Removed OPP dependency
- Split latency into entry/exit latencies
- Reintroduced processor and cache retention boolean
- Made power_state generic parameter for all entry methods
- Redefined idle state hierarchy
Changes in v2:
- Updated cache bindings according to review
- Added power domain phandle to cache bindings
- Added power domains to C-states bindings
- Removed useless reg property from C-states bindings
- Removed cpu-map references from C-states bindings
- Added dependency on OPP in C-states parameters
- Added C-state state hierarchy
ARM based systems embed power management HW that allows SW to enter low-power states according to run-time criteria based on parameters (eg power state entry/exit latency) that define how an idle state has to be managed and its respective properties. ARM partners implement HW power management schemes through custom HW, with power controllers and relative control mechanisms differing on both HW implementations and the way SW can control them. This differentiation forces PM software in the kernel to cope with states differences in power management drivers, which cause code fragmentation and duplication of functionality.
Most of the power control scheme HW parameters are not probeable on ARM platforms from a SW point of view, hence, in order to tackle the drivers fragmentation problem, this patch series defines device tree bindings to describe idle states parameters on ARM platforms.
Device tree bindings for idle states also require the introduction of device tree bindings for processor caches, since idle states entry/exit require SW cache maintainance; in some ARM systems, where firmware does not support power down interfaces, cache maintainance must be carried out in the OS power management layer, which then requires a description of the cache topology through device tree nodes.
Idle states device tree standardization shares most of the concepts and definitions with the ongoing ACPI ARM C-state bindings proposal so that both standards can contain a coherent set of parameters, simplifying the way SW will have to handle the respective device drivers.
Lorenzo Pieralisi (3):
Documentation: devicetree: psci: define CPU suspend parameter
Documentation: arm: add cache DT bindings
Documentation: arm: define DT idle states bindings
Documentation/devicetree/bindings/arm/cache.txt | 167 + Documentation/devicetree/bindings/arm/cpus.txt | 10 + Documentation/devicetree/bindings/arm/idle-states.txt | 781 +++++ Documentation/devicetree/bindings/arm/psci.txt | 11 + 4 files changed, 969 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/cache.txt create mode 100644 Documentation/devicetree/bindings/arm/idle-states.txt
Signature · 1 line
1.8.4
RFC PATCH v4 1/3 Documentation: devicetree: psci: define CPU suspend parameter
OS layers built on top of PSCI to enter low-power states require the power_state parameter to be passed to the PSCI CPU suspend method.
This parameter is specific to a power state and platform specific, therefore must be provided by firmware to the OS in order to enable proper call sequence.
This patch adds a property in the PSCI bindings that describes how the CPU suspend power_state parameter should be defined in DT in all device nodes that rely on PSCI CPU suspend method usage.
--- Documentation/devicetree/bindings/arm/psci.txt | 11 +++++ 1 file changed, 11 insertions(+)
Documentation/devicetree/bindings/arm/psci.txt +11 -0
@@ -42,6 +42,14 @@ Main node optional properties: - migrate : Function ID for MIGRATE operation +Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie idle +states bindings[1]) must specify the following properties: + +- entry-method-param + Usage: Required for idle states bindings [1]. + Value type: <u32> + Definition: power_state parameter to pass to the PSCI + suspend call. Example:
@@ -53,3 +61,6 @@ Example: cpu_on = <0x95c10002>; migrate = <0x95c10003>; }; + +[1] Kernel documentation - ARM idle states bindings + Documentation/devicetree/bindings/arm/idle-states.txt
Signature · 1 line
1.8.4
RFC PATCH v4 2/3 Documentation: arm: add cache DT bindings
In reply to Lorenzo PieralisiOn ARM systems the cache topology cannot be probed at runtime, in particular, it is impossible to probe which CPUs share a given cache level. Power management software requires this knowledge to implement optimized power down sequences, hence this patch adds a document that defines the DT cache bindings for ARM systems. The bindings supersede cache bindings in the ePAPR (PowerPC bindings), because caches geometry for architected caches is probeable on ARM systems. This patch also adds properties that are specific to ARM architected caches to the existing ones defined in the ePAPR v1.1, as bindings extensions.
--- Documentation/devicetree/bindings/arm/cache.txt | 167 +++++ 1 file changed, 167 insertions(+)
Documentation/devicetree/bindings/arm/cache.txt new file +167 -0
@@ -0,0 +1,167 @@ +========================================== +ARM processors cache binding description +========================================== + +Device tree bindings for cache nodes are already part of the ePAPR standard +v1.1 ([2]) for PowerPC platforms. This document defines the cache bindings +for caches on ARM processor systems. + +On ARM based systems most of the cache properties related to cache geometry +are probeable in HW (please refer to the processor TRMs in [1] for register +details), hence, unless otherwise stated, the properties defined in ePAPR for +internal, multi-level and shared caches ([2], 3.7.3, 3.8) are to be considered +superseded on ARM. + +On ARM, caches are either architected (directly controlled by the processor +through coprocessor instructions and tightly coupled with the processor +implementation) or unarchitected (controlled through a memory mapped +interface, implemented as a stand-alone IP external to the processor +implementation). + +This document provides the device tree bindings for ARM architected caches. + +- ARM architected cache node + + Description: must be a direct child of the cpu node. + A system can contain multiple architected cache nodes + per cpu node, linked through the next-level-cache phandle. + The next-level-cache property in the cpu node points to + the first level of architected cache for the CPU. + The next-level-cache links ordering must represent the + system cache hierarchy in the system, with the upper + cache level represented by a cache node with a missing + next-level-cache property. + + ARM architected cache node defines the following properties: + + - compatible + Usage: Required + Value type: <string> + Definition: value shall be "arm,arch-cache". + + - power-domain + Usage: Optional + Value type: phandle + Definition: A phandle and power domain specifier as defined by + bindings of power domain specified by the + phandle [3]. + +Example(dual-cluster big.LITTLE system 32-bit) + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + next-level-cache = <&L1_0>; + + L1_0: l1-cache { + compatible = "arm,arch-cache"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "arm,arch-cache"; + }; + }; + + cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + next-level-cache = <&L1_1>; + + L1_1: l1-cache { + compatible = "arm,arch-cache"; + next-level-cache = <&L2_0>; + }; + }; + + cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x2>; + next-level-cache = <&L1_2>; + + L1_2: l1-cache { + compatible = "arm,arch-cache"; + next-level-cache = <&L2_0>; + }; + }; + + cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x3>; + next-level-cache = <&L1_3>; + + L1_3: l1-cache { + compatible = "arm,arch-cache"; + next-level-cache = <&L2_0>; + }; + }; + + cpu at 100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + next-level-cache = <&L1_4>; + + L1_4: l1-cache { + compatible = "arm,arch-cache"; + next-level-cache = <&L2_1>; + }; + + L2_1: l2-cache { + compatible = "arm,arch-cache"; + }; + }; + + cpu at 101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + next-level-cache = <&L1_5>; + + L1_5: l1-cache { + compatible = "arm,arch-cache"; + next-level-cache = <&L2_1>; + }; + }; + + cpu at 102 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + next-level-cache = <&L1_6>; + + L1_6: l1-cache { + compatible = "arm,arch-cache"; + next-level-cache = <&L2_1>; + }; + }; + + cpu at 103 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + next-level-cache = <&L1_7>; + + L1_7: l1-cache { + compatible = "arm,arch-cache"; + next-level-cache = <&L2_1>; + }; + }; + }; + +[1] ARM Architecture Reference Manuals + http://infocenter.arm.com/help/index.jsp + +[2] ePAPR standard + https://www.power.org/documentation/epapr-version-1-1/ + +[3] Kernel documentation - power domain bindings + Documentation/devicetree/bindings/power/power_domain.txt
Signature · 1 line
1.8.4
RFC PATCH v4 3/3 Documentation: arm: define DT idle states bindings
In reply to Lorenzo PieralisiARM based platforms implement a variety of power management schemes that allow processors to enter idle states at run-time.
The parameters defining these idle states vary on a per-platform basis forcing the OS to hardcode the state parameters in platform specific static tables whose size grows as the number of platforms supported in the kernel increases and hampers device drivers standardization.
Therefore, this patch aims at standardizing idle state device tree bindings for ARM platforms. Bindings define idle state parameters inclusive of entry methods and state latencies, to allow operating systems to retrieve the configuration entries from the device tree and initialize the related power management drivers, paving the way for common code in the kernel to deal with idle states and removing the need for static data in current and previous kernel versions.
--- Documentation/devicetree/bindings/arm/cpus.txt | 10 + Documentation/devicetree/bindings/arm/idle-states.txt | 781 +++++ 2 files changed, 791 insertions(+)
Documentation/devicetree/bindings/arm/cpus.txt +10 -0
@@ -191,6 +191,13 @@ nodes to be present and contain the properties described below. property identifying a 64-bit zero-initialised memory location. + - cpu-idle-states + Usage: Optional + Value type: <prop-encoded-array> + Definition: + # List of phandles to idle state nodes supported + by this cpu [1]. + Example 1 (dual-cluster big.LITTLE system 32-bit): cpus {
@@ -382,3 +389,6 @@ cpus { cpu-release-addr = <0 0x20000000>; }; }; + +[1] ARM Linux kernel documentation - idle states bindings + Documentation/devicetree/bindings/arm/idle-states.txt
Documentation/devicetree/bindings/arm/idle-states.txt new file +781 -0
781 lines not on this page · raw message
Signature · 1 line
1.8.4
RFC PATCH v4 3/3 Documentation: arm: define DT idle states bindings
Quoting Lorenzo Pieralisi (2014-02-18 03:47:31)
Documentation/devicetree/bindings/arm/idle-states.txt line 132
Quoted 7 lines
Documentation/devicetree/bindings/arm/idle-states.txt new file +7
-0+ - index + Usage: Required + Value type: <u32> + Definition: It represents the idle state index. + An increasing index value implies less power + consumption. Index must be given a sequential + value = {0, 1, ....}, starting from 0.
One minor comment. In the example, it can be tricky to see how this is sequential since the states interleave. Not sure if it merits rewording here?
These look good to me!
Thanks!
Sebastian
RFC PATCH v4 3/3 Documentation: arm: define DT idle states bindings
Quoted 10 lines · Sebastian Capella
Quoting Lorenzo Pieralisi (2014-02-18 03:47:31)
Documentation/devicetree/bindings/arm/idle-states.txt line 132
Quoted 7 lines
Documentation/devicetree/bindings/arm/idle-states.txt new file +7
-0+ - index + Usage: Required + Value type: <u32> + Definition: It represents the idle state index. + An increasing index value implies less power + consumption. Index must be given a sequential + value = {0, 1, ....}, starting from 0.One minor comment. In the example, it can be tricky to see how this is sequential since the states interleave. Not sure if it merits rewording here?
- index
Usage: Required
Value type: <u32>
Definition: It represents the idle state index.
The index must be given an increasing value = {0, 1, ....}, starting from 0, with higher values implying less power consumption. Indices must be unique as seen from a cpu perspective, ie phandles in the cpu nodes [1] cpu-idle-states array property are not allowed to point at idle state nodes having the same index value.
Ack ?
I will post a v5, should be final.
Lorenzo
Re: [PATCH RFC v4 3/3] Documentation: arm: define DT idle states bindings
Quoted 3 lines · Lorenzo Pieralisi
Ack ?
Hi Lorenzo,
Yes, ack from me.
Thanks!
Sebastian
RFC PATCH v4 3/3 Documentation: arm: define DT idle states bindings
In reply to Lorenzo PieralisiQuoted 1 line · Lorenzo Pieralisi
Ack ?
Hi Lorenzo,
Yes, ack from me.
Thanks!
Sebastian
RFC PATCH v4 3/3 Documentation: arm: define DT idle states bindings
In reply to Lorenzo PieralisiQuoted 71 lines · Lorenzo Pieralisi
ARM based platforms implement a variety of power management schemes that allow processors to enter idle states at run-time.
The parameters defining these idle states vary on a per-platform basis forcing the OS to hardcode the state parameters in platform specific static tables whose size grows as the number of platforms supported in the kernel increases and hampers device drivers standardization.Therefore, this patch aims at standardizing idle state device tree bindings for ARM platforms. Bindings define idle state parameters inclusive of entry methods and state latencies, to allow operating systems to retrieve the configuration entries from the device tree and initialize the related power management drivers, paving the way for common code in the kernel to deal with idle states and removing the need for static data in current and previous kernel versions.
Signed-off-by Lorenzo Pieralisi <[email protected]>--- Documentation/devicetree/bindings/arm/cpus.txt | 10 + Documentation/devicetree/bindings/arm/idle-states.txt | 781 +++++ 2 files changed, 791 insertions(+)Documentation/devicetree/bindings/arm/cpus.txt +10
-0@@ -191,6 +191,13 @@ nodes to be present and contain the properties described below. property identifying a 64-bit zero-initialised memory location. + - cpu-idle-states + Usage: Optional + Value type: <prop-encoded-array> + Definition: + # List of phandles to idle state nodes supported + by this cpu [1]. + Example 1 (dual-cluster big.LITTLE system 32-bit): cpus {@@ -382,3 +389,6 @@ cpus { cpu-release-addr = <0 0x20000000>; }; }; + +[1] ARM Linux kernel documentation - idle states bindings + Documentation/devicetree/bindings/arm/idle-states.txtDocumentation/devicetree/bindings/arm/idle-states.txt new file +19
-0@@ -0,0 +1,781 @@ +========================================== +ARM idle states binding description +========================================== + +========================================== +1 - Introduction +========================================== + +ARM systems contain HW capable of managing power consumption dynamically, +where cores can be put in different low-power states (ranging from simple +wfi to power gating) according to OSPM policies. The CPU states representing +the range of dynamic idle states that a processor can enter at run-time, can be +specified through device tree bindings representing the parameters required +to enter/exit specific idle states on a given processor. + +According to the Server Base System Architecture document (SBSA, [4]), the +power states an ARM CPU can be put into are identified by the following list: + +- Running
Documentation/devicetree/bindings/arm/idle-states.txt line 29
Quoted 10 lines
Documentation/devicetree/bindings/arm/idle-states.txt new file +10
-0+- Idle_standby +- Idle_retention +- Sleep +- Off + +The power states described in the SBSA document define the basic CPU states on +top of which ARM platforms implement power management schemes that allow an OS +PM implementation to put the processor in different idle states (which include +states listed above; "off" state is not an idle state since it does not have +wake-up capabilities, hence it is not considered in this document).
Is your only target SBSA compliant systems? If so, we obviously don't need this since those will all be using ACPI. :)
Either way I'd like to see some real usage of this binding. We continue to add more and more complexity to cpu related DT bindings with very little actual use. We don't need bindings for how ARM thinks h/w should work. We need bindings for how h/w actually works.
I continue to be confused why we added cpu topology bindings yet don't add information that applies to certain levels in the topology. This makes me think the topology should just be built into /cpus.
Quoted 96 lines
Documentation/devicetree/bindings/arm/idle-states.txt new file +96
-0+ +Idle state parameters (eg entry latency) are platform specific and need to be +characterized with bindings that provide the required information to OSPM +code so that it can build the required tables and use them at runtime. + +The device tree binding definition for ARM idle states is the subject of this +document. + +=========================================== +2 - idle-states node +=========================================== + +ARM processor idle states are defined within the idle-states node, which is +a direct child of the cpus node and provides a container where the processor +idle states, defined as device tree nodes, are listed. + +- idle-states node + + Usage: Optional - On ARM systems, is a container of processor idle + states nodes. If the system does not provide CPU + power management capabilities or the processor just + supports idle_standby an idle-states node is not + required. + + Description: idle-states node is a container node, where its + subnodes describe the CPU idle states. + + Node name must be "idle-states". + + The idle-states node's parent node must be the cpus node. + + The idle-states node's child nodes can be: + + - one or more state nodes + + Any other configuration is considered invalid. + + An idle-states node defines the following properties: + + - entry-method + Usage: Required + Value type: <stringlist> + Definition: Describes the method by which a CPU enters the + idle states. This property is required and must be + one of: + + - "arm,psci-cpu-suspend" + ARM PSCI firmware interface, CPU suspend + method[3]. + + - "[vendor],[method]" + An implementation dependent string with + format "vendor,method", where vendor is a string + denoting the name of the manufacturer and + method is a string specifying the mechanism + used to enter the idle state. + +The nodes describing the idle states (state) can only be defined within the +idle-states node. + +Any other configuration is consider invalid and therefore must be ignored. + +=========================================== +3 - state node +=========================================== + +A state node represents an idle state description and must be defined as +follows: + +- state node + + Description: must be child of either the idle-states node or + a state node. + + The state node name shall follow standard device tree naming + rules ([6], 2.2.1 "Node names"), in particular state nodes which + are siblings within a single common parent must be given a unique name. + + The idle state entered by executing the wfi instruction (idle_standby + SBSA,[4][5]) is considered standard on all ARM platforms and therefore + must not be listed. + + A state node can contain state child nodes. A state node with + children represents a hierarchical state, which is a superset of + the child states. Hierarchical states require all CPUs on which + they are valid (ie cpu nodes [1] containing cpu-idle-states arrays + having a phandle to the state) to request the state in order for it + to be entered. + + A state node defines the following properties: + + - compatible + Usage: Required + Value type: <stringlist> + Definition: Must be "arm,idle-state". +
Documentation/devicetree/bindings/arm/idle-states.txt line 135
Quoted 10 lines
Documentation/devicetree/bindings/arm/idle-states.txt new file +10
-0+ - index + Usage: Required + Value type: <u32> + Definition: It represents the idle state index. + An increasing index value implies less power + consumption. Index must be given a sequential + value = {0, 1, ....}, starting from 0. + Phandles in the cpu nodes [1] cpu-idle-states + array property are not allowed to point at idle + state nodes having the same index value.
Generally, we don't do indexes in DT. Why is this not just the order of states defined in the DT.
cpuidle wants to know the power consumption for a state as well as latencies. While I'm not for just putting what Linux wants into DT, that does seem like a h/w property. How do you plan to handle that? Maybe it is deemed to not really be useful information. After all, I just made shit up for highbank.
Quoted 15 lines
Documentation/devicetree/bindings/arm/idle-states.txt new file +15
-0+ + - logic-state-retained + Usage: See definition + Value type: <none> + Definition: if present logic is retained on state entry, + otherwise it is lost. + + - cache-state-retained + Usage: See definition + Value type: <none> + Definition: if present cache memory is retained on state entry, + otherwise it is lost. + + - entry-method-param + Usage: See definition.
Documentation/devicetree/bindings/arm/idle-states.txt line 160
Quoted 10 lines
Documentation/devicetree/bindings/arm/idle-states.txt new file +10
-0+ Value type: <u32> + Definition: Depends on the idle-states node entry-method + property value. Refer to the entry-method bindings + for this property value definition. + + - entry-latency + Usage: Required + Value type: <prop-encoded-array> + Definition: u32 value representing worst case latency + in microseconds required to enter the idle state.
Append times with the unit. "-us" in this case.
Documentation/devicetree/bindings/arm/idle-states.txt line 166
Quoted 6 lines
Documentation/devicetree/bindings/arm/idle-states.txt new file +6
-0+ + - exit-latency + Usage: Required + Value type: <prop-encoded-array> + Definition: u32 value representing worst case latency + in microseconds required to exit the idle state.
ditto
Documentation/devicetree/bindings/arm/idle-states.txt line 174
Quoted 8 lines
Documentation/devicetree/bindings/arm/idle-states.txt new file +8
-0+ + - min-residency + Usage: Required + Value type: <prop-encoded-array> + Definition: u32 value representing time in microseconds + required for the CPU to be in the idle state to + break even in power consumption terms compared + to idle state idle_standby ([4][5]).
ditto
Quoted 40 lines
Documentation/devicetree/bindings/arm/idle-states.txt new file +40
-0+ + - power-domains + Usage: Optional + Value type: <prop-encoded-array> + Definition: List of power domain specifiers ([2]) describing + the power domains that are affected by the idle + state entry. All devices whose power-domain phandle + points at one of the power domains listed in this + property are affected by the idle state entry. + + +=========================================== +4 - Examples +=========================================== + +Example 1 (ARM 64-bit, 16-cpu system): + +pd_clusters: power-domain-clusters at 80002000 { + compatible = "arm,power-controller"; + reg = <0x0 0x80002000 0x0 0x1000>; + #power-domain-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + + pd_cores: power-domain-cores at 80000000 { + compatible = "arm,power-controller"; + reg = <0x0 0x80000000 0x0 0x1000>; + #power-domain-cells = <1>; + }; +}; + +cpus { + #size-cells = <0>; + #address-cells = <2>; + + idle-states { + entry-method = "arm,psci-cpu-suspend"; + + CLUSTER_RET_0: cluster-ret-0 { + /* cluster retention */
Documentation/devicetree/bindings/arm/idle-states.txt line 224
Quoted 10 lines
Documentation/devicetree/bindings/arm/idle-states.txt new file +10
-0+ compatible = "arm,idle-state"; + index = <2>; + logic-state-retained; + cache-state-retained; + entry-method-param = <0x1010000>; + entry-latency = <50>; + exit-latency = <100>; + min-residency = <250>; + power-domains = <&pd_clusters 0>; + CPU_RET_0_0: cpu-ret-0 {
As I pointed out, here we have topology definition and it is independent of the cpu topology binding.
I'd prefer to see retention spelled out.
Documentation/devicetree/bindings/arm/idle-states.txt line 225
Quoted 1 line
Documentation/devicetree/bindings/arm/idle-states.txt new file +1
-0+ /* cpu retention */
then the comment wouldn't be needed.
Quoted 5 lines
Documentation/devicetree/bindings/arm/idle-states.txt new file +5
-0+ compatible = "arm,idle-state"; + index = <0>; + cache-state-retained; + entry-method-param = <0x0010000>; + entry-latency = <20>;
Documentation/devicetree/bindings/arm/idle-states.txt line 240
Quoted 10 lines
Documentation/devicetree/bindings/arm/idle-states.txt new file +10
-0+ exit-latency = <40>; + min-residency = <30>; + power-domains = <&pd_cores 0>, + <&pd_cores 1>, + <&pd_cores 2>, + <&pd_cores 3>, + <&pd_cores 4>, + <&pd_cores 5>, + <&pd_cores 6>, + <&pd_cores 7>;
I don't like this. The power domain phandle for a core belongs with the core.
What if you have groups of 2 cores in 1 domain? It doesn't work and that's a very common scenario in current h/w.
Rob
RFC PATCH v4 3/3 Documentation: arm: define DT idle states bindings
Quoted 78 lines · Rob Herring
Quoted 76 lines · Lorenzo Pieralisi
ARM based platforms implement a variety of power management schemes that allow processors to enter idle states at run-time.
The parameters defining these idle states vary on a per-platform basis forcing the OS to hardcode the state parameters in platform specific static tables whose size grows as the number of platforms supported in the kernel increases and hampers device drivers standardization.Therefore, this patch aims at standardizing idle state device tree bindings for ARM platforms. Bindings define idle state parameters inclusive of entry methods and state latencies, to allow operating systems to retrieve the configuration entries from the device tree and initialize the related power management drivers, paving the way for common code in the kernel to deal with idle states and removing the need for static data in current and previous kernel versions.
Signed-off-by Lorenzo Pieralisi <[email protected]>--- Documentation/devicetree/bindings/arm/cpus.txt | 10 + Documentation/devicetree/bindings/arm/idle-states.txt | 781 +++++ 2 files changed, 791 insertions(+)Documentation/devicetree/bindings/arm/cpus.txt +10
-0@@ -191,6 +191,13 @@ nodes to be present and contain the properties described below. property identifying a 64-bit zero-initialised memory location. + - cpu-idle-states + Usage: Optional + Value type: <prop-encoded-array> + Definition: + # List of phandles to idle state nodes supported + by this cpu [1]. + Example 1 (dual-cluster big.LITTLE system 32-bit): cpus {@@ -382,3 +389,6 @@ cpus { cpu-release-addr = <0 0x20000000>; }; }; + +[1] ARM Linux kernel documentation - idle states bindings + Documentation/devicetree/bindings/arm/idle-states.txtDocumentation/devicetree/bindings/arm/idle-states.txt new file +24
-0@@ -0,0 +1,781 @@ +========================================== +ARM idle states binding description +========================================== + +========================================== +1 - Introduction +========================================== + +ARM systems contain HW capable of managing power consumption dynamically, +where cores can be put in different low-power states (ranging from simple +wfi to power gating) according to OSPM policies. The CPU states representing +the range of dynamic idle states that a processor can enter at run-time, can be +specified through device tree bindings representing the parameters required +to enter/exit specific idle states on a given processor. + +According to the Server Base System Architecture document (SBSA, [4]), the +power states an ARM CPU can be put into are identified by the following list: + +- Running +- Idle_standby +- Idle_retention +- Sleep +- Off +
Quoted 8 lines
Documentation/devicetree/bindings/arm/idle-states.txt line 29
Quoted 5 lines
Documentation/devicetree/bindings/arm/idle-states.txt new file +5
-0+The power states described in the SBSA document define the basic CPU states on +top of which ARM platforms implement power management schemes that allow an OS +PM implementation to put the processor in different idle states (which include +states listed above; "off" state is not an idle state since it does not have +wake-up capabilities, hence it is not considered in this document).Is your only target SBSA compliant systems? If so, we obviously don't need this since those will all be using ACPI. :)
SBSA defines nomenclature "on top of which ARM platforms implement power management schemes". I think that's proper wording, ACPI or DT.
Quoted 4 lines
Either way I'd like to see some real usage of this binding. We continue to add more and more complexity to cpu related DT bindings with very little actual use. We don't need bindings for how ARM thinks h/w should work. We need bindings for how h/w actually works.
That's great and that's what these bindings are meant for. If you and other reviewers out there spot inconsinstencies with how "h/w actually works (TM)", flag this up. I am not posting these bindings to define how ARM thinks h/w should work, I really do not understand why you think that's the case.
I will be posting a generic PSCI based CPU idle driver soon.
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I continue to be confused why we added cpu topology bindings yet don't add information that applies to certain levels in the topology. This makes me think the topology should just be built into /cpus.
And how is that different from cpu-map ?
Are you referring to OPPs ? What do you mean by "built into /cpus" ?
The first reason why we defined the cpu-map was to override MPIDR configurations. If we want to use that for other reasons (use phandle to topology nodes to group CPUs) that's still fine.
I told you already, it was not an easy decision to make and I am always open to suggestions, if you have a solution in mind post it.
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Documentation/devicetree/bindings/arm/idle-states.txt new file +101
-0+ +Idle state parameters (eg entry latency) are platform specific and need to be +characterized with bindings that provide the required information to OSPM +code so that it can build the required tables and use them at runtime. + +The device tree binding definition for ARM idle states is the subject of this +document. + +=========================================== +2 - idle-states node +=========================================== + +ARM processor idle states are defined within the idle-states node, which is +a direct child of the cpus node and provides a container where the processor +idle states, defined as device tree nodes, are listed. + +- idle-states node + + Usage: Optional - On ARM systems, is a container of processor idle + states nodes. If the system does not provide CPU + power management capabilities or the processor just + supports idle_standby an idle-states node is not + required. + + Description: idle-states node is a container node, where its + subnodes describe the CPU idle states. + + Node name must be "idle-states". + + The idle-states node's parent node must be the cpus node. + + The idle-states node's child nodes can be: + + - one or more state nodes + + Any other configuration is considered invalid. + + An idle-states node defines the following properties: + + - entry-method + Usage: Required + Value type: <stringlist> + Definition: Describes the method by which a CPU enters the + idle states. This property is required and must be + one of: + + - "arm,psci-cpu-suspend" + ARM PSCI firmware interface, CPU suspend + method[3]. + + - "[vendor],[method]" + An implementation dependent string with + format "vendor,method", where vendor is a string + denoting the name of the manufacturer and + method is a string specifying the mechanism + used to enter the idle state. + +The nodes describing the idle states (state) can only be defined within the +idle-states node. + +Any other configuration is consider invalid and therefore must be ignored. + +=========================================== +3 - state node +=========================================== + +A state node represents an idle state description and must be defined as +follows: + +- state node + + Description: must be child of either the idle-states node or + a state node. + + The state node name shall follow standard device tree naming + rules ([6], 2.2.1 "Node names"), in particular state nodes which + are siblings within a single common parent must be given a unique name. + + The idle state entered by executing the wfi instruction (idle_standby + SBSA,[4][5]) is considered standard on all ARM platforms and therefore + must not be listed. + + A state node can contain state child nodes. A state node with + children represents a hierarchical state, which is a superset of + the child states. Hierarchical states require all CPUs on which + they are valid (ie cpu nodes [1] containing cpu-idle-states arrays + having a phandle to the state) to request the state in order for it + to be entered. + + A state node defines the following properties: + + - compatible + Usage: Required + Value type: <stringlist> + Definition: Must be "arm,idle-state". + + - index + Usage: Required + Value type: <u32> + Definition: It represents the idle state index. + An increasing index value implies less power
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Documentation/devicetree/bindings/arm/idle-states.txt line 135
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Documentation/devicetree/bindings/arm/idle-states.txt new file +5
-0+ consumption. Index must be given a sequential + value = {0, 1, ....}, starting from 0. + Phandles in the cpu nodes [1] cpu-idle-states + array property are not allowed to point at idle + state nodes having the same index value.Generally, we don't do indexes in DT. Why is this not just the order of states defined in the DT.
Because I need a way to order states in terms of power consumption.
Quoted 3 lines
cpuidle wants to know the power consumption for a state as well as latencies. While I'm not for just putting what Linux wants into DT, that does seem like a h/w property. How do you plan to handle that?
Linux does not require power consumption for a state anymore. Ordering is needed (Linux and possibly other OS) that's what index is supposed to do, increasing indices meaning less power consumption.
Adding a h/w property for power consumption is extremely hard to define because it depends on loads of parameters and buys us nothing. Ordering is important, though.
Quoted 2 lines
Maybe it is deemed to not really be useful information. After all, I just made shit up for highbank.
That's great to read, maybe we should NAK this patch and made all data up in the kernel for the upcoming CPU idle drivers.
Or we improve it and get it in the kernel to revert that status quo.
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Documentation/devicetree/bindings/arm/idle-states.txt new file +19
-0+ + - logic-state-retained + Usage: See definition + Value type: <none> + Definition: if present logic is retained on state entry, + otherwise it is lost. + + - cache-state-retained + Usage: See definition + Value type: <none> + Definition: if present cache memory is retained on state entry, + otherwise it is lost. + + - entry-method-param + Usage: See definition. + Value type: <u32> + Definition: Depends on the idle-states node entry-method + property value. Refer to the entry-method bindings + for this property value definition.
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Documentation/devicetree/bindings/arm/idle-states.txt line 160
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Documentation/devicetree/bindings/arm/idle-states.txt new file +6
-0+ + - entry-latency + Usage: Required + Value type: <prop-encoded-array> + Definition: u32 value representing worst case latency + in microseconds required to enter the idle state.Append times with the unit. "-us" in this case.
Ok.
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Documentation/devicetree/bindings/arm/idle-states.txt line 166
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Documentation/devicetree/bindings/arm/idle-states.txt new file +6
-0+ + - exit-latency + Usage: Required + Value type: <prop-encoded-array> + Definition: u32 value representing worst case latency + in microseconds required to exit the idle state.ditto
Documentation/devicetree/bindings/arm/idle-states.txt line 174
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Documentation/devicetree/bindings/arm/idle-states.txt new file +8
-0+ + - min-residency + Usage: Required + Value type: <prop-encoded-array> + Definition: u32 value representing time in microseconds + required for the CPU to be in the idle state to + break even in power consumption terms compared + to idle state idle_standby ([4][5]).ditto
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Documentation/devicetree/bindings/arm/idle-states.txt new file +45
-0+ + - power-domains + Usage: Optional + Value type: <prop-encoded-array> + Definition: List of power domain specifiers ([2]) describing + the power domains that are affected by the idle + state entry. All devices whose power-domain phandle + points at one of the power domains listed in this + property are affected by the idle state entry. + + +=========================================== +4 - Examples +=========================================== + +Example 1 (ARM 64-bit, 16-cpu system): + +pd_clusters: power-domain-clusters at 80002000 { + compatible = "arm,power-controller"; + reg = <0x0 0x80002000 0x0 0x1000>; + #power-domain-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + + pd_cores: power-domain-cores at 80000000 { + compatible = "arm,power-controller"; + reg = <0x0 0x80000000 0x0 0x1000>; + #power-domain-cells = <1>; + }; +}; + +cpus { + #size-cells = <0>; + #address-cells = <2>; + + idle-states { + entry-method = "arm,psci-cpu-suspend"; + + CLUSTER_RET_0: cluster-ret-0 { + /* cluster retention */ + compatible = "arm,idle-state"; + index = <2>; + logic-state-retained; + cache-state-retained; + entry-method-param = <0x1010000>;
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Documentation/devicetree/bindings/arm/idle-states.txt line 224
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Documentation/devicetree/bindings/arm/idle-states.txt new file +5
-0+ entry-latency = <50>; + exit-latency = <100>; + min-residency = <250>; + power-domains = <&pd_clusters 0>; + CPU_RET_0_0: cpu-ret-0 {As I pointed out, here we have topology definition and it is independent of the cpu topology binding.
Early version of the patches used cpu-map here to define on which CPUs the state is valid. I can remove the cpu-idle-states list of phandles from the cpu nodes and define a phandle in every idle state pointing at topology nodes to describe on which CPUs that state is valid.
Is that what you want to see ? BTW, this is the only reason why I have not posted the generic idle code yet, I want to understand if there is a dependency on cpu-map parsing code first.
There is another and more important reason: what if the power domain layout does not follow the topology (a power domain for only two cores in a cluster of 4) ? Weird, but possible. I am just trying to cater for all sensible cases from the beginning, and not as an afterthought.
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I'd prefer to see retention spelled out.
Both node name and tag ? That's cumbersome, but I will do it.
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Documentation/devicetree/bindings/arm/idle-states.txt line 225
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Documentation/devicetree/bindings/arm/idle-states.txt new file +1
-0+ /* cpu retention */then the comment wouldn't be needed.
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Documentation/devicetree/bindings/arm/idle-states.txt new file +5
-0+ compatible = "arm,idle-state"; + index = <0>; + cache-state-retained; + entry-method-param = <0x0010000>; + entry-latency = <20>;Documentation/devicetree/bindings/arm/idle-states.txt line 240
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Documentation/devicetree/bindings/arm/idle-states.txt new file +10
-0+ exit-latency = <40>; + min-residency = <30>; + power-domains = <&pd_cores 0>, + <&pd_cores 1>, + <&pd_cores 2>, + <&pd_cores 3>, + <&pd_cores 4>, + <&pd_cores 5>, + <&pd_cores 6>, + <&pd_cores 7>;
Quoted 1 line
I don't like this. The power domain phandle for a core belongs with the core.
The power domains list define all power domains affected by the idle state entry. In that specific case, it is a core power-gating state valid on some of the CPUs, and the list defines all power domains affected. If we have a separate power domain for caches, or CPU peripherals this allows us to define what "CPU" components are affected by the idle state entry.
A CPU becomes just another device, attached to a list of power domains.
And in the process, it avoids replicating the same idle state for every given CPU.
Quoted 2 lines
What if you have groups of 2 cores in 1 domain? It doesn't work and that's a very common scenario in current h/w.
You define an idle state, attach it to that domain and the two cores point at it in their cpu-idle-states phandle list. Or if you prefer, the idle state points at a node in the cpu-map defining the two cores (but please see my comment above).
I just need to fix a discrepancy related to the definition of hierarchical states, whch cpus are affected by what state can be detected by using power domains phandles in the cpu node.
Thanks for having a look,
Lorenzo
RFC PATCH v4 3/3 Documentation: arm: define DT idle states bindings
In reply to Lorenzo PieralisiSorry for having been lazy in commenting..
From: Lorenzo Pieralisi <[email protected]>
Date: Tue, 18 Feb 2014 11:47:31 +0000
Documentation/devicetree/bindings/arm/idle-states.txt line 174
Quoted 7 lines
Documentation/devicetree/bindings/arm/idle-states.txt new file +7
-0+ - min-residency + Usage: Required + Value type: <prop-encoded-array> + Definition: u32 value representing time in microseconds + required for the CPU to be in the idle state to + break even in power consumption terms compared + to idle state idle_standby ([4][5]).
To me this continues to be a bit illdefined. Say we have three states:
0,1,2. State 0 is the idle_standby. Providing a minimum residency for state 1 compared to state 0 sort of makes sense, but if we provide a minimum residency for state 2 compared to state 0 the break even time is going to be smaller than break even when comparing state 1 and state 2. With this data we'd enter state 2 when we'd be better off entering state 1.
--Antti
RFC PATCH v4 3/3 Documentation: arm: define DT idle states bindings
Hi Antti,
Quoted 1 line · Antti P Miettinen
Sorry for having been lazy in commenting..
No worries, comments always welcome.
Quoted 17 lines
From: Lorenzo Pieralisi <[email protected]>
Date: Tue, 18 Feb 2014 11:47:31 +0000Documentation/devicetree/bindings/arm/idle-states.txt line 174
Quoted 7 lines
Documentation/devicetree/bindings/arm/idle-states.txt new file +7
-0+ - min-residency + Usage: Required + Value type: <prop-encoded-array> + Definition: u32 value representing time in microseconds + required for the CPU to be in the idle state to + break even in power consumption terms compared + to idle state idle_standby ([4][5]).To me this continues to be a bit illdefined. Say we have three states:
0,1,2. State 0 is theidle_standby. Providing a minimum residency for state 1 compared to state 0 sort of makes sense, but if we provide a minimum residency for state 2 compared to state 0 the break even time is going to be smaller than break even when comparing state 1 and state 2. With this data we'd enter state 2 when we'd be better off entering state 1.
I am not sure I got your reply right, but min-residency for state 2 will be higher than state 1, since it has to cater for the dynamic power consumed by entering the state (but burns less power than state 1 when _in_ the state).
Entering a state has a power cost and min-residency should take that into account, worst-case as per other stats.
min-residency (and so the break-even) should take into account that entering the state is not for free.
I think that comparing against idle_standby is the only sane way we can define that parameter, either that or we remove it.
Does it make sense ?
Thanks !
Lorenzo
RFC PATCH v4 3/3 Documentation: arm: define DT idle states bindings
From: Lorenzo Pieralisi <[email protected]>
Quoted 36 lines
Hi Antti,
Quoted 1 line · Antti P Miettinen
Sorry for having been lazy in commenting..
No worries, comments always welcome.
Quoted 17 lines
From: Lorenzo Pieralisi <[email protected]>
Date: Tue, 18 Feb 2014 11:47:31 +0000Documentation/devicetree/bindings/arm/idle-states.txt line 174
Quoted 7 lines
Documentation/devicetree/bindings/arm/idle-states.txt new file +7
-0+ - min-residency + Usage: Required + Value type: <prop-encoded-array> + Definition: u32 value representing time in microseconds + required for the CPU to be in the idle state to + break even in power consumption terms compared + to idle state idle_standby ([4][5]).To me this continues to be a bit illdefined. Say we have three states:
0,1,2. State 0 is theidle_standby. Providing a minimum residency for state 1 compared to state 0 sort of makes sense, but if we provide a minimum residency for state 2 compared to state 0 the break even time is going to be smaller than break even when comparing state 1 and state 2. With this data we'd enter state 2 when we'd be better off entering state 1.I am not sure I got your reply right, but min-residency for state 2 will be higher than state 1, since it has to cater for the dynamic power consumed by entering the state (but burns less power than state 1 when _in_ the state).
Entering a state has a power cost and min-residency should take that into account, worst-case as per other stats.
min-residency (and so the break-even) should take into account that entering the state is not for free.
Quoted 7 lines
I think that comparing against
idle_standbyis the only sane way we can define that parameter, either that or we remove it.Does it make sense ?
Thanks !
Lorenzo
The point is that if you compare breakeven between state 0 and state 2 the breakeven time will be smaller that when you compare the breakeven between state 1 and state 2. Assuming states ordered by "deepness" in the sense that deeper states have lower in-state power and longer entry/exit times.
I guess you could specify that the min-residency defines the time when the state breaks even compared to the previous (shallower) state.
--Antti
RFC PATCH v4 3/3 Documentation: arm: define DT idle states bindings
Quoted 45 lines · Antti P Miettinen
From: Lorenzo Pieralisi <[email protected]>
Quoted 36 lines
Hi Antti,
Quoted 1 line · Antti P Miettinen
Sorry for having been lazy in commenting..
No worries, comments always welcome.
Quoted 17 lines
From: Lorenzo Pieralisi <[email protected]>
Date: Tue, 18 Feb 2014 11:47:31 +0000Documentation/devicetree/bindings/arm/idle-states.txt line 174
Quoted 7 lines
Documentation/devicetree/bindings/arm/idle-states.txt new file +7
-0+ - min-residency + Usage: Required + Value type: <prop-encoded-array> + Definition: u32 value representing time in microseconds + required for the CPU to be in the idle state to + break even in power consumption terms compared + to idle state idle_standby ([4][5]).To me this continues to be a bit illdefined. Say we have three states:
0,1,2. State 0 is theidle_standby. Providing a minimum residency for state 1 compared to state 0 sort of makes sense, but if we provide a minimum residency for state 2 compared to state 0 the break even time is going to be smaller than break even when comparing state 1 and state 2. With this data we'd enter state 2 when we'd be better off entering state 1.I am not sure I got your reply right, but min-residency for state 2 will be higher than state 1, since it has to cater for the dynamic power consumed by entering the state (but burns less power than state 1 when _in_ the state).
Entering a state has a power cost and min-residency should take that into account, worst-case as per other stats.
min-residency (and so the break-even) should take into account that entering the state is not for free.
Quoted 7 lines
I think that comparing against
idle_standbyis the only sane way we can define that parameter, either that or we remove it.Does it make sense ?
Thanks !
Lorenzo
Quoted 8 lines
The point is that if you compare breakeven between state 0 and state 2 the breakeven time will be smaller that when you compare the breakeven between state 1 and state 2. Assuming states ordered by "deepness" in the sense that deeper states have lower in-state power and longer entry/exit times.
I guess you could specify that the min-residency defines the time when the state breaks even compared to the previous (shallower) state.
I am not following Antti I am sorry. States are ordered in terms of power consumption which also means that deeper idle states have a longer required min-residency to break even against idle_standby in order to actually save power.
When we make a decision on what idle state to enter all we do, and that's OS agnostic, is predicting (+checking the next event) the next IRQ and see if it is worth entering a state or not. We have to compare it against a baseline, which is the processor being in standbywfi and that's what these bindings define.
I do not understand why you want to define min-residency against the previous shallower state.
What this binding says is: standbywfi is the shallower idle state in power consumption terms. Deeper idle states save more power than standbywfi if the residency in that state is at least min-residency.
I do not see where the problem is to be honest, maybe I need an example.
Thanks!
Lorenzo
RFC PATCH v4 3/3 Documentation: arm: define DT idle states bindings
From: Lorenzo Pieralisi <[email protected]>
Quoted 9 lines
When we make a decision on what idle state to enter all we do, and that's OS agnostic, is predicting (+checking the next event) the next IRQ and see if it is worth entering a state or not. We have to compare it against a baseline, which is the processor being in standbywfi and that's what these bindings define.
I do not understand why you want to define min-residency against the previous shallower state.
Quoted 8 lines
What this binding says is: standbywfi is the shallower idle state in power consumption terms. Deeper idle states save more power than standbywfi if the residency in that state is at least min-residency.
I do not see where the problem is to be honest, maybe I need an example.
Thanks!
Lorenzo
Sorry, I should have explained myself more clearly. I've been pondering about these issues somewhat lately so I'm perhaps suffering from a bit of a tunnel vision.
In short, when we choose an idle state based on expected idle duration we are not comparing wfi against all possible idle states in turn and making a decision between wfi and state X. Instead we want to choose among all states the one that gives minimum energy for the expected idle time. I'll try to elaborate..
Entering and exiting idle states takes time at nonzero power. To make up for this lost energy we indeed want the time in the idle state to be sufficiently long to make up for the lost energy. Now the important question here is "make up compared to what?".
The energy over the idle time can be also interpreted as average power. When the idle time increases the average power for a state approaches the in-state power. A deeper idle state would be a state with lower in-state power and longer entry/exit time. Therefore the average power for a deeper idle state drops slower as function of idle time than the average power for a shallower idle state. If we'd plot the average power for a number of idle states as function of idle duration, we'd get a set of "constant over idle time plus constant" style curves. Average power for state 0 will drop fastest close to the in-state power of state 0. Average power for state 1 will drop slower and approach the in-state power of state 1, average power for state 2 will drop even slower and approach the in-state power of state 3.
To define that the min-residency is the breakeven time against state 0 means that we are looking at the curves and asking "when does the average power for state X cross the average power for state 0?". But that would be the guideline for making a decision between state 0 and the state in question. Even if average power for state 2 is below the average power of state 0 it is not necessarily yet below the average power of state 1. To break even against state 1 the idle duration needs to be longer.
Yet another way to look at this: for three states we can define three times of interest:
- t1: the time when state1 breaks even against state0
- t2: the time when state2 breaks even against state0
- t3: the time when state2 breaks even against state1
and t3 would typically be larger than t2.
--Antti
RFC PATCH v4 3/3 Documentation: arm: define DT idle states bindings
Quoted 56 lines · Antti P Miettinen
From: Lorenzo Pieralisi <[email protected]>
Quoted 9 lines
When we make a decision on what idle state to enter all we do, and that's OS agnostic, is predicting (+checking the next event) the next IRQ and see if it is worth entering a state or not. We have to compare it against a baseline, which is the processor being in standbywfi and that's what these bindings define.
I do not understand why you want to define min-residency against the previous shallower state.
Quoted 8 lines
What this binding says is: standbywfi is the shallower idle state in power consumption terms. Deeper idle states save more power than standbywfi if the residency in that state is at least min-residency.
I do not see where the problem is to be honest, maybe I need an example.
Thanks!
LorenzoSorry, I should have explained myself more clearly. I've been pondering about these issues somewhat lately so I'm perhaps suffering from a bit of a tunnel vision.
In short, when we choose an idle state based on expected idle duration we are not comparing wfi against all possible idle states in turn and making a decision between wfi and state X. Instead we want to choose among all states the one that gives minimum energy for the expected idle time. I'll try to elaborate..
Entering and exiting idle states takes time at nonzero power. To make up for this lost energy we indeed want the time in the idle state to be sufficiently long to make up for the lost energy. Now the important question here is "make up compared to what?".
The energy over the idle time can be also interpreted as average power. When the idle time increases the average power for a state approaches the in-state power. A deeper idle state would be a state with lower in-state power and longer entry/exit time. Therefore the average power for a deeper idle state drops slower as function of idle time than the average power for a shallower idle state. If we'd plot the average power for a number of idle states as function of idle duration, we'd get a set of "constant over idle time plus constant" style curves. Average power for state 0 will drop fastest close to the in-state power of state 0. Average power for state 1 will drop slower and approach the in-state power of state 1, average power for state 2 will drop even slower and approach the in-state power of state 3.
To define that the min-residency is the breakeven time against state 0 means that we are looking at the curves and asking "when does the average power for state X cross the average power for state 0?". But that would be the guideline for making a decision between state 0 and the state in question. Even if average power for state 2 is below the average power of state 0 it is not necessarily yet below the average power of state 1. To break even against state 1 the idle duration needs to be longer.
Quoted 6 lines
Yet another way to look at this: for three states we can define three times of interest:
- t1: the time when state1 breaks even against state0
- t2: the time when state2 breaks even against state0
- t3: the time when state2 breaks even against state1
and t3 would typically be larger than t2.
Now it is crystal clear, and you are absolutely right, sorry for misunderstanding.
Help me define it then please:
- min-residency-us
"u32 value representing time in microseconds required for the CPU to be in the idle state to guarantee power savings maximization".
Rather vague (on purpose), if anyone comes up with a better definition please shout.
Thanks !
Lorenzo