ARM: sun7i/sun6i: irqchip: Irqchip driver for NMI
v4 cover ARM: sun7i/sun6i: irqchip: Irqchip driver for NMI
Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI. Three register are present to (un)mask, control and acknowledge NMI. These two patches add a new irqchip driver in cascade with GIC.
Changes since v1:
- added binding document
Changes since v2:
- fixed trigger type in DTS
- new explanations in binding documentation
- added support for A31 (sun6i)
Changes since v3:
- changed compatibles
Carlo Caione (3):
ARM: sun7i/sun6i: irqchip: Add irqchip driver for NMI controller
ARM: sun7i/sun6i: dts: Add NMI irqchip support
ARM: sun7i/sun6i: irqchip: Update the documentation
.../allwinner,sun67i-sc-nmi.txt | 27 +++ arch/arm/boot/dts/sun6i-a31.dtsi | 9 + arch/arm/boot/dts/sun7i-a20.dtsi | 9 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sunxi-nmi.c | 228 +++++++++++++++++++++ 5 files changed, 274 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt create mode 100644 drivers/irqchip/irq-sunxi-nmi.c
Signature · 1 line
1.8.3.2
PATCH v4 1/3 ARM: sun7i/sun6i: irqchip: Add irqchip driver for NMI controller
Allwinner A20/A31 SoCs have special registers to control / (un)mask / acknowledge NMI. This NMI controller is separated and independent from GIC. This patch adds a new irqchip to manage NMI.
--- drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sunxi-nmi.c | 228 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 229 insertions(+) create mode 100644 drivers/irqchip/irq-sunxi-nmi.c
drivers/irqchip/Makefile +1 -0
@@ -11,6 +11,7 @@ obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o obj-$(CONFIG_ARCH_MOXART) += irq-moxart.o obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o +obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o obj-$(CONFIG_ARM_GIC) += irq-gic.o obj-$(CONFIG_ARM_NVIC) += irq-nvic.o
drivers/irqchip/irq-sunxi-nmi.c new file +228 -0
228 lines not on this page · raw message
Signature · 1 line
1.8.3.2
PATCH v4 1/3 ARM: sun7i/sun6i: irqchip: Add irqchip driver for NMI controller
Hi Carlo,
Quoted 5 lines · Carlo Caione
Allwinner A20/A31 SoCs have special registers to control / (un)mask / acknowledge NMI. This NMI controller is separated and independent from GIC. This patch adds a new irqchip to manage NMI.
Signed-off-by Carlo Caione <[email protected]>
Thanks!
Maxime
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140303/2c0a8c14/attachment.sig>
PATCH v4 2/3 ARM: sun7i/sun6i: dts: Add NMI irqchip support
In reply to Carlo CaioneThis patch adds DTS entries for NMI controller as child of GIC.
--- arch/arm/boot/dts/sun6i-a31.dtsi | 9 +++++++++ arch/arm/boot/dts/sun7i-a20.dtsi | 9 +++++++++ 2 files changed, 18 insertions(+)
arch/arm/boot/dts/sun6i-a31.dtsi +9 -0
@@ -190,6 +190,15 @@ #size-cells = <1>; ranges; + nmi_intc: sc-nmi-intc at 01f00c0c { + compatible = "allwinner,sun6i-a31-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01f00c0c 0x38>; + interrupt-parent = <&gic>; + interrupts = <0 0 4>; + }; + pio: pinctrl at 01c20800 { compatible = "allwinner,sun6i-a31-pinctrl"; reg = <0x01c20800 0x400>;
arch/arm/boot/dts/sun7i-a20.dtsi +9 -0
@@ -310,6 +310,15 @@ #size-cells = <1>; ranges; + nmi_intc: sc-nmi-intc at 01c00030 { + compatible = "allwinner,sun7i-a20-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>; + interrupt-parent = <&gic>; + interrupts = <0 0 4>; + }; + emac: ethernet at 01c0b000 { compatible = "allwinner,sun4i-emac"; reg = <0x01c0b000 0x1000>;
Signature · 1 line
1.8.3.2
PATCH v4 3/3 ARM: sun7i/sun6i: irqchip: Update the documentation
In reply to Carlo CaioneAdded documentation for NMI irqchip.
--- .../allwinner,sun67i-sc-nmi.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt new file +27 -0
@@ -0,0 +1,27 @@ +Allwinner Sunxi NMI Controller +============================== + +Required properties: + +- compatible : should be "allwinner,sun7i-a20-sc-nmi" or + "allwinner,sun6i-a31-sc-nmi" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 2. The first cell is the IRQ number, the + second cell the trigger type. +- interrupt-parent: Specifies the parent interrupt controller. +- interrupts: Specifies the list of interrupt lines which are handled by + the interrupt controller in the parent controller's notation. This value + shall be the NMI. + +Example: + +sc-nmi-intc at 01c00030 { + compatible = "allwinner,sun7i-a20-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>; + interrupt-parent = <&gic>; + interrupts = <0 0 4>; +};
Signature · 1 line
1.8.3.2
PATCH v4 3/3 ARM: sun7i/sun6i: irqchip: Update the documentation
Hi,
Quoted 16 lines · Carlo Caione
Added documentation for NMI irqchip.
Signed-off-by Carlo Caione <[email protected]>--- .../allwinner,sun67i-sc-nmi.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txtDocumentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt new file +2
-0@@ -0,0 +1,27 @@ +Allwinner Sunxi NMI Controller +==============================
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt line 12
Quoted 10 lines
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt new file +10
-0+ +Required properties: + +- compatible : should be "allwinner,sun7i-a20-sc-nmi" or + "allwinner,sun6i-a31-sc-nmi" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 2. The first cell is the IRQ number, the + second cell the trigger type.
What values correspond to what trigger type? What are the accepted values?
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt line 16
Quoted 4 lines
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt new file +4
-0+- interrupt-parent: Specifies the parent interrupt controller. +- interrupts: Specifies the list of interrupt lines which are handled by + the interrupt controller in the parent controller's notation. This value + shall be the NMI.
Hmmm, there's only one interrupt, not a list of them.
Quoted 14 lines
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt new file +11
-0+ +Example: + +sc-nmi-intc at 01c00030 { + compatible = "allwinner,sun7i-a20-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c00030 0x0c>; + interrupt-parent = <&gic>; + interrupts = <0 0 4>; +};Signature · 1 line
1.8.3.2
Thanks!
Maxime
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140303/96759468/attachment.sig>
[linux-sunxi] Re: [PATCH v4 3/3] ARM: sun7i/sun6i: irqchip: Update the documentation
Quoted 32 lines · Maxime Ripard
Hi,
Quoted 16 lines · Carlo Caione
Added documentation for NMI irqchip.
Signed-off-by Carlo Caione <[email protected]>--- .../allwinner,sun67i-sc-nmi.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txtDocumentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt new file +2
-0@@ -0,0 +1,27 @@ +Allwinner Sunxi NMI Controller +==============================Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt line 12
Quoted 10 lines
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt new file +10
-0+ +Required properties: + +- compatible : should be "allwinner,sun7i-a20-sc-nmi" or + "allwinner,sun6i-a31-sc-nmi" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 2. The first cell is the IRQ number, the + second cell the trigger type.What values correspond to what trigger type? What are the accepted values?
Quoted 6 lines
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt line 16
Quoted 4 lines
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt new file +4
-0+- interrupt-parent: Specifies the parent interrupt controller. +- interrupts: Specifies the list of interrupt lines which are handled by + the interrupt controller in the parent controller's notation. This value + shall be the NMI.Hmmm, there's only one interrupt, not a list of them.
Fix for both in v5.
Thank you,
Signature · 1 line
Carlo Caione