ARM: OMAP2 DT clock conversion
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cover ARM: OMAP2 DT clock conversion
Hi,
This set concludes the omap2+ clock DT conversion work by creating the DT clock data for omap2 SoC also.
I am also currently doing related work to cleanup CM/PRM codebase in preparation to move it into drivers/, this set is basically going to be a pre-requisite for that. I'll hopefully post something related to that early next week.
This set has been boot tested on OMAP2430 only (thanks Nishanth, I don't have access to OMAP2 hardware myself), so any testing feedback on 2420 board(s) would be appreciated.
Working tree:
Tree: https://github.com/t-kristo/linux-pm.git
Branch: 3.14-rc4-omap2-dt-clks
-Tero
PATCH 1/12 ARM: OMAP2: convert sys_ck and osc_ck to standard clock types
osc_ck can be simply defined as a multiplexer clock, and the sys_ck can be a simple divider.
Signed-off-by Tero Kristo <[email protected]>
--- arch/arm/mach-omap2/Makefile | 3 +- arch/arm/mach-omap2/cclock2420_data.c | 52 +++++++++++++------------ arch/arm/mach-omap2/cclock2430_data.c | 60 +++++++++++++++------------- arch/arm/mach-omap2/clkt2xxx_osc.c | 69 --------------------------------- arch/arm/mach-omap2/clkt2xxx_sys.c | 47 ---------------------- arch/arm/mach-omap2/clock2xxx.h | 2 - arch/arm/mach-omap2/cm-regbits-24xx.h | 1 + arch/arm/mach-omap2/pm24xx.c | 4 ++ 8 files changed, 67 insertions(+), 171 deletions(-) delete mode 100644 arch/arm/mach-omap2/clkt2xxx_osc.c delete mode 100644 arch/arm/mach-omap2/clkt2xxx_sys.c
arch/arm/mach-omap2/Makefile +1 -2
@@ -173,10 +173,9 @@ obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o # Clock framework obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o +obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o obj-$(CONFIG_SOC_OMAP2420) += cclock2420_data.o obj-$(CONFIG_SOC_OMAP2430) += clock2430.o cclock2430_data.o
arch/arm/mach-omap2/cclock2420_data.c +28 -24
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arch/arm/mach-omap2/cclock2430_data.c +33 -27
95 lines not on this page · raw message
arch/arm/mach-omap2/clkt2xxx_osc.c deleted +0 -69
69 lines not on this page · raw message
arch/arm/mach-omap2/clkt2xxx_sys.c deleted +0 -47
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arch/arm/mach-omap2/clock2xxx.h +0 -2
@@ -49,8 +49,6 @@ int omap2430_clk_init(void);#define omap2430_clk_init () do { } while(0)#endif -extern void __iomem *prcm_clksrc_ctrl; -extern struct clk_hw *dclk_hw;int omap2_enable_osc_ck (struct clk_hw *hw);void omap2_disable_osc_ck (struct clk_hw *hw);
arch/arm/mach-omap2/cm-regbits-24xx.h +1 -0
@@ -107,6 +107,7 @@#define OMAP24XX_AUTO_DPLL_SHIFT 0#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)#define OMAP24XX_APLLS_CLKIN_SHIFT 23 +#define OMAP24XX_APLLS_CLKIN_WIDTH 3#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23)#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12)#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
arch/arm/mach-omap2/pm24xx.c +4 -0
@@ -251,6 +251,10 @@ static void __init prcm_setup_regs(void)/* Enable wake-up events */ omap2_prm_write_mod_reg (OMAP24XX_EN_GPIOS_MASK |OMAP24XX_EN_GPT1_MASK ,WKUP_MOD ,PM_WKEN ); + +/* Enable SYS_CLKEN control when all domains idle */ +omap2_prm_set_mod_reg_bits (OMAP_AUTOEXTCLKMODE_MASK ,OMAP24XX_GR_MOD , +OMAP2_PRCM_CLKSRC_CTRL_OFFSET ); }int __init omap2_pm_init (void )
Signature · 1 line
1.7.9.5
PATCH 2/12 ARM: OMAP2420: clock: get rid of fixed-div property use
In reply to Tero KristoCleans up the code a bit and is useful for clock data DT conversion.
Signed-off-by Tero Kristo <[email protected]>
--- arch/arm/mach-omap2/cclock2420_data.c | 15 ++++----------- arch/arm/mach-omap2/clock.c | 21 --------------------- arch/arm/mach-omap2/clock.h | 3 --- 3 files changed, 4 insertions(+), 35 deletions(-)
arch/arm/mach-omap2/cclock2420_data.c +4 -11
@@ -1025,18 +1025,12 @@ DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel,OMAP2420_EN_IVA_COP_SHIFT , &clkhwops_wait, dsp_fck_parent_names, dsp_fck_ops); +DEFINE_CLK_FIXED_FACTOR (iva1_ifck_div,"iva1_ifck" , &iva1_ifck,0x0 ,1 ,2 ); +static struct clk iva1_mpu_int_ifck;static const char *iva1_mpu_int_ifck_parent_names[] = { -"iva1_ifck" , -}; - -static const struct clk_ops iva1_mpu_int_ifck_ops = { - .init = &omap2_init_clk_clkdm, - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap_fixed_divisor_recalc, +"iva1_ifck_div" , };static struct clk_hw_omap iva1_mpu_int_ifck_hw = {
@@ -1047,11 +1041,10 @@ static struct clk_hw_omap iva1_mpu_int_ifck_hw = { .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, .clkdm_name = "iva1_clkdm", - .fixed_div = 2, };DEFINE_STRUCT_CLK (iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names, - iva1_mpu_int_ifck_ops); + aes_ick_ops);static struct clk mailboxes_ick;
arch/arm/mach-omap2/clock.c +0 -21
@@ -82,27 +82,6 @@ u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) }/* -* Used for clocks that have the same value as the parent clock, -* divided by some factor -*/ -unsigned long omap_fixed_divisor_recalc (struct clk_hw *hw, -unsigned long parent_rate) -{ -struct clk_hw_omap *oclk; - -if (!hw) { -pr_warn ("%s: hw is NULL\n" , __func__); -return -EINVAL ; - } - - oclk =to_clk_hw_omap (hw); - -WARN_ON (!oclk->fixed_div); - -return parent_rate / oclk->fixed_div; -} - -/* * OMAP2+ specific clock functions */
arch/arm/mach-omap2/clock.h +0 -3
@@ -189,9 +189,6 @@ struct clk_hw_omap_ops {void (*deny_idle)(struct clk_hw_omap *oclk); }; -unsigned long omap_fixed_divisor_recalc (struct clk_hw *hw, -unsigned long parent_rate); -/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ #define CORE_CLK_SRC_32K 0x0#define CORE_CLK_SRC_DPLL 0x1
Signature · 1 line
1.7.9.5
PATCH 3/12 CLK: TI: DPLL: simplify autoidle register detection logic
In reply to Tero KristoAMxxxx dpll_data previously had autoidle_mask set, even if these SoC:s don't have autoidle register. Remove the bit-field value as it is unused, also drop the unnecessary DPLL_HAS_AUTOIDLE flag passing during init, as we can just simply check against the contents of the autoidle_mask.
Signed-off-by Tero Kristo <[email protected]>
--- drivers/clk/ti/dpll.c | 39 +++++++++++++++------------------------ 1 file changed, 15 insertions(+), 24 deletions(-)
drivers/clk/ti/dpll.c +15 -24
@@ -25,8 +25,6 @@#undef pr_fmt#define pr_fmt (fmt) "%s: " fmt, __func__ -#define DPLL_HAS_AUTOIDLE 0x1 -#if defined(CONFIG_ARCH_OMAP4 ) || defined(CONFIG_SOC_OMAP5 ) || \ defined(CONFIG_SOC_DRA7XX ) static const struct clk_ops dpll_m4xen_ck_ops = {
@@ -193,14 +191,12 @@ static void ti_clk_register_dpll_x2(struct device_node *node,* @node: device node containing the DPLL info * @ops: ops for the DPLL * @ddt: DPLL data template to use -* @init_flags: flags for controlling init types * * Initializes a DPLL clock from device tree data. */ static void __init of_ti_dpll_setup (struct device_node *node,const struct clk_ops *ops, -const struct dpll_data *ddt, -u8 init_flags) +const struct dpll_data *ddt) {struct clk_hw_omap *clk_hw =NULL ;struct clk_init_data *init =NULL ;
@@ -247,7 +243,7 @@ static void __init of_ti_dpll_setup(struct device_node *node,if (!dd->control_reg || !dd->idlest_reg || !dd->mult_div1_reg) goto cleanup; -if (init_flags &DPLL_HAS_AUTOIDLE ) { +if (dd->autoidle_mask) { dd->autoidle_reg =ti_clk_get_reg_addr (node,3 );if (!dd->autoidle_reg) goto cleanup;
@@ -310,7 +306,7 @@ static void __init of_ti_omap3_dpll_setup(struct device_node *node) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; -of_ti_dpll_setup (node, &omap3_dpll_ck_ops, &dd,DPLL_HAS_AUTOIDLE ); +of_ti_dpll_setup (node, &omap3_dpll_ck_ops, &dd); }CLK_OF_DECLARE (ti_omap3_dpll_clock,"ti,omap3-dpll-clock" , of_ti_omap3_dpll_setup);
@@ -329,7 +325,7 @@ static void __init of_ti_omap3_core_dpll_setup(struct device_node *node) .freqsel_mask = 0xf0, }; -of_ti_dpll_setup (node, &omap3_dpll_core_ck_ops, &dd,DPLL_HAS_AUTOIDLE ); +of_ti_dpll_setup (node, &omap3_dpll_core_ck_ops, &dd); }CLK_OF_DECLARE (ti_omap3_core_dpll_clock,"ti,omap3-dpll-core-clock" , of_ti_omap3_core_dpll_setup);
@@ -349,7 +345,7 @@ static void __init of_ti_omap3_per_dpll_setup(struct device_node *node) .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), }; -of_ti_dpll_setup (node, &omap3_dpll_per_ck_ops, &dd,DPLL_HAS_AUTOIDLE ); +of_ti_dpll_setup (node, &omap3_dpll_per_ck_ops, &dd); }CLK_OF_DECLARE (ti_omap3_per_dpll_clock,"ti,omap3-dpll-per-clock" , of_ti_omap3_per_dpll_setup);
@@ -371,7 +367,7 @@ static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node) .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), }; -of_ti_dpll_setup (node, &omap3_dpll_per_ck_ops, &dd,DPLL_HAS_AUTOIDLE ); +of_ti_dpll_setup (node, &omap3_dpll_per_ck_ops, &dd); }CLK_OF_DECLARE (ti_omap3_per_jtype_dpll_clock,"ti,omap3-dpll-per-j-type-clock" , of_ti_omap3_per_jtype_dpll_setup);
@@ -391,7 +387,7 @@ static void __init of_ti_omap4_dpll_setup(struct device_node *node) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; -of_ti_dpll_setup (node, &dpll_ck_ops, &dd,DPLL_HAS_AUTOIDLE ); +of_ti_dpll_setup (node, &dpll_ck_ops, &dd); }CLK_OF_DECLARE (ti_omap4_dpll_clock,"ti,omap4-dpll-clock" , of_ti_omap4_dpll_setup);
@@ -410,7 +406,7 @@ static void __init of_ti_omap4_core_dpll_setup(struct device_node *node) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; -of_ti_dpll_setup (node, &dpll_core_ck_ops, &dd,DPLL_HAS_AUTOIDLE ); +of_ti_dpll_setup (node, &dpll_core_ck_ops, &dd); }CLK_OF_DECLARE (ti_omap4_core_dpll_clock,"ti,omap4-dpll-core-clock" , of_ti_omap4_core_dpll_setup);
@@ -433,7 +429,7 @@ static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; -of_ti_dpll_setup (node, &dpll_m4xen_ck_ops, &dd,DPLL_HAS_AUTOIDLE ); +of_ti_dpll_setup (node, &dpll_m4xen_ck_ops, &dd); }CLK_OF_DECLARE (ti_omap4_m4xen_dpll_clock,"ti,omap4-dpll-m4xen-clock" , of_ti_omap4_m4xen_dpll_setup);
@@ -454,7 +450,7 @@ static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; -of_ti_dpll_setup (node, &dpll_m4xen_ck_ops, &dd,DPLL_HAS_AUTOIDLE ); +of_ti_dpll_setup (node, &dpll_m4xen_ck_ops, &dd); }CLK_OF_DECLARE (ti_omap4_jtype_dpll_clock,"ti,omap4-dpll-j-type-clock" , of_ti_omap4_jtype_dpll_setup);
@@ -465,7 +461,6 @@ static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)const struct dpll_data dd = { .idlest_mask =0x1 , .enable_mask =0x7 , - .autoidle_mask =0x7 , .mult_mask =0x7ff <<8 , .div1_mask =0x7f , .max_multiplier =2047 ,
@@ -474,7 +469,7 @@ static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; -of_ti_dpll_setup (node, &dpll_no_gate_ck_ops, &dd,0 ); +of_ti_dpll_setup (node, &dpll_no_gate_ck_ops, &dd); }CLK_OF_DECLARE (ti_am3_no_gate_dpll_clock,"ti,am3-dpll-no-gate-clock" , of_ti_am3_no_gate_dpll_setup);
@@ -484,7 +479,6 @@ static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)const struct dpll_data dd = { .idlest_mask =0x1 , .enable_mask =0x7 , - .autoidle_mask =0x7 , .mult_mask =0x7ff <<8 , .div1_mask =0x7f , .max_multiplier =4095 ,
@@ -494,7 +488,7 @@ static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; -of_ti_dpll_setup (node, &dpll_ck_ops, &dd,0 ); +of_ti_dpll_setup (node, &dpll_ck_ops, &dd); }CLK_OF_DECLARE (ti_am3_jtype_dpll_clock,"ti,am3-dpll-j-type-clock" , of_ti_am3_jtype_dpll_setup);
@@ -504,7 +498,6 @@ static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)const struct dpll_data dd = { .idlest_mask =0x1 , .enable_mask =0x7 , - .autoidle_mask =0x7 , .mult_mask =0x7ff <<8 , .div1_mask =0x7f , .max_multiplier =2047 ,
@@ -514,7 +507,7 @@ static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; -of_ti_dpll_setup (node, &dpll_no_gate_ck_ops, &dd,0 ); +of_ti_dpll_setup (node, &dpll_no_gate_ck_ops, &dd); } CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock, "ti,am3-dpll-no-gate-j-type-clock",
@@ -525,7 +518,6 @@ static void __init of_ti_am3_dpll_setup(struct device_node *node)const struct dpll_data dd = { .idlest_mask =0x1 , .enable_mask =0x7 , - .autoidle_mask =0x7 , .mult_mask =0x7ff <<8 , .div1_mask =0x7f , .max_multiplier =2047 ,
@@ -534,7 +526,7 @@ static void __init of_ti_am3_dpll_setup(struct device_node *node) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; -of_ti_dpll_setup (node, &dpll_ck_ops, &dd,0 ); +of_ti_dpll_setup (node, &dpll_ck_ops, &dd); }CLK_OF_DECLARE (ti_am3_dpll_clock,"ti,am3-dpll-clock" , of_ti_am3_dpll_setup);
@@ -543,7 +535,6 @@ static void __init of_ti_am3_core_dpll_setup(struct device_node *node)const struct dpll_data dd = { .idlest_mask =0x1 , .enable_mask =0x7 , - .autoidle_mask =0x7 , .mult_mask =0x7ff <<8 , .div1_mask =0x7f , .max_multiplier =2047 ,
@@ -552,7 +543,7 @@ static void __init of_ti_am3_core_dpll_setup(struct device_node *node) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; -of_ti_dpll_setup (node, &dpll_core_ck_ops, &dd,0 ); +of_ti_dpll_setup (node, &dpll_core_ck_ops, &dd); }CLK_OF_DECLARE (ti_am3_core_dpll_clock,"ti,am3-dpll-core-clock" , of_ti_am3_core_dpll_setup);
Signature · 1 line
1.7.9.5
PATCH 4/12 CLK: TI: DPLL: add support for omap2 core dpll
In reply to Tero KristoOMAP2 has slightly different DPLL compared to later OMAP generations. This patch adds support for the ti,omap2-dpll-core-clock and also adds the bindings documentation.
Signed-off-by Tero Kristo <[email protected]>
--- .../devicetree/bindings/clock/ti/dpll.txt | 9 ++++ arch/arm/mach-omap2/clock.h | 1 - arch/arm/mach-omap2/clock2xxx.h | 4 -- drivers/clk/ti/dpll.c | 45 ++++++++++++++++++-- include/linux/clk/ti.h | 6 +++ 5 files changed, 57 insertions(+), 8 deletions(-)
Documentation/devicetree/bindings/clock/ti/dpll.txt +9 -0
@@ -30,6 +30,7 @@ Required properties: "ti,am3-dpll-clock", "ti,am3-dpll-core-clock", "ti,am3-dpll-x2-clock", + "ti,omap2-dpll-core-clock", - #clock-cells : from common clock binding; shall be set to 0. - clocks : link phandles of parent clocks, first entry lists reference clock
@@ -41,6 +42,7 @@ Required properties: "mult-div1" - contains the multiplier / divider register base address "autoidle" - contains the autoidle register base address (optional) ti,am3-* dpll types do not have autoidle register + ti,omap2-* dpll type does not support idlest / autoidle registers Optional properties: - DPLL mode setting - defining any one or more of the following overrides
@@ -73,3 +75,10 @@ Examples: clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x90>, <0x5c>, <0x68>; }; + + dpll_ck: dpll_ck { + #clock-cells = <0>; + compatible = "ti,omap2-dpll-core-clock"; + clocks = <&sys_ck>, <&sys_ck>; + reg = <0x0500>, <0x0540>; + };
arch/arm/mach-omap2/clock.h +0 -1
@@ -276,7 +276,6 @@ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;extern const struct clk_hw_omap_ops clkhwops_apll54;extern const struct clk_hw_omap_ops clkhwops_apll96; -extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;/* clksel_rate blocks shared between OMAP44xx and AM33xx */
arch/arm/mach-omap2/clock2xxx.h +0 -4
@@ -21,10 +21,6 @@ unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk, unsigned long parent_rate);unsigned long omap2_osc_clk_recalc (struct clk_hw *clk,unsigned long parent_rate); -unsigned long omap2_dpllcore_recalc (struct clk_hw *hw, -unsigned long parent_rate); -int omap2_reprogram_dpllcore (struct clk_hw *clk,unsigned long rate, -unsigned long parent_rate);void omap2xxx_clkt_dpllcore_init (struct clk_hw *hw);unsigned long omap2_clk_apll54_recalc (struct clk_hw *hw,unsigned long parent_rate);
drivers/clk/ti/dpll.c +42 -3
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include/linux/clk/ti.h +6 -0
@@ -255,6 +255,11 @@ int omap2_dflt_clk_enable(struct clk_hw *hw);void omap2_dflt_clk_disable (struct clk_hw *hw);int omap2_dflt_clk_is_enabled (struct clk_hw *hw);void omap3_clk_lock_dpll5 (void ); +unsigned long omap2_dpllcore_recalc (struct clk_hw *hw, +unsigned long parent_rate); +int omap2_reprogram_dpllcore (struct clk_hw *clk,unsigned long rate, +unsigned long parent_rate); +void omap2xxx_clkt_dpllcore_init (struct clk_hw *hw);void __iomem *ti_clk_get_reg_addr (struct device_node *node,int index);void ti_dt_clocks_register (struct ti_dt_clk *oclks);
@@ -283,6 +288,7 @@ static inline void of_ti_clk_allow_autoidle_all(void) { }static inline void of_ti_clk_deny_autoidle_all (void ) { }#endif +extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;extern const struct clk_hw_omap_ops clkhwops_wait;
Signature · 1 line
1.7.9.5
PATCH 5/12 CLK: TI: APLL: add support for omap2 aplls
In reply to Tero KristoThis patch adds support for omap2 type aplls, which have gating and autoidle functionality.
Signed-off-by Tero Kristo <[email protected]>
--- .../devicetree/bindings/clock/ti/apll.txt | 21 ++- arch/arm/mach-omap2/clock.h | 11 -- drivers/clk/ti/apll.c | 180 ++++++++++++++++++++ include/linux/clk/ti.h | 21 ++- 4 files changed, 216 insertions(+), 17 deletions(-)
Documentation/devicetree/bindings/clock/ti/apll.txt +16 -5
@@ -14,18 +14,29 @@ a subtype of a DPLL [2], although a simplified one at that. [2] Documentation/devicetree/bindings/clock/ti/dpll.txt Required properties: -- compatible : shall be "ti,dra7-apll-clock" +- compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock" - #clock-cells : from common clock binding; shall be set to 0. - clocks : link phandles of parent clocks (clk-ref and clk-bypass) - reg : address and length of the register set for controlling the APLL. It contains the information of registers in the following order: - "control" - contains the control register base address - "idlest" - contains the idlest register base address + "control" - contains the control register offset + "idlest" - contains the idlest register offset + "autoidle" - contains the autoidle register offset (OMAP2 only) Examples: - apll_pcie_ck: apll_pcie_ck at 4a008200 { + apll_pcie_ck: apll_pcie_ck { #clock-cells = <0>; clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; - reg = <0x4a00821c 0x4>, <0x4a008220 0x4>; + reg = <0x021c>, <0x0220>; compatible = "ti,dra7-apll-clock"; }; + + apll96_ck: apll96_ck { + #clock-cells = <0>; + compatible = "ti,omap2-apll-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <2>; + ti,idlest-shift = <8>; + ti,clock-frequency = <96000000>; + reg = <0x0500>, <0x0530>, <0x0520>; + };
arch/arm/mach-omap2/clock.h +0 -11
@@ -178,17 +178,6 @@ struct clksel {const struct clksel_rate *rates; }; -struct clk_hw_omap_ops { -void (*find_idlest)(struct clk_hw_omap *oclk, -void __iomem **idlest_reg, -u8 *idlest_bit,u8 *idlest_val); -void (*find_companion)(struct clk_hw_omap *oclk, -void __iomem **other_reg, -u8 *other_bit); -void (*allow_idle)(struct clk_hw_omap *oclk); -void (*deny_idle)(struct clk_hw_omap *oclk); -}; -/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ #define CORE_CLK_SRC_32K 0x0#define CORE_CLK_SRC_DPLL 0x1
drivers/clk/ti/apll.c +180 -0
183 lines not on this page · raw message
include/linux/clk/ti.h +20 -1
@@ -94,7 +94,26 @@ struct dpll_data {u8 flags; }; -struct clk_hw_omap_ops ; +struct clk_hw_omap ; + +/** +* struct clk_hw_omap_ops - OMAP clk ops +* @find_idlest: find idlest register information for a clock +* @find_companion: find companion clock register information for a clock, +* basically converts CM_ICLKEN* <-> CM_FCLKEN* +* @allow_idle: enables autoidle hardware functionality for a clock +* @deny_idle: prevent autoidle hardware functionality for a clock +*/ +struct clk_hw_omap_ops { +void (*find_idlest)(struct clk_hw_omap *oclk, +void __iomem **idlest_reg, +u8 *idlest_bit,u8 *idlest_val); +void (*find_companion)(struct clk_hw_omap *oclk, +void __iomem **other_reg, +u8 *other_bit); +void (*allow_idle)(struct clk_hw_omap *oclk); +void (*deny_idle)(struct clk_hw_omap *oclk); +};/** * struct clk_hw_omap - OMAP struct clk
Signature · 1 line
1.7.9.5
PATCH 5/12 CLK: TI: APLL: add support for omap2 aplls
On 02/28/2014 03:22 AM, Tero Kristo wrote:
[...]
Quoted 59 lines
drivers/clk/ti/apll.c +59
-0+static void __init of_omap2_apll_setup (struct device_node *node) +{ +struct dpll_data *ad =NULL ; +struct clk_hw_omap *clk_hw =NULL ; +struct clk_init_data *init =NULL ; +struct clk *clk; +const char *parent_name; +u32 val; + + ad =kzalloc (sizeof (*clk_hw),GFP_KERNEL ); + clk_hw =kzalloc (sizeof (*clk_hw),GFP_KERNEL ); + init =kzalloc (sizeof (*init),GFP_KERNEL ); + +if (!ad || !clk_hw || !init) + goto cleanup; + + clk_hw->dpll_data = ad; + clk_hw->hw.init = init; + init->ops = &omap2_apll_ops; + init->name = node->name; + clk_hw->ops = &omap2_apll_hwops; + + init->num_parents =of_clk_get_parent_count (node); +if (init->num_parents !=1 ) { +pr_err ("%s must have one parent\n" , node->name); + goto cleanup; + } + + parent_name =of_clk_get_parent_name (node,0 ); + init->parent_names = &parent_name; + +if (of_property_read_u32 (node,"ti,clock-frequency" , &val)) { +pr_err ("%s missing clock-frequency\n" , node->name); + goto cleanup; + } + clk_hw->fixed_rate = val; + +if (of_property_read_u32 (node,"ti,bit-shift" , &val)) { +pr_err ("%s missing bit-shift\n" , node->name); + goto cleanup; + } + + clk_hw->enable_bit = val; + ad->enable_mask =0x3 << val; + ad->autoidle_mask =0x3 << val; + +if (of_property_read_u32 (node,"ti,idlest-shift" , &val)) { +pr_err ("%s missing idlest-shift\n" , node->name); + goto cleanup; + } + + ad->idlest_mask =1 << val; + + ad->control_reg =ti_clk_get_reg_addr (node,0 ); + ad->autoidle_reg =ti_clk_get_reg_addr (node,1 ); + ad->idlest_reg =ti_clk_get_reg_addr (node,2 ); + +if (!ad->control_reg || !ad->autoidle_reg || !ad->idlest_reg) + goto cleanup;
drivers/clk/ti/apll.c cleanup: · line 400
Quoted 10 lines
drivers/clk/ti/apll.c +10
-0+ + clk =clk_register (NULL , &clk_hw->hw); +if (!IS_ERR (clk)) { +of_clk_add_provider (node, of_clk_src_simple_get, clk); +kfree (init); +return ; + } +cleanup: +kfree (clk_hw); +kfree (init);
kfree(ad)?
smatch reported (as part of the kernel_patch_verify_report:+drivers/clk/ti/apll.c:400 of_omap2_apll_setup() warn: possible memory leak of 'ad'
Signature · 2 lines
Regards, Nishanth Menon
PATCH 6/12 CLK: TI: gate: fixed DT binding documentation bugs
In reply to Tero Kristoti,composite-gate-clock documentation was missing, also the register offset examples were wrong.
Signed-off-by Tero Kristo <[email protected]>
--- .../devicetree/bindings/clock/ti/gate.txt | 29 +++++++++++++++++--- 1 file changed, 25 insertions(+), 4 deletions(-)
Documentation/devicetree/bindings/clock/ti/gate.txt +25 -4
@@ -25,6 +25,11 @@ Required properties: to map clockdomains properly "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling, required for a hardware errata + "ti,composite-gate-clock" - composite gate clock, to be part of composite + clock + "ti,composite-no-wait-gate-clock" - composite gate clock that does not wait + for clock to be active before returning + from clk_enable() - #clock-cells : from common clock binding; shall be set to 0 - clocks : link to phandle of parent clock - reg : offset for register controlling adjustable gate, not needed for
@@ -41,7 +46,7 @@ Examples: #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&core_96m_fck>; - reg = <0x48004a00 0x4>; + reg = <0x0a00>; ti,bit-shift = <25>; };
@@ -57,7 +62,7 @@ Examples: #clock-cells = <0>; compatible = "ti,dss-gate-clock"; clocks = <&dpll4_m4x2_ck>; - reg = <0x48004e00 0x4>; + reg = <0x0e00>; ti,bit-shift = <0>; };
@@ -65,7 +70,7 @@ Examples: #clock-cells = <0>; compatible = "ti,am35xx-gate-clock"; clocks = <&ipss_ick>; - reg = <0x4800259c 0x4>; + reg = <0x059c>; ti,bit-shift = <1>; };
@@ -80,6 +85,22 @@ Examples: compatible = "ti,hsdiv-gate-clock"; clocks = <&dpll4_m2x2_mul_ck>; ti,bit-shift = <0x1b>; - reg = <0x48004d00 0x4>; + reg = <0x0d00>; ti,set-bit-to-disable; }; + + vlynq_gate_fck: vlynq_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <3>; + reg = <0x0200>; + }; + + sys_clkout2_src_gate: sys_clkout2_src_gate { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <15>; + reg = <0x0070>; + };
Signature · 1 line
1.7.9.5
PATCH 7/12 CLK: TI: interface: add support for omap2430 specific interface clock
In reply to Tero KristoOMAP2430 I2CHS modules require specific hardware ops to be used, so added a new compatible string for this.
Signed-off-by Tero Kristo <[email protected]>
--- .../devicetree/bindings/clock/ti/interface.txt | 2 ++ arch/arm/mach-omap2/clock.h | 1 - drivers/clk/ti/interface.c | 7 +++++++ include/linux/clk/ti.h | 1 + 4 files changed, 10 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/clock/ti/interface.txt +2 -0
@@ -21,6 +21,8 @@ Required properties: "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling "ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling + "ti,omap2430-interface-clock" - interface clock with OMAP2430 specific HW + handling - #clock-cells : from common clock binding; shall be set to 0 - clocks : link to phandle of parent clock - reg : base address for the control register
arch/arm/mach-omap2/clock.h +0 -1
@@ -265,7 +265,6 @@ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;extern const struct clk_hw_omap_ops clkhwops_apll54;extern const struct clk_hw_omap_ops clkhwops_apll96; -extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;/* clksel_rate blocks shared between OMAP44xx and AM33xx */ extern const struct clksel_rate div_1_0_rates[];
drivers/clk/ti/interface.c +7 -0
@@ -123,3 +123,10 @@ static void __init of_ti_am35xx_interface_clk_setup(struct device_node *node) }CLK_OF_DECLARE (ti_am35xx_interface_clk,"ti,am35xx-interface-clock" , of_ti_am35xx_interface_clk_setup); + +static void __init of_ti_omap2430_interface_clk_setup (struct device_node *node) +{ +_of_ti_interface_clk_setup (node, &clkhwops_omap2430_i2chs_wait); +} +CLK_OF_DECLARE (ti_omap2430_interface_clk,"ti,omap2430-interface-clock" , + of_ti_omap2430_interface_clk_setup);
include/linux/clk/ti.h +1 -0
@@ -308,6 +308,7 @@ static inline void of_ti_clk_deny_autoidle_all(void) { }#endif extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; +extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;extern const struct clk_hw_omap_ops clkhwops_wait;
Signature · 1 line
1.7.9.5
PATCH 8/12 CLK: TI: OMAP2: add clock init support
In reply to Tero KristoAdds support for registering the alias clocks, boot time clock-enable list and disabling autoidle of clocks.
Signed-off-by Tero Kristo <[email protected]>
--- drivers/clk/ti/Makefile | 1 + drivers/clk/ti/clk-2xxx.c | 254 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/clk/ti.h | 2 + 3 files changed, 257 insertions(+) create mode 100644 drivers/clk/ti/clk-2xxx.c
drivers/clk/ti/Makefile +1 -0
@@ -3,6 +3,7 @@ obj-y += clk.o autoidle.o clockdomain.o clk-common = dpll.o composite.o divider.o gate.o \ fixed-factor.o mux.o apll.o obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o +obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) clk-2xxx.o obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o clk-3xxx.o obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o
drivers/clk/ti/clk-2xxx.c new file +254 -0
254 lines not on this page · raw message
include/linux/clk/ti.h +2 -0
@@ -298,6 +298,8 @@ int omap5xxx_dt_clk_init(void);int dra7xx_dt_clk_init (void );int am33xx_dt_clk_init (void );int am43xx_dt_clk_init (void ); +int omap2420_dt_clk_init (void ); +int omap2430_dt_clk_init (void );#ifdef CONFIG_OF void of_ti_clk_allow_autoidle_all (void );
Signature · 1 line
1.7.9.5
PATCH 9/12 ARM: dts: omap2 clock data
In reply to Tero KristoThis patch creates a unique node for each clock in the OMAP2 power, reset and clock manager (PRCM).
Signed-off-by Tero Kristo <[email protected]>
--- arch/arm/boot/dts/omap2420-clocks.dtsi | 270 +++++++ arch/arm/boot/dts/omap2420.dtsi | 29 + arch/arm/boot/dts/omap2430-clocks.dtsi | 344 +++++++++ arch/arm/boot/dts/omap2430.dtsi | 29 + arch/arm/boot/dts/omap24xx-clocks.dtsi | 1238 ++++++++++++++++++++++++++++++++ 5 files changed, 1910 insertions(+) create mode 100644 arch/arm/boot/dts/omap2420-clocks.dtsi create mode 100644 arch/arm/boot/dts/omap2430-clocks.dtsi create mode 100644 arch/arm/boot/dts/omap24xx-clocks.dtsi
arch/arm/boot/dts/omap2420-clocks.dtsi new file +270 -0
@@ -0,0 +1,270 @@ +/* + * Device Tree Source for OMAP2420 clock data + * + * Copyright (C) 2014 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&prcm_clocks { + sys_clkout2_src_gate: sys_clkout2_src_gate { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <15>; + reg = <0x0070>; + }; + + sys_clkout2_src_mux: sys_clkout2_src_mux { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>; + ti,bit-shift = <8>; + reg = <0x0070>; + }; + + sys_clkout2_src: sys_clkout2_src { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>; + }; + + sys_clkout2: sys_clkout2 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sys_clkout2_src>; + ti,bit-shift = <11>; + ti,max-div = <64>; + reg = <0x0070>; + ti,index-power-of-two; + }; + + dsp_gate_ick: dsp_gate_ick { + #clock-cells = <0>; + compatible = "ti,composite-interface-clock"; + clocks = <&dsp_fck>; + ti,bit-shift = <1>; + reg = <0x0810>; + }; + + dsp_div_ick: dsp_div_ick { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&dsp_fck>; + ti,bit-shift = <5>; + ti,max-div = <3>; + reg = <0x0840>; + ti,index-starts-at-one; + }; + + dsp_ick: dsp_ick { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&dsp_gate_ick>, <&dsp_div_ick>; + }; + + iva1_gate_ifck: iva1_gate_ifck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <10>; + reg = <0x0800>; + }; + + iva1_div_ifck: iva1_div_ifck { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&core_ck>; + ti,bit-shift = <8>; + reg = <0x0840>; + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>; + }; + + iva1_ifck: iva1_ifck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>; + }; + + iva1_ifck_div: iva1_ifck_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&iva1_ifck>; + clock-mult = <1>; + clock-div = <2>; + }; + + iva1_mpu_int_ifck: iva1_mpu_int_ifck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&iva1_ifck_div>; + ti,bit-shift = <8>; + reg = <0x0800>; + }; + + wdt3_ick: wdt3_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <28>; + reg = <0x0210>; + }; + + wdt3_fck: wdt3_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <28>; + reg = <0x0200>; + }; + + mmc_ick: mmc_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <26>; + reg = <0x0210>; + }; + + mmc_fck: mmc_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_96m_ck>; + ti,bit-shift = <26>; + reg = <0x0200>; + }; + + eac_ick: eac_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <24>; + reg = <0x0210>; + }; + + eac_fck: eac_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_96m_ck>; + ti,bit-shift = <24>; + reg = <0x0200>; + }; + + i2c1_fck: i2c1_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_12m_ck>; + ti,bit-shift = <19>; + reg = <0x0200>; + }; + + i2c2_fck: i2c2_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_12m_ck>; + ti,bit-shift = <20>; + reg = <0x0200>; + }; + + vlynq_ick: vlynq_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l3_ck>; + ti,bit-shift = <3>; + reg = <0x0210>; + }; + + vlynq_gate_fck: vlynq_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <3>; + reg = <0x0200>; + }; + + core_d18_ck: core_d18_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <18>; + }; + + vlynq_mux_fck: vlynq_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>, <&core_d18_ck>; + ti,bit-shift = <15>; + reg = <0x0240>; + }; + + vlynq_fck: vlynq_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>; + }; +}; + +&prcm_clockdomains { + gfx_clkdm: gfx_clkdm { + compatible = "ti,clockdomain"; + clocks = <&gfx_ick>; + }; + + core_l3_clkdm: core_l3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>; + }; + + wkup_clkdm: wkup_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>, + <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>, + <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>; + }; + + iva1_clkdm: iva1_clkdm { + compatible = "ti,clockdomain"; + clocks = <&iva1_mpu_int_ifck>; + }; + + dss_clkdm: dss_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dss_ick>, <&dss_54m_fck>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>, + <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>, + <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>, + <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>, + <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>, + <&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, + <&uart3_ick>, <&uart3_fck>, <&cam_ick>, + <&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>, + <&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>, + <&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>, + <&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>, + <&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>, + <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>, + <&pka_ick>; + }; +}; + +&func_96m_ck { + compatible = "fixed-factor-clock"; + clocks = <&apll96_ck>; + clock-mult = <1>; + clock-div = <1>; +}; + +&dsp_div_fck { + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>; +}; + +&ssi_ssr_sst_div_fck { + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; +};
arch/arm/boot/dts/omap2420.dtsi +29 -0
@@ -14,6 +14,32 @@ compatible = "ti,omap2420", "ti,omap2"; ocp { + prcm: prcm at 48008000 { + compatible = "ti,omap2-prcm"; + reg = <0x48008000 0x1000>; + + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; + + scrm: scrm at 48000000 { + compatible = "ti,omap2-scrm"; + reg = <0x48000000 0x1000>; + + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scrm_clockdomains: clockdomains { + }; + }; + counter32k: counter at 48004000 { compatible = "ti,omap-counter32k"; reg = <0x48004000 0x20>;
@@ -146,3 +172,6 @@ &i2c2 { compatible = "ti,omap2420-i2c"; }; + +/include/ "omap24xx-clocks.dtsi" +/include/ "omap2420-clocks.dtsi"
arch/arm/boot/dts/omap2430-clocks.dtsi new file +344 -0
344 lines not on this page · raw message
arch/arm/boot/dts/omap2430.dtsi +29 -0
@@ -14,6 +14,32 @@ compatible = "ti,omap2430", "ti,omap2"; ocp { + prcm: prcm at 49006000 { + compatible = "ti,omap2-prcm"; + reg = <0x49006000 0x1000>; + + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; + + scrm: scrm at 49002000 { + compatible = "ti,omap2-scrm"; + reg = <0x49002000 0x1000>; + + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scrm_clockdomains: clockdomains { + }; + }; + counter32k: counter at 49020000 { compatible = "ti,omap-counter32k"; reg = <0x49020000 0x20>;
@@ -233,3 +259,6 @@ &i2c2 { compatible = "ti,omap2430-i2c"; }; + +/include/ "omap24xx-clocks.dtsi" +/include/ "omap2430-clocks.dtsi"
arch/arm/boot/dts/omap24xx-clocks.dtsi new file +1238 -0
1,238 lines not on this page · raw message
Signature · 1 line
1.7.9.5
PATCH 10/12 ARM: OMAP2: clock: add DT boot support for cpufreq_ck
In reply to Tero KristoThe clock and clkdev for this are added manually.
Signed-off-by Tero Kristo <[email protected]>
--- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 46 ++++++++++++++++++++++++++ drivers/clk/ti/clk-2xxx.c | 2 ++ include/linux/clk/ti.h | 1 + 3 files changed, 49 insertions(+)
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +53 -0
@@ -208,3 +208,56 @@ void omap2xxx_clkt_vps_late_init(void)clk_put (c); } } + +#ifdef CONFIG_OF +#include <linux/clk-provider.h> +#include <linux/clkdev.h> + +static const struct clk_ops virt_prcm_set_ops = { + .recalc_rate = &omap2_table_mpu_recalc, + .set_rate = &omap2_select_table_rate, + .round_rate = &omap2_round_to_table_rate, +}; + +/** +* omap2xxx_clkt_vps_init - initialize virt_prcm_set clock +* +* Does a manual init for the virtual prcm DVFS clock for OMAP2. This +* function is called only from omap2 DT clock init, as the virtual +* node is not modelled in the DT clock data. +*/ +void omap2xxx_clkt_vps_init (void ) +{ +struct clk_init_data init = {NULL }; +struct clk_hw_omap *hw =NULL ; +struct clk *clk; +const char *parent_name ="mpu_ck" ; +struct clk_lookup *lookup =NULL ; + +omap2xxx_clkt_vps_late_init (); +omap2xxx_clkt_vps_check_bootloader_rates (); + + hw =kzalloc (sizeof (*hw),GFP_KERNEL ); + lookup =kzalloc (sizeof (*lookup),GFP_KERNEL ); +if (!hw || !lookup) + goto cleanup; + init.name ="virt_prcm_set" ; + init.ops = &virt_prcm_set_ops; + init.parent_names = &parent_name; + init.num_parents =1 ; + + hw->hw.init = &init; + + clk =clk_register (NULL , &hw->hw); + + lookup->dev_id =NULL ; + lookup->con_id ="cpufreq_ck" ; + lookup->clk = clk; + +clkdev_add (lookup); +return ; +cleanup: +kfree (hw); +kfree (lookup); +} +#endif
drivers/clk/ti/clk-2xxx.c +2 -0
@@ -229,6 +229,8 @@ static int __init omap2xxx_dt_clk_init(int soc_type)else ti_dt_clocks_register (omap2430_clks); +omap2xxx_clkt_vps_init (); +omap2_clk_disable_autoidle_all (); omap2_clk_enable_init_clocks(enable_init_clks,
include/linux/clk/ti.h +1 -0
@@ -279,6 +279,7 @@ unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,int omap2_reprogram_dpllcore (struct clk_hw *clk,unsigned long rate,unsigned long parent_rate);void omap2xxx_clkt_dpllcore_init (struct clk_hw *hw); +void omap2xxx_clkt_vps_init (void );void __iomem *ti_clk_get_reg_addr (struct device_node *node,int index);void ti_dt_clocks_register (struct ti_dt_clk *oclks);
Signature · 1 line
1.7.9.5
PATCH 11/12 ARM: OMAP2: PRM: add support for OMAP2 specific clock providers
In reply to Tero KristoThis patch adds support for initializing also omap2-prcm and omap2-scrm through DT.
Signed-off-by Tero Kristo <[email protected]>
--- arch/arm/mach-omap2/prm_common.c | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/mach-omap2/prm_common.c +2 -0
@@ -475,6 +475,8 @@ static struct of_device_id omap_prcm_dt_match_table[] = { { .compatible = "ti,am3-scrm" }, { .compatible = "ti,am4-prcm" }, { .compatible = "ti,am4-scrm" }, + { .compatible = "ti,omap2-prcm" }, + { .compatible = "ti,omap2-scrm" }, { .compatible = "ti,omap3-prm" }, { .compatible = "ti,omap3-cm" }, { .compatible = "ti,omap3-scrm" },
Signature · 1 line
1.7.9.5
PATCH 11/12 ARM: OMAP2: PRM: add support for OMAP2 specific clock providers
Quoted 14 lines · Tero Kristo
This patch adds support for initializing also omap2-prcm and omap2-scrm through DT.
Signed-off-by Tero Kristo <[email protected]>--- arch/arm/mach-omap2/prm_common.c | 2 ++ 1 file changed, 2 insertions(+)arch/arm/mach-omap2/prm_common.c +0
-0
arch/arm/mach-omap2/prm_common.c static struct of_device_id omap_prcm_dt_match_table[] = { · line 482
Quoted 8 lines
arch/arm/mach-omap2/prm_common.c +2
-0@@ -475,6 +475,8 @@ static struct of_device_id omap_prcm_dt_match_table[] = { { .compatible = "ti,am3-scrm" }, { .compatible = "ti,am4-prcm" }, { .compatible = "ti,am4-scrm" }, + { .compatible = "ti,omap2-prcm" }, + { .compatible = "ti,omap2-scrm" }, { .compatible = "ti,omap3-prm" }, { .compatible = "ti,omap3-cm" }, { .compatible = "ti,omap3-scrm" },
probably needs Bindings documentation as well.
Signature · 2 lines
Regards, Nishanth Menon
PATCH 12/12 ARM: OMAP2: clock: use DT clock boot if available
In reply to Tero KristoOtherwise legacy boot clock data is used.
Signed-off-by Tero Kristo <[email protected]>
--- arch/arm/mach-omap2/io.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-)
arch/arm/mach-omap2/io.c +13 -2
@@ -53,6 +53,7 @@#include "prm2xxx.h" #include "prm3xxx.h" #include "prm44xx.h" +#include "opp2xxx.h" /* * omap_clk_soc_init: points to a function that does the SoC-specific
@@ -410,7 +411,12 @@ void __init omap2420_init_early(void)omap242x_clockdomains_init ();omap2420_hwmod_init ();omap_hwmod_init_postsetup (); - omap_clk_soc_init = omap2420_clk_init; +if (of_have_populated_dt ()) { + omap_clk_soc_init = omap2420_dt_clk_init; + rate_table = omap2420_rate_table; + }else { + omap_clk_soc_init = omap2420_clk_init; + } }void __init omap2420_init_late (void )
@@ -439,7 +445,12 @@ void __init omap2430_init_early(void)omap243x_clockdomains_init ();omap2430_hwmod_init ();omap_hwmod_init_postsetup (); - omap_clk_soc_init = omap2430_clk_init; +if (of_have_populated_dt ()) { + omap_clk_soc_init = omap2430_dt_clk_init; + rate_table = omap2430_rate_table; + }else { + omap_clk_soc_init = omap2430_clk_init; + } }void __init omap2430_init_late (void )
Signature · 1 line
1.7.9.5
cover ARM: OMAP2 DT clock conversion
In reply to Tero KristoQuoted 10 lines · Tero Kristo
Hi,
This set concludes the omap2+ clock DT conversion work by creating the DT clock data for omap2 SoC also.
I am also currently doing related work to cleanup CM/PRM codebase in preparation to move it into
drivers/, this set is basically going to be a pre-requisite for that. I'll hopefully post something related to that early next week.
Quoted 8 lines
This set has been boot tested on OMAP2430 only (thanks Nishanth, I don't have access to OMAP2 hardware myself), so any testing feedback on 2420 board(s) would be appreciated.
Working tree:
Tree: https://github.com/t-kristo/linux-pm.git
Branch: 3.14-rc4-omap2-dt-clks
I do see checkpatch warnings in the series:
http://slexy.org/view/s20mzhlJ93
Series boot tested with:
3.14-rc4-omap2-dt-clks fc73a96 ARM: OMAP2: clock: use DT clock boot if available
from the tree mentioned above.
Things look good other than the checkpatch violation noticed in report, so other than that,
Tested-by Nishanth Menon <[email protected]>
omap2plus_defconfig
1: am335x-evm: Boot PASS: http://slexy.org/raw/s2jdV3XMCC 2: am335x-sk: Boot PASS: http://slexy.org/raw/s210nZI8Hx 3: am3517-evm: Boot PASS: http://slexy.org/raw/s21MG8kg6u 4: am37x-evm: Boot PASS: http://slexy.org/raw/s20coVhzLt
5: am43xx-epos: Boot PASS: http://slexy.org/raw/s21XKjjwyk
6: BeagleBoard-XM: Boot PASS: http://slexy.org/raw/s27PCmlDq7
7: BeagleBone-Black: Boot PASS: http://slexy.org/raw/s2HX1Q3iPb
8: crane: No Image built - Missing platform support?:
9: dra7: Boot PASS: http://slexy.org/raw/s21ofDfpD2
10: ldp: Boot FAIL: http://slexy.org/raw/s2SbrpyX2p
^^ legacy behavior
11: PandaBoard-ES: Boot PASS: http://slexy.org/raw/s21n4iMUKd
12: sdp2430: Boot PASS: http://slexy.org/raw/s2CJ5hYl72 13: sdp3430: Boot PASS: http://slexy.org/raw/s20axZ1nyb 14: sdp4430: Boot PASS: http://slexy.org/raw/s21wt3C5F3
15: OMAP5432uEVM: Boot PASS: http://slexy.org/raw/s208PhmCpm
TOTAL = 15 boards, Booted Boards = 13, No Boot boards = 2
Signature · 2 lines
Regards, Nishanth Menon
Tony Lindgren
maintainercover ARM: OMAP2 DT clock conversion
Quoted 46 lines · Nishanth Menon
Quoted 10 lines · Tero Kristo
Hi,
This set concludes the omap2+ clock DT conversion work by creating the DT clock data for omap2 SoC also.
I am also currently doing related work to cleanup CM/PRM codebase in preparation to move it into
drivers/, this set is basically going to be a pre-requisite for that. I'll hopefully post something related to that early next week.Quoted 8 lines
This set has been boot tested on OMAP2430 only (thanks Nishanth, I don't have access to OMAP2 hardware myself), so any testing feedback on 2420 board(s) would be appreciated.
Working tree:
Tree: https://github.com/t-kristo/linux-pm.git
Branch: 3.14-rc4-omap2-dt-clksI do see checkpatch warnings in the series:
http://slexy.org/view/s20mzhlJ93Series boot tested with:
3.14-rc4-omap2-dt-clks fc73a96 ARM: OMAP2: clock: use DT clock boot if available
from the tree mentioned above.Things look good other than the checkpatch violation noticed in report, so other than that,
Tested-by Nishanth Menon <[email protected]>
omap2plus_defconfig1: am335x-evm: Boot PASS: http://slexy.org/raw/s2jdV3XMCC 2: am335x-sk: Boot PASS: http://slexy.org/raw/s210nZI8Hx 3: am3517-evm: Boot PASS: http://slexy.org/raw/s21MG8kg6u 4: am37x-evm: Boot PASS: http://slexy.org/raw/s20coVhzLt5: am43xx-epos: Boot PASS: http://slexy.org/raw/s21XKjjwyk
6: BeagleBoard-XM: Boot PASS: http://slexy.org/raw/s27PCmlDq7
7: BeagleBone-Black: Boot PASS: http://slexy.org/raw/s2HX1Q3iPb
8: crane: No Image built - Missing platform support?:
9: dra7: Boot PASS: http://slexy.org/raw/s21ofDfpD2
10: ldp: Boot FAIL: http://slexy.org/raw/s2SbrpyX2p
^^ legacy behavior
11: PandaBoard-ES: Boot PASS: http://slexy.org/raw/s21n4iMUKd
Quoted 5 lines
12: sdp2430: Boot PASS: http://slexy.org/raw/s2CJ5hYl72 13: sdp3430: Boot PASS: http://slexy.org/raw/s20axZ1nyb 14: sdp4430: Boot PASS: http://slexy.org/raw/s21wt3C5F315: OMAP5432uEVM: Boot PASS: http://slexy.org/raw/s208PhmCpm
TOTAL = 15 boards, Booted Boards = 13, No Boot boards = 2
I'm getting this with omap2 only build:
drivers/clk/ti/dpll.c:235: undefined reference to clkhwops_omap3_dpll' drivers/built-in.o:(.rodata+0x1dd50): undefined reference to omap3_noncore_dpll_enable' drivers/built-in.o:(.rodata+0x1dd54): undefined reference to omap3_noncore_dpll_disable' drivers/built-in.o:(.rodata+0x1dd60): undefined reference to omap3_dpll_recalc' drivers/built-in.o:(.rodata+0x1dd74): undefined reference to omap3_noncore_dpll_set_rate' drivers/built-in.o:(.rodata+0x1ddb8): undefined reference to omap3_dpll_recalc' drivers/built-in.o:(.rodata+0x1ddfc): undefined reference to omap3_dpll_recalc' drivers/built-in.o:(.rodata+0x1de10): undefined reference to omap3_noncore_dpll_set_rate'
And this if 2430 is not selected:
drivers/clk/ti/interface.c:129: undefined reference to `clkhwops_omap2430_i2chs_wait'
Then I get this early on when trying to boot on n800:
[ 0.000000] Unable to handle kernel NULL pointer dereference at virtual address 00000000 [ 0.000000] pgd = c0004000 [ 0.000000] [00000000] *pgd=00000000 [ 0.000000] Internal error: Oops: 5 [#1] ARM [ 0.000000] Modules linked in: [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 3.14.0-rc1-00012-ga93a376 #225 [ 0.000000] task: c073ee80 ti: c0734000 task.ti: c0734000 [ 0.000000] PC is at strcmp+0xc/0x34 [ 0.000000] LR is at __clk_init+0x244/0x4d0 [ 0.000000] pc : [<c0273ed8>] lr : [<c0401858>] psr: 200001d3 [ 0.000000] sp : c0735e68 ip : c781cf80 fp : c05440b8 [ 0.000000] r10: 00000000 r9 : c781ba80 r8 : c781ba80 [ 0.000000] r7 : 0000000b r6 : c781ba80 r5 : 0000000b r4 : c0cf27f4 [ 0.000000] r3 : c781cfc0 r2 : 00000000 r1 : 00000000 r0 : 00000076 [ 0.000000] Flags: nzCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment kernel [ 0.000000] Control: 00c5387d Table: 80004000 DAC: 00000017 [ 0.000000] Process swapper (pid: 0, stack limit = 0xc0734240) [ 0.000000] Stack: (0xc0735e68 to 0xc0736000) [ 0.000000] 5e60: c7df5868 c781ba00 0000000b c781cfc0 c781ba80 c781ba00 [ 0.000000] 5e80: 00000000 c781ce80 c0544074 c0401bcc c781ba80 00000000 c781ba00 c7df5a68 [ 0.000000] 5ea0: c781cec0 c0401d08 c05442b8 c781ba00 0000000b c0403070 c0686038 00000000 [ 0.000000] 5ec0: c0686038 c7df5a68 c781ba08 c781cec0 c0735f0b 00000020 c0d09ce8 00000000 [ 0.000000] 5ee0: c781cf40 c781cf40 00000000 c781cf4c 4107b362 c7df59a8 00000000 c0719f30 [ 0.000000] 5f00: c781ce80 c05442b8 00000000 c0544074 c781cc80 c05440b8 00000000 c781cf44 [ 0.000000] 5f20: 4107b362 c7df59a8 c781cf40 00000002 00000002 c781cf48 c0735f48 c071a040 [ 0.000000] 5f40: c0735f48 c007533c c7df5874 00000000 a00001d3 a00001d3 c0797b6c 80004008 [ 0.000000] 5f60: c0797b6c c04e07c4 a00001d3 c07320d0 c7df59a8 c7df59a8 c7de8d10 c07a7454 [ 0.000000] 5f80: c07408dc 80004008 807244d0 c0403184 c7de8c70 00000000 c07a7454 c07408dc [ 0.000000] 5fa0: 80004008 c06f6884 c07a69bc 00000001 c073c041 c06f0918 ffffffff c06f317c [ 0.000000] 5fc0: 4107b362 c06ec8c0 00000000 c06e8a8c ffffffff ffffffff c06e8724 00000000 [ 0.000000] 5fe0: 00000000 c07256d0 00c5387d c073c094 c0725ad4 80008070 00000000 00000000 [ 0.000000] [<c0273ed8>] (strcmp) from [<c0401858>] (__clk_init+0x244/0x4d0) [ 0.000000] [<c0401858>] (__clk_init) from [<c0401bcc>] (_clk_register+0xe8/0x180) [ 0.000000] [<c0401bcc>] (_clk_register) from [<c0401d08>] (clk_register+0x38/0x78) [ 0.000000] [<c0401d08>] (clk_register) from [<c0403070>] (clk_register_composite+0x180/0x244) [ 0.000000] [<c0403070>] (clk_register_composite) from [<c0719f30>] (ti_clk_register_composite+0x1f8/0x268) [ 0.000000] [<c0719f30>] (ti_clk_register_composite) from [<c071a040>] (of_ti_composite_clk_setup+0xa0/0xbc) [ 0.000000] [<c071a040>] (of_ti_composite_clk_setup) from [<c0403184>] (ti_dt_clk_init_provider+0x50/0x10c) [ 0.000000] [<c0403184>] (ti_dt_clk_init_provider) from [<c06f6884>] (of_prcm_init+0x4c/0x84) [ 0.000000] [<c06f6884>] (of_prcm_init) from [<c06f0918>] (omap_clk_init+0x18/0x30) [ 0.000000] [<c06f0918>] (omap_clk_init) from [<c06f317c>] (omap2_sync32k_timer_init+0xc/0x64) [ 0.000000] [<c06f317c>] (omap2_sync32k_timer_init) from [<c06ec8c0>] (time_init+0x20/0x38) [ 0.000000] [<c06ec8c0>] (time_init) from [<c06e8a8c>] (start_kernel+0x134/0x2f4) [ 0.000000] [<c06e8a8c>] (start_kernel) from [<80008070>] (0x80008070) [ 0.000000] Code: e12fff1e e1a0c000 e3a02000 e7dc0002 (e7d13002) [ 0.000000] ---[ end trace 3406ff24bd97382e ]---
Regards,
Tony
cover ARM: OMAP2 DT clock conversion
Quoted 24 lines · Tony Lindgren
Quoted 23 lines · Nishanth Menon
Quoted 10 lines · Tero Kristo
Hi,
This set concludes the omap2+ clock DT conversion work by creating the DT clock data for omap2 SoC also.
I am also currently doing related work to cleanup CM/PRM codebase in preparation to move it into
drivers/, this set is basically going to be a pre-requisite for that. I'll hopefully post something related to that early next week.Quoted 8 lines
This set has been boot tested on OMAP2430 only (thanks Nishanth, I don't have access to OMAP2 hardware myself), so any testing feedback on 2420 board(s) would be appreciated.
Working tree:
Tree: https://github.com/t-kristo/linux-pm.git
Branch: 3.14-rc4-omap2-dt-clksI do see checkpatch warnings in the series:
http://slexy.org/view/s20mzhlJ93
Quoted 7 lines
Quoted 7 lines
Series boot tested with:
3.14-rc4-omap2-dt-clks fc73a96 ARM: OMAP2: clock: use DT clock boot if available
from the tree mentioned above.Things look good other than the checkpatch violation noticed in report, so other than that,
I noticed the checkpatch warnings also, most of them are impossible to fix, and/or are false warnings (see the fixed-factor / fixed-clock complaints for example.)
Quoted 33 lines
Quoted 16 lines
Tested-by Nishanth Menon <[email protected]>
omap2plus_defconfig1: am335x-evm: Boot PASS: http://slexy.org/raw/s2jdV3XMCC 2: am335x-sk: Boot PASS: http://slexy.org/raw/s210nZI8Hx 3: am3517-evm: Boot PASS: http://slexy.org/raw/s21MG8kg6u 4: am37x-evm: Boot PASS: http://slexy.org/raw/s20coVhzLt5: am43xx-epos: Boot PASS: http://slexy.org/raw/s21XKjjwyk
6: BeagleBoard-XM: Boot PASS: http://slexy.org/raw/s27PCmlDq7
7: BeagleBone-Black: Boot PASS: http://slexy.org/raw/s2HX1Q3iPb
8: crane: No Image built - Missing platform support?:
9: dra7: Boot PASS: http://slexy.org/raw/s21ofDfpD2
10: ldp: Boot FAIL: http://slexy.org/raw/s2SbrpyX2p
^^ legacy behavior
11: PandaBoard-ES: Boot PASS: http://slexy.org/raw/s21n4iMUKdQuoted 5 lines
12: sdp2430: Boot PASS: http://slexy.org/raw/s2CJ5hYl72 13: sdp3430: Boot PASS: http://slexy.org/raw/s20axZ1nyb 14: sdp4430: Boot PASS: http://slexy.org/raw/s21wt3C5F315: OMAP5432uEVM: Boot PASS: http://slexy.org/raw/s208PhmCpm
TOTAL = 15 boards, Booted Boards = 13, No Boot boards = 2I'm getting this with omap2 only build:
drivers/clk/ti/dpll.c:235: undefined reference toclkhwops_omap3_dpll' drivers/built-in.o:(.rodata+0x1dd50): undefined reference toomap3_noncore_dpll_enable' drivers/built-in.o:(.rodata+0x1dd54): undefined reference toomap3_noncore_dpll_disable' drivers/built-in.o:(.rodata+0x1dd60): undefined reference toomap3_dpll_recalc' drivers/built-in.o:(.rodata+0x1dd74): undefined reference toomap3_noncore_dpll_set_rate' drivers/built-in.o:(.rodata+0x1ddb8): undefined reference toomap3_dpll_recalc' drivers/built-in.o:(.rodata+0x1ddfc): undefined reference toomap3_dpll_recalc' drivers/built-in.o:(.rodata+0x1de10): undefined reference toomap3_noncore_dpll_set_rate'
Quoted 3 lines
And this if 2430 is not selected:
drivers/clk/ti/interface.c:129: undefined reference to `clkhwops_omap2430_i2chs_wait'
Hmm okay, these should be easy to fix... I'll need to see if I have introduced some other build breakages also...
Quoted 41 lines
Then I get this early on when trying to boot on n800:
[ 0.000000] Unable to handle kernel NULL pointer dereference at virtual address 00000000 [ 0.000000] pgd = c0004000 [ 0.000000] [00000000] *pgd=00000000 [ 0.000000] Internal error: Oops: 5 [#1] ARM [ 0.000000] Modules linked in: [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 3.14.0-rc1-00012-ga93a376 #225 [ 0.000000] task: c073ee80 ti: c0734000 task.ti: c0734000 [ 0.000000] PC is at strcmp+0xc/0x34 [ 0.000000] LR is at __clk_init+0x244/0x4d0 [ 0.000000] pc : [<c0273ed8>] lr : [<c0401858>] psr: 200001d3 [ 0.000000] sp : c0735e68 ip : c781cf80 fp : c05440b8 [ 0.000000] r10: 00000000 r9 : c781ba80 r8 : c781ba80 [ 0.000000] r7 : 0000000b r6 : c781ba80 r5 : 0000000b r4 : c0cf27f4 [ 0.000000] r3 : c781cfc0 r2 : 00000000 r1 : 00000000 r0 : 00000076 [ 0.000000] Flags: nzCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment kernel [ 0.000000] Control: 00c5387d Table: 80004000 DAC: 00000017 [ 0.000000] Process swapper (pid: 0, stack limit = 0xc0734240) [ 0.000000] Stack: (0xc0735e68 to 0xc0736000) [ 0.000000] 5e60: c7df5868 c781ba00 0000000b c781cfc0 c781ba80 c781ba00 [ 0.000000] 5e80: 00000000 c781ce80 c0544074 c0401bcc c781ba80 00000000 c781ba00 c7df5a68 [ 0.000000] 5ea0: c781cec0 c0401d08 c05442b8 c781ba00 0000000b c0403070 c0686038 00000000 [ 0.000000] 5ec0: c0686038 c7df5a68 c781ba08 c781cec0 c0735f0b 00000020 c0d09ce8 00000000 [ 0.000000] 5ee0: c781cf40 c781cf40 00000000 c781cf4c 4107b362 c7df59a8 00000000 c0719f30 [ 0.000000] 5f00: c781ce80 c05442b8 00000000 c0544074 c781cc80 c05440b8 00000000 c781cf44 [ 0.000000] 5f20: 4107b362 c7df59a8 c781cf40 00000002 00000002 c781cf48 c0735f48 c071a040 [ 0.000000] 5f40: c0735f48 c007533c c7df5874 00000000 a00001d3 a00001d3 c0797b6c 80004008 [ 0.000000] 5f60: c0797b6c c04e07c4 a00001d3 c07320d0 c7df59a8 c7df59a8 c7de8d10 c07a7454 [ 0.000000] 5f80: c07408dc 80004008 807244d0 c0403184 c7de8c70 00000000 c07a7454 c07408dc [ 0.000000] 5fa0: 80004008 c06f6884 c07a69bc 00000001 c073c041 c06f0918 ffffffff c06f317c [ 0.000000] 5fc0: 4107b362 c06ec8c0 00000000 c06e8a8c ffffffff ffffffff c06e8724 00000000 [ 0.000000] 5fe0: 00000000 c07256d0 00c5387d c073c094 c0725ad4 80008070 00000000 00000000 [ 0.000000] [<c0273ed8>] (strcmp) from [<c0401858>] (__clk_init+0x244/0x4d0) [ 0.000000] [<c0401858>] (__clk_init) from [<c0401bcc>] (_clk_register+0xe8/0x180) [ 0.000000] [<c0401bcc>] (_clk_register) from [<c0401d08>] (clk_register+0x38/0x78) [ 0.000000] [<c0401d08>] (clk_register) from [<c0403070>] (clk_register_composite+0x180/0x244) [ 0.000000] [<c0403070>] (clk_register_composite) from [<c0719f30>] (ti_clk_register_composite+0x1f8/0x268) [ 0.000000] [<c0719f30>] (ti_clk_register_composite) from [<c071a040>] (of_ti_composite_clk_setup+0xa0/0xbc) [ 0.000000] [<c071a040>] (of_ti_composite_clk_setup) from [<c0403184>] (ti_dt_clk_init_provider+0x50/0x10c)
Quoted 8 lines
[ 0.000000] [<c0403184>] (ti_dt_clk_init_provider) from [<c06f6884>] (of_prcm_init+0x4c/0x84) [ 0.000000] [<c06f6884>] (of_prcm_init) from [<c06f0918>] (omap_clk_init+0x18/0x30) [ 0.000000] [<c06f0918>] (omap_clk_init) from [<c06f317c>] (omap2_sync32k_timer_init+0xc/0x64) [ 0.000000] [<c06f317c>] (omap2_sync32k_timer_init) from [<c06ec8c0>] (time_init+0x20/0x38) [ 0.000000] [<c06ec8c0>] (time_init) from [<c06e8a8c>] (start_kernel+0x134/0x2f4) [ 0.000000] [<c06e8a8c>] (start_kernel) from [<80008070>] (0x80008070) [ 0.000000] Code: e12fff1e e1a0c000 e3a02000 e7dc0002 (e7d13002) [ 0.000000] ---[ end trace 3406ff24bd97382e ]---
Hmm, some clock node is broken, might be missing a name or parent name for some reason. Can you try to boot with DEBUG enabled so you get pr_debug:s out and see which clock is being initialized during the crash?
-Tero
Tony Lindgren
maintainercover ARM: OMAP2 DT clock conversion
Quoted 5 lines · Tero Kristo
Hmm, some clock node is broken, might be missing a name or parent name for some reason. Can you try to boot with DEBUG enabled so you get pr_debug:s out and see which clock is being initialized during the crash?
...
[ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: core_d18_ck [ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: vlynq_mux_fck [ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: vlynq_fck [ 0.000000] Unable to handle kernel NULL pointer dereference at virtual address 00000000
...
We really should be registering the clocks lazily as needed BTW. That leaves out the dependency to DEBUG_LL for seeing any kind of decent error messages during the booting.
Regards,
Tony
cover ARM: OMAP2 DT clock conversion
Quoted 14 lines · Tony Lindgren
Quoted 5 lines · Tero Kristo
Hmm, some clock node is broken, might be missing a name or parent name for some reason. Can you try to boot with DEBUG enabled so you get pr_debug:s out and see which clock is being initialized during the crash?
...
[ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: core_d18_ck [ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: vlynq_mux_fck [ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: vlynq_fck [ 0.000000] Unable to handle kernel NULL pointer dereference at virtual address 00000000...
Quoted 8 lines
We really should be registering the clocks lazily as needed BTW. That leaves out the dependency to
DEBUG_LLfor seeing any kind of decent error messages during the booting.Regards,
Tony
Hey Tony,
Can you retry with the branch? I just pushed one patch there, seems the parents for the vlynq_mux_fck were somewhat broken (there are holes in the valid mux values list, which hasn't happened with any other mux-clock so far.)
If this works, I will rework the series a bit and send v2 out. Alternatively I need to add extra debug info.
-Tero
Tony Lindgren
maintainercover ARM: OMAP2 DT clock conversion
Quoted 26 lines · Tero Kristo
Quoted 14 lines · Tony Lindgren
Quoted 5 lines · Tero Kristo
Hmm, some clock node is broken, might be missing a name or parent name for some reason. Can you try to boot with DEBUG enabled so you get pr_debug:s out and see which clock is being initialized during the crash?
...
[ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: core_d18_ck [ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: vlynq_mux_fck [ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: vlynq_fck [ 0.000000] Unable to handle kernel NULL pointer dereference at virtual address 00000000...
Quoted 8 lines
We really should be registering the clocks lazily as needed BTW. That leaves out the dependency to
DEBUG_LLfor seeing any kind of decent error messages during the booting.Regards,
Tony
Hey Tony,
Quoted 7 lines
Can you retry with the branch? I just pushed one patch there, seems the parents for the
vlynq_mux_fckwere somewhat broken (there are holes in the valid mux values list, which hasn't happened with any other mux-clock so far.)If this works, I will rework the series a bit and send v2 out. Alternatively I need to add extra debug info.
Still getting this without omap3:
drivers/built-in.o: In function `of_ti_dpll_setup':/home/tmlind/src/linux-2.6/drivers/clk/ti/dpll.c:235: undefined reference to clkhwops_omap3_dpll' drivers/built-in.o:(.rodata+0x1d7a0): undefined reference to omap3_noncore_dpll_enable' drivers/built-in.o:(.rodata+0x1d7a4): undefined reference to omap3_noncore_dpll_disable' drivers/built-in.o:(.rodata+0x1d7b0): undefined reference to omap3_dpll_recalc' drivers/built-in.o:(.rodata+0x1d7c4): undefined reference to omap3_noncore_dpll_set_rate' drivers/built-in.o:(.rodata+0x1d808): undefined reference to omap3_dpll_recalc' drivers/built-in.o:(.rodata+0x1d84c): undefined reference to omap3_dpll_recalc' drivers/built-in.o:(.rodata+0x1d860): undefined reference to omap3_noncore_dpll_set_rate'
and after enabling omap3 getting this without 2430:
drivers/built-in.o: In function `of_ti_omap2430_interface_clk_setup':/home/tmlind/src/linux-2.6/drivers/clk/ti/interface.c:129: undefined reference to `clkhwops_omap2430_i2chs_wait'
But after enabling those, it now boots on n8x0. The dmesg is below.
Care to post a patch to try dropping the legacy clock data as it should now work with the DT clocks only for omap2?
Regards,
Tony
[ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 3.14.0-rc5-00014-g2297f72-dirty (tmlind at muffinssi) (gcc version 4.3.5 (Debian 4.3.5-4) ) #388 Mon Mar 3 10:38:58 PST 2014 [ 0.000000] CPU: ARMv6-compatible processor [4107b362] revision 2 (ARMv6TEJ), cr=00c5387d [ 0.000000] CPU: VIPT aliasing data cache, VIPT aliasing instruction cache [ 0.000000] Machine model: Nokia N800 [ 0.000000] bootconsole [earlycon0] enabled [ 0.000000] debug: ignoring loglevel setting. [ 0.000000] Memory policy: Data cache writeback [ 0.000000] On node 0 totalpages: 32512 [ 0.000000] free_area_init_node: node 0, pgdat c07969a8, node_mem_map c7df9000 [ 0.000000] Normal zone: 256 pages used for memmap [ 0.000000] Normal zone: 0 pages reserved [ 0.000000] Normal zone: 32512 pages, LIFO batch:7 [ 0.000000] CPU: All CPU(s) started in SVC mode. [ 0.000000] OMAP2420 [ 0.000000] [ 0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 [ 0.000000] pcpu-alloc: [0] 0 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32256 [ 0.000000] Kernel command line: root=/dev/mmcblk0p2 rootwait console=ttyO2,115200 earlyprintk ignore_loglevel [ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes) [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) [ 0.000000] Memory: 115492K/130048K available (5098K kernel code, 457K rwdata, 1884K rodata, 304K init, 5485K bss, 14556K reserved, 0K highmem) [ 0.000000] Virtual kernel memory layout: [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB) [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) [ 0.000000] vmalloc : 0xc8800000 - 0xff000000 ( 872 MB) [ 0.000000] lowmem : 0xc0000000 - 0xc8000000 ( 128 MB) [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB) [ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB) [ 0.000000] .text : 0xc0008000 - 0xc06d9e10 (6984 kB) [ 0.000000] .init : 0xc06da000 - 0xc072601c ( 305 kB) [ 0.000000] .data : 0xc0728000 - 0xc079a690 ( 458 kB) [ 0.000000] .bss : 0xc079a690 - 0xc0cf5b10 (5486 kB) [ 0.000000] NR_IRQS:16 nr_irqs:16 16 [ 0.000000] IRQ: Found an INTC at 0xfa0fe000 (revision 2.0) with 96 interrupts [ 0.000000] Total of 96 interrupts on 1 active controller [ 0.000000] Clocking rate (Crystal/DPLL/MPU): 19.2/658/329 MHz [ 0.000000] OMAP clockevent source: timer1 at 32768 Hz [ 0.000030] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 65536000000000ns [ 0.008758] OMAP clocksource: 32k_counter at 32768 Hz [ 0.014465] hw-breakpoint: CPUID feature registers not supported. Assuming v6 debug is present. [ 0.026245] Console: colour dummy device 80x30 [ 0.031005] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar [ 0.039215] ... MAX_LOCKDEP_SUBCLASSES: 8 [ 0.043609] ... MAX_LOCK_DEPTH: 48 [ 0.048034] ... MAX_LOCKDEP_KEYS: 8191 [ 0.052673] ... CLASSHASH_SIZE: 4096 [ 0.057250] ... MAX_LOCKDEP_ENTRIES: 16384 [ 0.061981] ... MAX_LOCKDEP_CHAINS: 32768 [ 0.066680] ... CHAINHASH_SIZE: 16384 [ 0.071411] memory used by lock dependency info: 3695 kB [ 0.077056] per task-struct memory footprint: 1152 bytes [ 0.082916] Calibrating delay loop... 324.40 BogoMIPS (lpj=1622016) [ 0.143737] pid_max: default: 32768 minimum: 301 [ 0.149230] Security Framework initialized [ 0.153930] Mount-cache hash table entries: 512 [ 0.247467] CPU: Testing write buffer coherency: ok [ 0.256866] Setting up static identity map for 0x804db430 - 0x804db4a0 [ 0.286865] VFP support v0.3: implementor 41 architecture 1 part 20 variant b rev 2 [ 0.404479] pinctrl core: initialized pinctrl subsystem [ 0.424957] regulator-dummy: no parameters [ 0.437042] NET: Registered protocol family 16 [ 0.443664] DMA: preallocated 256 KiB pool for atomic coherent allocations [ 0.615081] omap_gpio 48018000.gpio: Could not get gpio dbck [ 0.626770] gpiochip_add: registered GPIOs 0 to 31 on device: gpio [ 0.636871] OMAP GPIO hardware version 1.8 [ 0.647003] omap_gpio 4801a000.gpio: Could not get gpio dbck [ 0.655456] gpiochip_add: registered GPIOs 32 to 63 on device: gpio [ 0.668640] omap_gpio 4801c000.gpio: Could not get gpio dbck [ 0.677062] gpiochip_add: registered GPIOs 64 to 95 on device: gpio [ 0.690704] omap_gpio 4801e000.gpio: Could not get gpio dbck [ 0.698974] gpiochip_add: registered GPIOs 96 to 127 on device: gpio [ 0.712554] omap-gpmc 6800a000.gpmc: GPMC revision 2.0 [ 0.730529] platform mmci-omap.0: alias fck already exists [ 0.743072] No ATAGs? [ 0.745300] hw-breakpoint: found 6 breakpoint and 1 watchpoint registers. [ 0.752807] hw-breakpoint: maximum watchpoint size is 4 bytes. [ 0.771942] OMAP DMA hardware revision 2.0 [ 1.001983] bio: create slab <bio-0> at 0 [ 1.308654] omap-dma-engine 48056000.dma-controller: OMAP DMA engine driver [ 1.336578] SCSI subsystem initialized [ 1.351013] usbcore: registered new interface driver usbfs [ 1.358825] usbcore: registered new interface driver hub [ 1.366912] usbcore: registered new device driver usb [ 1.391571] omap_i2c 48070000.i2c: bus 0 rev3.3 at 400 kHz [ 1.401855] omap_i2c 48072000.i2c: bus 1 rev3.3 at 400 kHz [ 1.433074] Switched to clocksource 32k_counter [ 1.892578] NET: Registered protocol family 2 [ 1.902313] TCP established hash table entries: 1024 (order: 0, 4096 bytes) [ 1.910247] TCP bind hash table entries: 1024 (order: 3, 36864 bytes) [ 1.918212] TCP: Hash tables configured (established 1024 bind 1024) [ 1.925659] TCP: reno registered [ 1.929168] UDP hash table entries: 256 (order: 2, 20480 bytes) [ 1.936157] UDP-Lite hash table entries: 256 (order: 2, 20480 bytes) [ 1.946411] NET: Registered protocol family 1 [ 1.955749] RPC: Registered named UNIX socket transport module. [ 1.962005] RPC: Registered udp transport module. [ 1.967132] RPC: Registered tcp transport module. [ 1.972106] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 1.983520] hw perfevents: enabled with v6 PMU driver, 3 counters available [ 2.018554] futex hash table entries: 256 (order: 1, 10240 bytes) [ 2.587036] VFS: Disk quotas dquot_6.5.2 [ 2.591400] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) [ 2.603668] NFS: Registering the id_resolver key type [ 2.610473] Key type id_resolver registered [ 2.615142] Key type id_legacy registered [ 2.619812] jffs2: version 2.2. (NAND) (SUMMARY) ? 2001-2006 Red Hat, Inc. [ 2.629089] msgmni has been set to 225 [ 2.645568] io scheduler noop registered [ 2.649749] io scheduler deadline registered [ 2.654632] io scheduler cfq registered (default) [ 2.671997] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled [ 2.702178] omap_uart 4806a000.serial: no wakeirq for uart0 [ 2.708282] of_get_named_gpiod_flags: can't parse gpios property of node '/ocp/serial at 4806a000[0]' [ 2.720428] 4806a000.serial: ttyO0 at MMIO 0x4806a000 (irq = 88, base_baud = 3000000) is a OMAP UART0 [ 2.736633] omap_uart 4806c000.serial: no wakeirq for uart0 [ 2.742553] of_get_named_gpiod_flags: can't parse gpios property of node '/ocp/serial at 4806c000[0]' [ 2.753723] 4806c000.serial: ttyO1 at MMIO 0x4806c000 (irq = 89, base_baud = 3000000) is a OMAP UART1 [ 2.768005] omap_uart 4806e000.serial: no wakeirq for uart0 [ 2.774078] of_get_named_gpiod_flags: can't parse gpios property of node '/ocp/serial at 4806e000[0]' [ 2.784912] 4806e000.serial: ttyO2 at MMIO 0x4806e000 (irq = 90, base_baud = 3000000) is a OMAP UART2 [ 2.795776] console [ttyO2] enabled [ 2.795776] console [ttyO2] enabled [ 2.803344] bootconsole [earlycon0] disabled [ 2.803344] bootconsole [earlycon0] disabled [ 2.825744] omap_rng 480a0000.rng: OMAP Random Number Generator ver. 40 [ 2.935699] brd: module loaded [ 2.997741] loop: module loaded [ 3.006866] Menelaus rev 2.2 [ 3.047821] mtdoops: mtd device (mtddev=name/number) must be supplied [ 3.059997] omap2-onenand omap2-onenand: initializing on CS0, phys base 0x04000000, virtual base c88c0000, freq 54 MHz [ 3.071533] OneNAND Manufacturer: Samsung (0xec) [ 3.076538] Muxed OneNAND(DDP) 256MB 1.8V 16-bit (0x48) [ 3.082092] OneNAND version = 0x0011 [ 3.085968] Chip support all block unlock [ 3.090332] onenand_wait: controller error = 0x0400 [ 3.097259] Scanning device for bad blocks [ 3.254333] 6 ofpart partitions found on MTD device omap2-onenand [ 3.260803] Creating 6 MTD partitions on "omap2-onenand": [ 3.266662] 0x000000000000-0x000000020000 : "bootloader" [ 3.292877] 0x000000020000-0x000000080000 : "config" [ 3.312042] 0x000000080000-0x000000280000 : "kernel" [ 3.331085] 0x000000280000-0x000000680000 : "initfs" [ 3.350555] 0x000000680000-0x000010000000 : "rootfs" [ 3.393737] 0x000000000000-0x000010000000 : "omap2-onenand" [ 3.474853] usbcore: registered new interface driver asix [ 3.482421] usbcore: registered new interface driver ax88179_178a [ 3.490844] usbcore: registered new interface driver cdc_ether [ 3.498992] usbcore: registered new interface driver r815x [ 3.506896] usbcore: registered new interface driver smsc95xx [ 3.514953] usbcore: registered new interface driver net1080 [ 3.522705] usbcore: registered new interface driver cdc_subset [ 3.530944] usbcore: registered new interface driver zaurus [ 3.539093] usbcore: registered new interface driver cdc_ncm [ 3.551727] usbcore: registered new interface driver cdc_wdm [ 3.559906] usbcore: registered new interface driver usb-storage [ 3.568420] usbcore: registered new interface driver usbtest [ 3.583953] mousedev: PS/2 mouse device common for all mice [ 3.606262] i2c /dev entries driver [ 3.620574] of_get_named_gpiod_flags exited with status 0 [ 3.626647] of_get_named_gpiod_flags exited with status 0 [ 3.632476] of_get_named_gpiod_flags exited with status 0 [ 3.656005] retu-mfd 2-0001: Retu & Vilma v1.5 found [ 3.677124] input: retu-pwrbutton as /devices/ocp.3/i2c.4/i2c-2/2-0001/retu-pwrbutton/input/input0 [ 3.695190] Driver for 1-wire Dallas network protocol. [ 3.724243] mmci-omap mmci-omap.0: no slots [ 3.728820] platform mmci-omap.0: Driver mmci-omap requests probe deferral [ 3.745727] usbcore: registered new interface driver usbhid [ 3.751678] usbhid: USB HID core driver [ 3.760375] oprofile: using arm/armv6 [ 3.766571] TCP: cubic registered [ 3.770111] Initializing XFRM netlink socket [ 3.775299] NET: Registered protocol family 17 [ 3.780242] NET: Registered protocol family 15 [ 3.786315] Key type dns_resolver registered [ 3.804290] omap_mux_get_by_name: Could not find signal sys_ndmareq0 [ 3.811065] omap_mux_get_by_name: Could not find signal sys_ndmareq1 [ 3.817932] omap_mux_get_by_name: Could not find signal sys_ndmareq2 [ 3.824768] omap_mux_get_by_name: Could not find signal sys_ndmareq3 [ 3.831512] omap_mux_get_by_name: Could not find signal sys_ndmareq4 [ 3.838317] omap_mux_get_by_name: Could not find signal sys_ndmareq5 [ 3.854064] usb_phy_gen_xceiv supply vcc not found, using dummy regulator [ 3.883972] tusb: prcm2.0 int2.0 gpio3.0 dma3.0 dieid2 rev3.1 [ 3.890167] musb-hdrc: ConfigData=0x06 (UTMI-8, dyn FIFOs, SoftConn) [ 3.897064] musb-hdrc: MHDRC RTL version 1.400 [ 3.901885] musb-hdrc: setup fifo_mode 4 [ 3.906188] musb-hdrc: 28/31 max ep, 16384/16384 memory [ 3.912506] musb-hdrc musb-hdrc.0.auto: MUSB HDRC host driver [ 3.928985] musb-hdrc musb-hdrc.0.auto: new USB bus registered, assigned bus number 1 [ 3.942871] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 [ 3.950256] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 [ 3.958068] usb usb1: Product: MUSB HDRC host driver [ 3.963439] usb usb1: Manufacturer: Linux 3.14.0-rc5-00014-g2297f72-dirty musb-hcd [ 3.971466] usb usb1: SerialNumber: musb-hdrc.0.auto [ 3.992279] hub 1-0:1.0: USB hub found [ 3.997680] hub 1-0:1.0: 1 port detected [ 4.022338] TUSB 6010 [ 4.157165] mmci-omap mmci-omap.0: command timeout (CMD52) [ 4.165161] mmci-omap mmci-omap.0: command timeout (CMD52) [ 4.196777] mmci-omap mmci-omap.0: command timeout (CMD5) [ 4.203491] mmci-omap mmci-omap.0: command timeout (CMD5) [ 4.210144] mmci-omap mmci-omap.0: command timeout (CMD5) [ 4.219604] mmci-omap mmci-omap.0: command timeout (CMD5) [ 4.241088] drivers/rtc/hctosys.c: unable to open rtc device (rtc0) [ 4.353851] Waiting for root device /dev/mmcblk0p2... [ 4.385711] mmc0: host does not support reading read-only switch. assuming write-enable. [ 4.395019] mmc0: new SDHC card at address ea4d [ 4.407897] mmcblk0: mmc0:ea4d SU04G 3.79 GiB [ 4.428863] mmcblk0: p1 p2 [ 4.447296] mmci-omap mmci-omap.0: command timeout (CMD52) [ 4.454101] mmci-omap mmci-omap.0: command timeout (CMD52) [ 4.464874] mmci-omap mmci-omap.0: command timeout (CMD8) [ 4.477966] mmci-omap mmci-omap.0: command timeout (CMD5) [ 4.488250] mmci-omap mmci-omap.0: command timeout (CMD5) [ 4.498260] mmci-omap mmci-omap.0: command timeout (CMD5) [ 4.506286] EXT3-fs (mmcblk0p2): recovery required on readonly filesystem [ 4.513671] EXT3-fs (mmcblk0p2): write access will be enabled during recovery [ 4.523468] mmci-omap mmci-omap.0: command timeout (CMD5) [ 4.540527] mmci-omap mmci-omap.0: command timeout (CMD8) [ 4.547363] kjournald starting. Commit interval 5 seconds [ 4.562103] EXT3-fs (mmcblk0p2): recovery complete [ 4.567413] EXT3-fs (mmcblk0p2): mounted filesystem with ordered data mode [ 4.577270] VFS: Mounted root (ext3 filesystem) readonly on device 179:2. [ 4.587280] Freeing unused kernel memory: 304K (c06da000 - c0726000) [ 4.662048] mmc1: host does not support reading read-only switch. assuming write-enable. [ 4.671020] mmc1: new SD card at address e624 [ 4.683898] mmcblk1: mmc1:e624 SD128 120 MiB [ 4.706298] mmcblk1: p1
INIT: version 2.86 booting
cover ARM: OMAP2 DT clock conversion
Quoted 47 lines · Tony Lindgren
Quoted 26 lines · Tero Kristo
Quoted 14 lines · Tony Lindgren
Quoted 5 lines · Tero Kristo
Hmm, some clock node is broken, might be missing a name or parent name for some reason. Can you try to boot with DEBUG enabled so you get pr_debug:s out and see which clock is being initialized during the crash?
...
[ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: core_d18_ck [ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: vlynq_mux_fck [ 0.000000] ti_dt_clk_init_provider: ti_dt_clk_init_provider: initializing: vlynq_fck [ 0.000000] Unable to handle kernel NULL pointer dereference at virtual address 00000000...
Quoted 8 lines
We really should be registering the clocks lazily as needed BTW. That leaves out the dependency to
DEBUG_LLfor seeing any kind of decent error messages during the booting.Regards,
Tony
Hey Tony,
Quoted 7 lines
Can you retry with the branch? I just pushed one patch there, seems the parents for the
vlynq_mux_fckwere somewhat broken (there are holes in the valid mux values list, which hasn't happened with any other mux-clock so far.)If this works, I will rework the series a bit and send v2 out. Alternatively I need to add extra debug info.
Still getting this without omap3:
drivers/built-in.o: In function `of_ti_dpll_setup':/home/tmlind/src/linux-2.6/drivers/clk/ti/dpll.c:235: undefined reference toclkhwops_omap3_dpll' drivers/built-in.o:(.rodata+0x1d7a0): undefined reference toomap3_noncore_dpll_enable' drivers/built-in.o:(.rodata+0x1d7a4): undefined reference toomap3_noncore_dpll_disable' drivers/built-in.o:(.rodata+0x1d7b0): undefined reference toomap3_dpll_recalc' drivers/built-in.o:(.rodata+0x1d7c4): undefined reference toomap3_noncore_dpll_set_rate' drivers/built-in.o:(.rodata+0x1d808): undefined reference toomap3_dpll_recalc' drivers/built-in.o:(.rodata+0x1d84c): undefined reference toomap3_dpll_recalc' drivers/built-in.o:(.rodata+0x1d860): undefined reference toomap3_noncore_dpll_set_rate'
Quoted 4 lines
and after enabling omap3 getting this without 2430:
drivers/built-in.o: In function `of_ti_omap2430_interface_clk_setup':/home/tmlind/src/linux-2.6/drivers/clk/ti/interface.c:129: undefined reference to `clkhwops_omap2430_i2chs_wait'
Yea, I didn't fix these with the patch I pushed, just the boot problem. I will fix these with the next version of the set, in addition to the issues reported by Nishanth.
Quoted 2 lines
But after enabling those, it now boots on n8x0. The dmesg is below.
This is good, so the culprit was only the vlynq fck.
Quoted 2 lines
Care to post a patch to try dropping the legacy clock data as it should now work with the DT clocks only for omap2?
Yes, I can post patches for this for omap2/omap3 also tomorrow.
-Tero
Quoted 238 lines
Regards,
Tony
[ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 3.14.0-rc5-00014-g2297f72-dirty (tmlind at muffinssi) (gcc version 4.3.5 (Debian 4.3.5-4) ) #388 Mon Mar 3 10:38:58 PST 2014 [ 0.000000] CPU: ARMv6-compatible processor [4107b362] revision 2 (ARMv6TEJ), cr=00c5387d [ 0.000000] CPU: VIPT aliasing data cache, VIPT aliasing instruction cache [ 0.000000] Machine model: Nokia N800 [ 0.000000] bootconsole [earlycon0] enabled [ 0.000000] debug: ignoring loglevel setting. [ 0.000000] Memory policy: Data cache writeback [ 0.000000] On node 0 totalpages: 32512 [ 0.000000] free_area_init_node: node 0, pgdat c07969a8, node_mem_map c7df9000 [ 0.000000] Normal zone: 256 pages used for memmap [ 0.000000] Normal zone: 0 pages reserved [ 0.000000] Normal zone: 32512 pages, LIFO batch:7 [ 0.000000] CPU: All CPU(s) started in SVC mode. [ 0.000000] OMAP2420 [ 0.000000] [ 0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 [ 0.000000] pcpu-alloc: [0] 0 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32256 [ 0.000000] Kernel command line: root=/dev/mmcblk0p2 rootwait console=ttyO2,115200 earlyprintk ignore_loglevel [ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes) [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) [ 0.000000] Memory: 115492K/130048K available (5098K kernel code, 457K rwdata, 1884K rodata, 304K init, 5485K bss, 14556K reserved, 0K highmem) [ 0.000000] Virtual kernel memory layout: [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB) [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) [ 0.000000] vmalloc : 0xc8800000 - 0xff000000 ( 872 MB) [ 0.000000] lowmem : 0xc0000000 - 0xc8000000 ( 128 MB) [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB) [ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB) [ 0.000000] .text : 0xc0008000 - 0xc06d9e10 (6984 kB) [ 0.000000] .init : 0xc06da000 - 0xc072601c ( 305 kB) [ 0.000000] .data : 0xc0728000 - 0xc079a690 ( 458 kB) [ 0.000000] .bss : 0xc079a690 - 0xc0cf5b10 (5486 kB) [ 0.000000] NR_IRQS:16 nr_irqs:16 16 [ 0.000000] IRQ: Found an INTC at 0xfa0fe000 (revision 2.0) with 96 interrupts [ 0.000000] Total of 96 interrupts on 1 active controller [ 0.000000] Clocking rate (Crystal/DPLL/MPU): 19.2/658/329 MHz [ 0.000000] OMAP clockevent source: timer1 at 32768 Hz [ 0.000030] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 65536000000000ns [ 0.008758] OMAP clocksource: 32k_counter at 32768 Hz [ 0.014465] hw-breakpoint: CPUID feature registers not supported. Assuming v6 debug is present. [ 0.026245] Console: colour dummy device 80x30 [ 0.031005] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar [ 0.039215] ... MAX_LOCKDEP_SUBCLASSES: 8 [ 0.043609] ... MAX_LOCK_DEPTH: 48 [ 0.048034] ... MAX_LOCKDEP_KEYS: 8191 [ 0.052673] ... CLASSHASH_SIZE: 4096 [ 0.057250] ... MAX_LOCKDEP_ENTRIES: 16384 [ 0.061981] ... MAX_LOCKDEP_CHAINS: 32768 [ 0.066680] ... CHAINHASH_SIZE: 16384 [ 0.071411] memory used by lock dependency info: 3695 kB [ 0.077056] per task-struct memory footprint: 1152 bytes [ 0.082916] Calibrating delay loop... 324.40 BogoMIPS (lpj=1622016) [ 0.143737] pid_max: default: 32768 minimum: 301 [ 0.149230] Security Framework initialized [ 0.153930] Mount-cache hash table entries: 512 [ 0.247467] CPU: Testing write buffer coherency: ok [ 0.256866] Setting up static identity map for 0x804db430 - 0x804db4a0 [ 0.286865] VFP support v0.3: implementor 41 architecture 1 part 20 variant b rev 2 [ 0.404479] pinctrl core: initialized pinctrl subsystem [ 0.424957] regulator-dummy: no parameters [ 0.437042] NET: Registered protocol family 16 [ 0.443664] DMA: preallocated 256 KiB pool for atomic coherent allocations [ 0.615081] omap_gpio 48018000.gpio: Could not get gpio dbck [ 0.626770] gpiochip_add: registered GPIOs 0 to 31 on device: gpio [ 0.636871] OMAP GPIO hardware version 1.8 [ 0.647003] omap_gpio 4801a000.gpio: Could not get gpio dbck [ 0.655456] gpiochip_add: registered GPIOs 32 to 63 on device: gpio [ 0.668640] omap_gpio 4801c000.gpio: Could not get gpio dbck [ 0.677062] gpiochip_add: registered GPIOs 64 to 95 on device: gpio [ 0.690704] omap_gpio 4801e000.gpio: Could not get gpio dbck [ 0.698974] gpiochip_add: registered GPIOs 96 to 127 on device: gpio [ 0.712554] omap-gpmc 6800a000.gpmc: GPMC revision 2.0 [ 0.730529] platform mmci-omap.0: alias fck already exists [ 0.743072] No ATAGs? [ 0.745300] hw-breakpoint: found 6 breakpoint and 1 watchpoint registers. [ 0.752807] hw-breakpoint: maximum watchpoint size is 4 bytes. [ 0.771942] OMAP DMA hardware revision 2.0 [ 1.001983] bio: create slab <bio-0> at 0 [ 1.308654] omap-dma-engine 48056000.dma-controller: OMAP DMA engine driver [ 1.336578] SCSI subsystem initialized [ 1.351013] usbcore: registered new interface driver usbfs [ 1.358825] usbcore: registered new interface driver hub [ 1.366912] usbcore: registered new device driver usb [ 1.391571] omap_i2c 48070000.i2c: bus 0 rev3.3 at 400 kHz [ 1.401855] omap_i2c 48072000.i2c: bus 1 rev3.3 at 400 kHz [ 1.433074] Switched to clocksource 32k_counter [ 1.892578] NET: Registered protocol family 2 [ 1.902313] TCP established hash table entries: 1024 (order: 0, 4096 bytes) [ 1.910247] TCP bind hash table entries: 1024 (order: 3, 36864 bytes) [ 1.918212] TCP: Hash tables configured (established 1024 bind 1024) [ 1.925659] TCP: reno registered [ 1.929168] UDP hash table entries: 256 (order: 2, 20480 bytes) [ 1.936157] UDP-Lite hash table entries: 256 (order: 2, 20480 bytes) [ 1.946411] NET: Registered protocol family 1 [ 1.955749] RPC: Registered named UNIX socket transport module. [ 1.962005] RPC: Registered udp transport module. [ 1.967132] RPC: Registered tcp transport module. [ 1.972106] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 1.983520] hw perfevents: enabled with v6 PMU driver, 3 counters available [ 2.018554] futex hash table entries: 256 (order: 1, 10240 bytes) [ 2.587036] VFS: Disk quotas dquot_6.5.2 [ 2.591400] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) [ 2.603668] NFS: Registering the id_resolver key type [ 2.610473] Key type id_resolver registered [ 2.615142] Key type id_legacy registered [ 2.619812] jffs2: version 2.2. (NAND) (SUMMARY) ? 2001-2006 Red Hat, Inc. [ 2.629089] msgmni has been set to 225 [ 2.645568] io scheduler noop registered [ 2.649749] io scheduler deadline registered [ 2.654632] io scheduler cfq registered (default) [ 2.671997] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled [ 2.702178] omap_uart 4806a000.serial: no wakeirq for uart0 [ 2.708282] of_get_named_gpiod_flags: can't parse gpios property of node '/ocp/serial at 4806a000[0]' [ 2.720428] 4806a000.serial: ttyO0 at MMIO 0x4806a000 (irq = 88, base_baud = 3000000) is a OMAP UART0 [ 2.736633] omap_uart 4806c000.serial: no wakeirq for uart0 [ 2.742553] of_get_named_gpiod_flags: can't parse gpios property of node '/ocp/serial at 4806c000[0]' [ 2.753723] 4806c000.serial: ttyO1 at MMIO 0x4806c000 (irq = 89, base_baud = 3000000) is a OMAP UART1 [ 2.768005] omap_uart 4806e000.serial: no wakeirq for uart0 [ 2.774078] of_get_named_gpiod_flags: can't parse gpios property of node '/ocp/serial at 4806e000[0]' [ 2.784912] 4806e000.serial: ttyO2 at MMIO 0x4806e000 (irq = 90, base_baud = 3000000) is a OMAP UART2 [ 2.795776] console [ttyO2] enabled [ 2.795776] console [ttyO2] enabled [ 2.803344] bootconsole [earlycon0] disabled [ 2.803344] bootconsole [earlycon0] disabled [ 2.825744] omap_rng 480a0000.rng: OMAP Random Number Generator ver. 40 [ 2.935699] brd: module loaded [ 2.997741] loop: module loaded [ 3.006866] Menelaus rev 2.2 [ 3.047821] mtdoops: mtd device (mtddev=name/number) must be supplied [ 3.059997] omap2-onenand omap2-onenand: initializing on CS0, phys base 0x04000000, virtual base c88c0000, freq 54 MHz [ 3.071533] OneNAND Manufacturer: Samsung (0xec) [ 3.076538] Muxed OneNAND(DDP) 256MB 1.8V 16-bit (0x48) [ 3.082092] OneNAND version = 0x0011 [ 3.085968] Chip support all block unlock [ 3.090332] onenand_wait: controller error = 0x0400 [ 3.097259] Scanning device for bad blocks [ 3.254333] 6 ofpart partitions found on MTD device omap2-onenand [ 3.260803] Creating 6 MTD partitions on "omap2-onenand": [ 3.266662] 0x000000000000-0x000000020000 : "bootloader" [ 3.292877] 0x000000020000-0x000000080000 : "config" [ 3.312042] 0x000000080000-0x000000280000 : "kernel" [ 3.331085] 0x000000280000-0x000000680000 : "initfs" [ 3.350555] 0x000000680000-0x000010000000 : "rootfs" [ 3.393737] 0x000000000000-0x000010000000 : "omap2-onenand" [ 3.474853] usbcore: registered new interface driver asix [ 3.482421] usbcore: registered new interface driver ax88179_178a [ 3.490844] usbcore: registered new interface driver cdc_ether [ 3.498992] usbcore: registered new interface driver r815x [ 3.506896] usbcore: registered new interface driver smsc95xx [ 3.514953] usbcore: registered new interface driver net1080 [ 3.522705] usbcore: registered new interface driver cdc_subset [ 3.530944] usbcore: registered new interface driver zaurus [ 3.539093] usbcore: registered new interface driver cdc_ncm [ 3.551727] usbcore: registered new interface driver cdc_wdm [ 3.559906] usbcore: registered new interface driver usb-storage [ 3.568420] usbcore: registered new interface driver usbtest [ 3.583953] mousedev: PS/2 mouse device common for all mice [ 3.606262] i2c /dev entries driver [ 3.620574] of_get_named_gpiod_flags exited with status 0 [ 3.626647] of_get_named_gpiod_flags exited with status 0 [ 3.632476] of_get_named_gpiod_flags exited with status 0 [ 3.656005] retu-mfd 2-0001: Retu & Vilma v1.5 found [ 3.677124] input: retu-pwrbutton as /devices/ocp.3/i2c.4/i2c-2/2-0001/retu-pwrbutton/input/input0 [ 3.695190] Driver for 1-wire Dallas network protocol. [ 3.724243] mmci-omap mmci-omap.0: no slots [ 3.728820] platform mmci-omap.0: Driver mmci-omap requests probe deferral [ 3.745727] usbcore: registered new interface driver usbhid [ 3.751678] usbhid: USB HID core driver [ 3.760375] oprofile: using arm/armv6 [ 3.766571] TCP: cubic registered [ 3.770111] Initializing XFRM netlink socket [ 3.775299] NET: Registered protocol family 17 [ 3.780242] NET: Registered protocol family 15 [ 3.786315] Key type dns_resolver registered [ 3.804290] omap_mux_get_by_name: Could not find signal sys_ndmareq0 [ 3.811065] omap_mux_get_by_name: Could not find signal sys_ndmareq1 [ 3.817932] omap_mux_get_by_name: Could not find signal sys_ndmareq2 [ 3.824768] omap_mux_get_by_name: Could not find signal sys_ndmareq3 [ 3.831512] omap_mux_get_by_name: Could not find signal sys_ndmareq4 [ 3.838317] omap_mux_get_by_name: Could not find signal sys_ndmareq5 [ 3.854064] usb_phy_gen_xceiv supply vcc not found, using dummy regulator [ 3.883972] tusb: prcm2.0 int2.0 gpio3.0 dma3.0 dieid2 rev3.1 [ 3.890167] musb-hdrc: ConfigData=0x06 (UTMI-8, dyn FIFOs, SoftConn) [ 3.897064] musb-hdrc: MHDRC RTL version 1.400 [ 3.901885] musb-hdrc: setup fifo_mode 4 [ 3.906188] musb-hdrc: 28/31 max ep, 16384/16384 memory [ 3.912506] musb-hdrc musb-hdrc.0.auto: MUSB HDRC host driver [ 3.928985] musb-hdrc musb-hdrc.0.auto: new USB bus registered, assigned bus number 1 [ 3.942871] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 [ 3.950256] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 [ 3.958068] usb usb1: Product: MUSB HDRC host driver [ 3.963439] usb usb1: Manufacturer: Linux 3.14.0-rc5-00014-g2297f72-dirty musb-hcd [ 3.971466] usb usb1: SerialNumber: musb-hdrc.0.auto [ 3.992279] hub 1-0:1.0: USB hub found [ 3.997680] hub 1-0:1.0: 1 port detected [ 4.022338] TUSB 6010 [ 4.157165] mmci-omap mmci-omap.0: command timeout (CMD52) [ 4.165161] mmci-omap mmci-omap.0: command timeout (CMD52) [ 4.196777] mmci-omap mmci-omap.0: command timeout (CMD5) [ 4.203491] mmci-omap mmci-omap.0: command timeout (CMD5) [ 4.210144] mmci-omap mmci-omap.0: command timeout (CMD5) [ 4.219604] mmci-omap mmci-omap.0: command timeout (CMD5) [ 4.241088] drivers/rtc/hctosys.c: unable to open rtc device (rtc0) [ 4.353851] Waiting for root device /dev/mmcblk0p2... [ 4.385711] mmc0: host does not support reading read-only switch. assuming write-enable. [ 4.395019] mmc0: new SDHC card at address ea4d [ 4.407897] mmcblk0: mmc0:ea4d SU04G 3.79 GiB [ 4.428863] mmcblk0: p1 p2 [ 4.447296] mmci-omap mmci-omap.0: command timeout (CMD52) [ 4.454101] mmci-omap mmci-omap.0: command timeout (CMD52) [ 4.464874] mmci-omap mmci-omap.0: command timeout (CMD8) [ 4.477966] mmci-omap mmci-omap.0: command timeout (CMD5) [ 4.488250] mmci-omap mmci-omap.0: command timeout (CMD5) [ 4.498260] mmci-omap mmci-omap.0: command timeout (CMD5) [ 4.506286] EXT3-fs (mmcblk0p2): recovery required on readonly filesystem [ 4.513671] EXT3-fs (mmcblk0p2): write access will be enabled during recovery [ 4.523468] mmci-omap mmci-omap.0: command timeout (CMD5) [ 4.540527] mmci-omap mmci-omap.0: command timeout (CMD8) [ 4.547363] kjournald starting. Commit interval 5 seconds [ 4.562103] EXT3-fs (mmcblk0p2): recovery complete [ 4.567413] EXT3-fs (mmcblk0p2): mounted filesystem with ordered data mode [ 4.577270] VFS: Mounted root (ext3 filesystem) readonly on device 179:2. [ 4.587280] Freeing unused kernel memory: 304K (c06da000 - c0726000) [ 4.662048] mmc1: host does not support reading read-only switch. assuming write-enable. [ 4.671020] mmc1: new SD card at address e624 [ 4.683898] mmcblk1: mmc1:e624 SD128 120 MiB [ 4.706298] mmcblk1: p1INIT: version 2.86 booting