arm64: Boot time configuration of Intermediate Physical Address size
v2 cover arm64: Boot time configuration of Intermediate Physical Address size
From: Radha Mohan Chintakuntla <[email protected]>
This patch adds support to read the implemented physical address size of a platform during boot-time and configure the translation control registers.
Changes since v1:
----------------
- Use BFI instruction instead of combination of UBFIZ and ORR.
Radha Mohan Chintakuntla (1):
arm64: Add boot time configuration of Intermediate Physical Address
size
arch/arm64/include/asm/kvm_arm.h | 15 ++++++--------- arch/arm64/include/asm/pgtable-hwdef.h | 5 ++--- arch/arm64/kvm/hyp-init.S | 6 ++++++ arch/arm64/mm/proc.S | 8 +++++++- 4 files changed, 21 insertions(+), 13 deletions(-)
RFC PATCH v2 1/1 arm64: Add boot time configuration of Intermediate Physical Address size
From: Radha Mohan Chintakuntla <[email protected]>
ARMv8 supports a range of physical address bit sizes. The PARange bits from ID_AA64MMFR0_EL1 register are read during boot-time and the intermediate physical address size bits are written in the translation control registers (TCR_EL1 and VTCR_EL2).
There is no change in the VA bits and levels of translation.
--- arch/arm64/include/asm/kvm_arm.h | 15 ++++++--------- arch/arm64/include/asm/pgtable-hwdef.h | 5 ++--- arch/arm64/kvm/hyp-init.S | 6 ++++++ arch/arm64/mm/proc.S | 8 +++++++- 4 files changed, 21 insertions(+), 13 deletions(-)
arch/arm64/include/asm/kvm_arm.h +6 -9
@@ -106,7 +106,6 @@/* VTCR_EL2 Registers bits */ #define VTCR_EL2_PS_MASK (7 << 16) -#define VTCR_EL2_PS_40B (2 << 16)#define VTCR_EL2_TG0_MASK (1 << 14)#define VTCR_EL2_TG0_4K (0 << 14)#define VTCR_EL2_TG0_64K (1 << 14)
@@ -129,10 +128,9 @@* 64kB pages (TG0 = 1) * 2 level page tables (SL = 1) */ -#define VTCR_EL2_FLAGS (VTCR_EL2_PS_40B | VTCR_EL2_TG0_64K | \ - VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ - VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \ - VTCR_EL2_T0SZ_40B) +#define VTCR_EL2_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SH0_INNER | \ + VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ + VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B)#define VTTBR_X (38 - VTCR_EL2_T0SZ_40B)#else /*
@@ -142,10 +140,9 @@* 4kB pages (TG0 = 0) * 3 level page tables (SL = 1) */ -#define VTCR_EL2_FLAGS (VTCR_EL2_PS_40B | VTCR_EL2_TG0_4K | \ - VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ - VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \ - VTCR_EL2_T0SZ_40B) +#define VTCR_EL2_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SH0_INNER | \ + VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ + VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B)#define VTTBR_X (37 - VTCR_EL2_T0SZ_40B)#endif
arch/arm64/include/asm/pgtable-hwdef.h +2 -3
@@ -100,9 +100,9 @@#define PTE_HYP PTE_USER/* -* 40-bit physical address supported. +* Highest possible physical address supported. */ -#define PHYS_MASK_SHIFT (40) +#define PHYS_MASK_SHIFT (48)#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)/*
@@ -122,7 +122,6 @@#define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28))#define TCR_TG0_64K (UL(1) << 14)#define TCR_TG1_64K (UL(1) << 30) -#define TCR_IPS_40BIT (UL(2) << 32)#define TCR_ASID16 (UL(1) << 36)#define TCR_TBI0 (UL(1) << 37)
arch/arm64/kvm/hyp-init.S +6 -0
@@ -68,6 +68,12 @@ __do_hyp_init: msr tcr_el2, x4 ldr x4, =VTCR_EL2_FLAGS + /* + * Read the PARange bits from ID_AA64MMFR0_EL1 and set the PS bits in + * VTCR_EL2. + */ + mrs x5, ID_AA64MMFR0_EL1 + bfi x4, x5, #16, #3 msr vtcr_el2, x4 mrs x4, mair_el1
arch/arm64/mm/proc.S +7 -1
@@ -209,8 +209,14 @@ ENTRY(__cpu_setup) * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for * both user and kernel. */ - ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \ + ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | \ TCR_ASID16 | TCR_TBI0 | (1 << 31) + /* + * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in + * TCR_EL1. + */ + mrs x9, ID_AA64MMFR0_EL1 + bfi x10, x9, #32, #3 #ifdef CONFIG_ARM64_64K_PAGES orr x10, x10, TCR_TG0_64K orr x10, x10, TCR_TG1_64K
Signature · 1 line
1.7.1
RFC PATCH v2 1/1 arm64: Add boot time configuration of Intermediate Physical Address size
Any more comments?
Quoted 121 lines · On Fri, Mar 7, 2014 at 2:19 PM, <[email protected]> wrote:
From: Radha Mohan Chintakuntla <[email protected]>
ARMv8 supports a range of physical address bit sizes. The PARange bits from
ID_AA64MMFR0_EL1register are read during boot-time and the intermediate physical address size bits are written in the translation control registers (TCR_EL1andVTCR_EL2).There is no change in the VA bits and levels of translation.
Signed-off-by Radha Mohan Chintakuntla <[email protected]>--- arch/arm64/include/asm/kvm_arm.h | 15 ++++++--------- arch/arm64/include/asm/pgtable-hwdef.h | 5 ++--- arch/arm64/kvm/hyp-init.S | 6 ++++++ arch/arm64/mm/proc.S | 8 +++++++- 4 files changed, 21 insertions(+), 13 deletions(-)arch/arm64/include/asm/kvm_arm.h +6
-9@@ -106,7 +106,6 @@/* VTCR_EL2 Registers bits */ #define VTCR_EL2_PS_MASK (7 << 16) -#define VTCR_EL2_PS_40B (2 << 16)#define VTCR_EL2_TG0_MASK (1 << 14)#define VTCR_EL2_TG0_4K (0 << 14)#define VTCR_EL2_TG0_64K (1 << 14)@@ -129,10 +128,9 @@* 64kB pages (TG0 = 1) * 2 level page tables (SL = 1) */ -#define VTCR_EL2_FLAGS (VTCR_EL2_PS_40B | VTCR_EL2_TG0_64K | \ - VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ - VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \ - VTCR_EL2_T0SZ_40B) +#define VTCR_EL2_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SH0_INNER | \ + VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ + VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B)#define VTTBR_X (38 - VTCR_EL2_T0SZ_40B)#else /* @@ -142,10 +140,9 @@* 4kB pages (TG0 = 0) * 3 level page tables (SL = 1) */ -#define VTCR_EL2_FLAGS (VTCR_EL2_PS_40B | VTCR_EL2_TG0_4K | \ - VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ - VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \ - VTCR_EL2_T0SZ_40B) +#define VTCR_EL2_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SH0_INNER | \ + VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ + VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B)#define VTTBR_X (37 - VTCR_EL2_T0SZ_40B)#endif arch/arm64/include/asm/pgtable-hwdef.h +2
-3@@ -100,9 +100,9 @@#define PTE_HYP PTE_USER/* -* 40-bit physical address supported. +* Highest possible physical address supported. */ -#define PHYS_MASK_SHIFT (40) +#define PHYS_MASK_SHIFT (48)#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)/* @@ -122,7 +122,6 @@#define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28))#define TCR_TG0_64K (UL(1) << 14)#define TCR_TG1_64K (UL(1) << 30) -#define TCR_IPS_40BIT (UL(2) << 32)#define TCR_ASID16 (UL(1) << 36)#define TCR_TBI0 (UL(1) << 37)arch/arm64/kvm/hyp-init.S +6
-0@@ -68,6 +68,12 @@ __do_hyp_init: msr tcr_el2, x4 ldr x4, =VTCR_EL2_FLAGS + /* + * Read the PARange bits from ID_AA64MMFR0_EL1 and set the PS bits in + * VTCR_EL2. + */ + mrs x5, ID_AA64MMFR0_EL1 + bfi x4, x5, #16, #3 msr vtcr_el2, x4 mrs x4, mair_el1arch/arm64/mm/proc.S +7
-2@@ -209,8 +209,14 @@ ENTRY(__cpu_setup) * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for * both user and kernel. */ - ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \ + ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | \ TCR_ASID16 | TCR_TBI0 | (1 << 31) + /* + * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in + * TCR_EL1. + */ + mrs x9, ID_AA64MMFR0_EL1 + bfi x10, x9, #32, #3 #ifdef CONFIG_ARM64_64K_PAGES orr x10, x10, TCR_TG0_64K orr x10, x10, TCR_TG1_64K --1.7.1
Catalin Marinas
maintainerRFC PATCH v2 1/1 arm64: Add boot time configuration of Intermediate Physical Address size
Quoted 1 line · Radha Mohan
Any more comments?
It looks fine to me but I'd like an ack from Marc as well on the KVM bits.
Patch below for reference. Thanks.
Quoted 121 lines · On Fri, Mar 7, 2014 at 2:19 PM, <[email protected]> wrote:
Quoted 120 lines
From: Radha Mohan Chintakuntla <[email protected]>
ARMv8 supports a range of physical address bit sizes. The PARange bits from
ID_AA64MMFR0_EL1register are read during boot-time and the intermediate physical address size bits are written in the translation control registers (TCR_EL1andVTCR_EL2).There is no change in the VA bits and levels of translation.
Signed-off-by Radha Mohan Chintakuntla <[email protected]>--- arch/arm64/include/asm/kvm_arm.h | 15 ++++++--------- arch/arm64/include/asm/pgtable-hwdef.h | 5 ++--- arch/arm64/kvm/hyp-init.S | 6 ++++++ arch/arm64/mm/proc.S | 8 +++++++- 4 files changed, 21 insertions(+), 13 deletions(-)arch/arm64/include/asm/kvm_arm.h +6
-9@@ -106,7 +106,6 @@/* VTCR_EL2 Registers bits */ #define VTCR_EL2_PS_MASK (7 << 16) -#define VTCR_EL2_PS_40B (2 << 16)#define VTCR_EL2_TG0_MASK (1 << 14)#define VTCR_EL2_TG0_4K (0 << 14)#define VTCR_EL2_TG0_64K (1 << 14)@@ -129,10 +128,9 @@* 64kB pages (TG0 = 1) * 2 level page tables (SL = 1) */ -#define VTCR_EL2_FLAGS (VTCR_EL2_PS_40B | VTCR_EL2_TG0_64K | \ - VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ - VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \ - VTCR_EL2_T0SZ_40B) +#define VTCR_EL2_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SH0_INNER | \ + VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ + VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B)#define VTTBR_X (38 - VTCR_EL2_T0SZ_40B)#else /* @@ -142,10 +140,9 @@* 4kB pages (TG0 = 0) * 3 level page tables (SL = 1) */ -#define VTCR_EL2_FLAGS (VTCR_EL2_PS_40B | VTCR_EL2_TG0_4K | \ - VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ - VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \ - VTCR_EL2_T0SZ_40B) +#define VTCR_EL2_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SH0_INNER | \ + VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ + VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B)#define VTTBR_X (37 - VTCR_EL2_T0SZ_40B)#endif arch/arm64/include/asm/pgtable-hwdef.h +2
-3@@ -100,9 +100,9 @@#define PTE_HYP PTE_USER/* -* 40-bit physical address supported. +* Highest possible physical address supported. */ -#define PHYS_MASK_SHIFT (40) +#define PHYS_MASK_SHIFT (48)#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)/* @@ -122,7 +122,6 @@#define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28))#define TCR_TG0_64K (UL(1) << 14)#define TCR_TG1_64K (UL(1) << 30) -#define TCR_IPS_40BIT (UL(2) << 32)#define TCR_ASID16 (UL(1) << 36)#define TCR_TBI0 (UL(1) << 37)arch/arm64/kvm/hyp-init.S +6
-0@@ -68,6 +68,12 @@ __do_hyp_init: msr tcr_el2, x4 ldr x4, =VTCR_EL2_FLAGS + /* + * Read the PARange bits from ID_AA64MMFR0_EL1 and set the PS bits in + * VTCR_EL2. + */ + mrs x5, ID_AA64MMFR0_EL1 + bfi x4, x5, #16, #3 msr vtcr_el2, x4 mrs x4, mair_el1arch/arm64/mm/proc.S +7
-2@@ -209,8 +209,14 @@ ENTRY(__cpu_setup) * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for * both user and kernel. */ - ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \ + ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | \ TCR_ASID16 | TCR_TBI0 | (1 << 31) + /* + * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in + * TCR_EL1. + */ + mrs x9, ID_AA64MMFR0_EL1 + bfi x10, x9, #32, #3 #ifdef CONFIG_ARM64_64K_PAGES orr x10, x10, TCR_TG0_64K orr x10, x10, TCR_TG1_64K --1.7.1
RFC PATCH v2 1/1 arm64: Add boot time configuration of Intermediate Physical Address size
Quoted 5 lines · Catalin Marinas
Quoted 1 line · Radha Mohan
Any more comments?
It looks fine to me but I'd like an ack from Marc as well on the KVM bits.
Thanks for putting me in the loop Catalin.
Quoted 115 lines
Patch below for reference. Thanks.
Quoted 113 lines · On Fri, Mar 7, 2014 at 2:19 PM, <[email protected]> wrote:
Quoted 112 lines
From: Radha Mohan Chintakuntla <[email protected]>
ARMv8 supports a range of physical address bit sizes. The PARange bits from
ID_AA64MMFR0_EL1register are read during boot-time and the intermediate physical address size bits are written in the translation control registers (TCR_EL1andVTCR_EL2).There is no change in the VA bits and levels of translation.
Signed-off-by Radha Mohan Chintakuntla <[email protected]>--- arch/arm64/include/asm/kvm_arm.h | 15 ++++++--------- arch/arm64/include/asm/pgtable-hwdef.h | 5 ++--- arch/arm64/kvm/hyp-init.S | 6 ++++++ arch/arm64/mm/proc.S | 8 +++++++- 4 files changed, 21 insertions(+), 13 deletions(-)arch/arm64/include/asm/kvm_arm.h +6
-9@@ -106,7 +106,6 @@/* VTCR_EL2 Registers bits */ #define VTCR_EL2_PS_MASK (7 << 16) -#define VTCR_EL2_PS_40B (2 << 16)#define VTCR_EL2_TG0_MASK (1 << 14)#define VTCR_EL2_TG0_4K (0 << 14)#define VTCR_EL2_TG0_64K (1 << 14)@@ -129,10 +128,9 @@* 64kB pages (TG0 = 1) * 2 level page tables (SL = 1) */ -#define VTCR_EL2_FLAGS (VTCR_EL2_PS_40B | VTCR_EL2_TG0_64K | \ - VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ - VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \ - VTCR_EL2_T0SZ_40B) +#define VTCR_EL2_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SH0_INNER | \ + VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ + VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B)#define VTTBR_X (38 - VTCR_EL2_T0SZ_40B)#else /* @@ -142,10 +140,9 @@* 4kB pages (TG0 = 0) * 3 level page tables (SL = 1) */ -#define VTCR_EL2_FLAGS (VTCR_EL2_PS_40B | VTCR_EL2_TG0_4K | \ - VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ - VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \ - VTCR_EL2_T0SZ_40B) +#define VTCR_EL2_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SH0_INNER | \ + VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ + VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B)#define VTTBR_X (37 - VTCR_EL2_T0SZ_40B)#endif arch/arm64/include/asm/pgtable-hwdef.h +2
-3@@ -100,9 +100,9 @@#define PTE_HYP PTE_USER/* -* 40-bit physical address supported. +* Highest possible physical address supported. */ -#define PHYS_MASK_SHIFT (40) +#define PHYS_MASK_SHIFT (48)#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)/* @@ -122,7 +122,6 @@#define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28))#define TCR_TG0_64K (UL(1) << 14)#define TCR_TG1_64K (UL(1) << 30) -#define TCR_IPS_40BIT (UL(2) << 32)#define TCR_ASID16 (UL(1) << 36)#define TCR_TBI0 (UL(1) << 37)arch/arm64/kvm/hyp-init.S +6
-0@@ -68,6 +68,12 @@ __do_hyp_init: msr tcr_el2, x4 ldr x4, =VTCR_EL2_FLAGS + /* + * Read the PARange bits from ID_AA64MMFR0_EL1 and set the PS bits in + * VTCR_EL2. + */ + mrs x5, ID_AA64MMFR0_EL1 + bfi x4, x5, #16, #3 msr vtcr_el2, x4 mrs x4, mair_el1arch/arm64/mm/proc.S +4
-1@@ -209,8 +209,14 @@ ENTRY(__cpu_setup) * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for * both user and kernel. */ - ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \ + ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | \ TCR_ASID16 | TCR_TBI0 | (1 << 31) + /* + * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in + * TCR_EL1.
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
arch/arm64/mm/proc.S +3
-1+ */ + mrs x9, ID_AA64MMFR0_EL1 + bfi x10, x9, #32, #3 #ifdef CONFIG_ARM64_64K_PAGES orr x10, x10, TCR_TG0_64K orr x10, x10, TCR_TG1_64K --1.7.1
Looks good to me.
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
Catalin Marinas
maintainerRFC PATCH v2 1/1 arm64: Add boot time configuration of Intermediate Physical Address size
Quoted 10 lines · Marc Zyngier
Quoted 5 lines · Catalin Marinas
Quoted 1 line · Radha Mohan
Any more comments?
It looks fine to me but I'd like an ack from Marc as well on the KVM bits.
Looks good to me.
Acked-by Marc Zyngier <[email protected]>
Thanks. Patch applied.
Signature · 1 line
Catalin
RFC PATCH v2 1/1 arm64: Add boot time configuration of Intermediate Physical Address size
In reply to mohun106 at gmail.comQuoted 8 lines · On Fri, Mar 07, 2014 at 08:49:25AM +0000, mohun106 at gmail.com wrote:
From: Radha Mohan Chintakuntla <[email protected]>
ARMv8 supports a range of physical address bit sizes. The PARange bits from
ID_AA64MMFR0_EL1register are read during boot-time and the intermediate physical address size bits are written in the translation control registers (TCR_EL1andVTCR_EL2).There is no change in the VA bits and levels of translation.
Will