ARM: sun7i/sun6i: irqchip: Irqchip driver for NMI controller

PATCH Superseded Carlo Caione 3 participants 10 messages Mar 15, 2014 – Mar 19, 2014

Subsystems (3)

Device tree bindings Arm/Allwinner sunXi SoC support irqchip drivers

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Carlo Caione

author

2014-03-15 13:40 UTC #0 lore raw

v6 cover ARM: sun7i/sun6i: irqchip: Irqchip driver for NMI controller

Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI. Three register are present to (un)mask, control and acknowledge NMI. These two patches add a new irqchip driver in cascade with GIC.

Changes since v1:
- added binding document

Changes since v2:
- fixed trigger type in DTS
- new explanations in binding documentation
- added support for A31 (sun6i)

Changes since v3:
- changed compatibles

Changes since v4:
- fixed binding documentation

Changes since v5:
- switched to handle_fasteoi_irq handler to avoid the double interrupts issue

Carlo Caione (3):
ARM: sun7i/sun6i: irqchip: Add irqchip driver for NMI controller
ARM: sun7i/sun6i: dts: Add NMI irqchip support
ARM: sun7i/sun6i: irqchip: Update the documentation

 .../allwinner,sun67i-sc-nmi.txt                    |  27 +++
 arch/arm/boot/dts/sun6i-a31.dtsi                   |   9 +
 arch/arm/boot/dts/sun7i-a20.dtsi                   |   9 +
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-sunxi-nmi.c                    | 208 +++++++++++++++++++++
 5 files changed, 254 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt
 create mode 100644 drivers/irqchip/irq-sunxi-nmi.c

Signature · 1 line

1.8.3.2

Carlo Caione

author

2014-03-15 13:40 UTC #1 lore raw

PATCH v6 1/3 ARM: sun7i/sun6i: irqchip: Add irqchip driver for NMI controller

Allwinner A20/A31 SoCs have special registers to control / (un)mask / acknowledge NMI. This NMI controller is separated and independent from GIC. This patch adds a new irqchip to manage NMI.

Signed-off-by Carlo Caione <[email protected]>

Acked-by Maxime Ripard <[email protected]>

---
 drivers/irqchip/Makefile        |   1 +
 drivers/irqchip/irq-sunxi-nmi.c | 208 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 209 insertions(+)
 create mode 100644 drivers/irqchip/irq-sunxi-nmi.c

drivers/irqchip/Makefile +1 -0

index 5194afb..1c0c151 100644
@@ -12,6 +12,7 @@ obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)	+= irq-metag.o
 obj-$(CONFIG_ARCH_MOXART)		+= irq-moxart.o
 obj-$(CONFIG_ORION_IRQCHIP)		+= irq-orion.o
 obj-$(CONFIG_ARCH_SUNXI)		+= irq-sun4i.o
+obj-$(CONFIG_ARCH_SUNXI)		+= irq-sunxi-nmi.o
 obj-$(CONFIG_ARCH_SPEAR3XX)		+= spear-shirq.o
 obj-$(CONFIG_ARM_GIC)			+= irq-gic.o
 obj-$(CONFIG_ARM_NVIC)			+= irq-nvic.o

drivers/irqchip/irq-sunxi-nmi.c new file +208 -0

208 lines not on this page · raw message

Signature · 1 line

1.8.3.2

Carlo Caione

author

2014-03-15 13:41 UTC #2 lore raw

PATCH v6 2/3 ARM: sun7i/sun6i: dts: Add NMI irqchip support

In reply to Carlo Caione

This patch adds DTS entries for NMI controller as child of GIC.

Signed-off-by Carlo Caione <[email protected]>

---
 arch/arm/boot/dts/sun6i-a31.dtsi | 9 +++++++++
 arch/arm/boot/dts/sun7i-a20.dtsi | 9 +++++++++
 2 files changed, 18 insertions(+)

arch/arm/boot/dts/sun6i-a31.dtsi +9 -0

index 5256ad9..4a5050c 100644
@@ -190,6 +190,15 @@
 		#size-cells = <1>;
 		ranges;
 
+		nmi_intc: sc-nmi-intc at 01f00c0c {
+			compatible = "allwinner,sun6i-a31-sc-nmi";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x01f00c0c 0x38>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 0 4>;
+		};
+
 		pio: pinctrl at 01c20800 {
 			compatible = "allwinner,sun6i-a31-pinctrl";
 			reg = <0x01c20800 0x400>;

arch/arm/boot/dts/sun7i-a20.dtsi +9 -0

index 6f25cf5..55464a0 100644
@@ -339,6 +339,15 @@
 		#size-cells = <1>;
 		ranges;
 
+		nmi_intc: sc-nmi-intc at 01c00030 {
+			compatible = "allwinner,sun7i-a20-sc-nmi";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x01c00030 0x0c>;
+			interrupt-parent = <&gic>;
+			interrupts = <0 0 4>;
+		};
+
 		emac: ethernet at 01c0b000 {
 			compatible = "allwinner,sun4i-a10-emac";
 			reg = <0x01c0b000 0x1000>;

Signature · 1 line

1.8.3.2

Maxime Ripard

2014-03-17 13:30 UTC #3 lore raw

PATCH v6 2/3 ARM: sun7i/sun6i: dts: Add NMI irqchip support

Quoted 13 lines · Carlo Caione

This patch adds DTS entries for NMI controller as child of GIC.
Signed-off-by Carlo Caione <[email protected]>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 9 +++++++++
 arch/arm/boot/dts/sun7i-a20.dtsi | 9 +++++++++
 2 files changed, 18 insertions(+)
arch/arm/boot/dts/sun6i-a31.dtsi +0 -0
index 5256ad9..4a5050c 100644

arch/arm/boot/dts/sun6i-a31.dtsi line 193

Quoted 4 lines

arch/arm/boot/dts/sun6i-a31.dtsi +1 -0

@@ -190,6 +190,15 @@
 		#size-cells = <1>;
 		ranges;
 
+		nmi_intc: sc-nmi-intc at 01f00c0c {

It should be interrupt-controller at 01f00c0c, according to the ePAPR.

arch/arm/boot/dts/sun6i-a31.dtsi line 194

Quoted 1 line

arch/arm/boot/dts/sun6i-a31.dtsi +1 -0
+			compatible = "allwinner,sun6i-a31-sc-nmi";

I'm curious, what is the "sc" for?

arch/arm/boot/dts/sun6i-a31.dtsi line 198

Quoted 4 lines

arch/arm/boot/dts/sun6i-a31.dtsi +4 -0

+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x01f00c0c 0x38>;
+			interrupt-parent = <&gic>;

This is actually the default.

arch/arm/boot/dts/sun6i-a31.dtsi line 201

Quoted 3 lines

arch/arm/boot/dts/sun6i-a31.dtsi +3 -0
+			interrupts = <0 0 4>;
+		};
+

Thanks!
Maxime

Signature · 10 lines

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Carlo Caione

author

2014-03-17 14:13 UTC #4 lore raw

[linux-sunxi] Re: [PATCH v6 2/3] ARM: sun7i/sun6i: dts: Add NMI irqchip support

Quoted 17 lines · Maxime Ripard

Quoted 16 lines · Carlo Caione
This patch adds DTS entries for NMI controller as child of GIC.
Signed-off-by Carlo Caione <[email protected]>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 9 +++++++++
 arch/arm/boot/dts/sun7i-a20.dtsi | 9 +++++++++
 2 files changed, 18 insertions(+)
arch/arm/boot/dts/sun6i-a31.dtsi +0 -0
index 5256ad9..4a5050c 100644
@@ -190,6 +190,15 @@
              #size-cells = <1>;
              ranges;
 

Quoted 3 lines

arch/arm/boot/dts/sun6i-a31.dtsi line 193
Quoted 1 line
arch/arm/boot/dts/sun6i-a31.dtsi +1 -0
+             nmi_intc: sc-nmi-intc at 01f00c0c {
It should be interrupt-controller at 01f00c0c, according to the ePAPR.

Quoted 3 lines

arch/arm/boot/dts/sun6i-a31.dtsi line 194
Quoted 1 line
arch/arm/boot/dts/sun6i-a31.dtsi +1 -0
+                     compatible = "allwinner,sun6i-a31-sc-nmi";
I'm curious, what is the "sc" for?

It stands for System Control (in the datasheet the NMI controller is included in a block named System Controller)

Quoted 6 lines

arch/arm/boot/dts/sun6i-a31.dtsi line 198
Quoted 4 lines
arch/arm/boot/dts/sun6i-a31.dtsi +4 -0
+                     interrupt-controller;
+                     #interrupt-cells = <2>;
+                     reg = <0x01f00c0c 0x38>;
+                     interrupt-parent = <&gic>;
This is actually the default.

I'll delete it.

Quoted 6 lines

arch/arm/boot/dts/sun6i-a31.dtsi line 201
Quoted 3 lines
arch/arm/boot/dts/sun6i-a31.dtsi +3 -0
+                     interrupts = <0 0 4>;
+             };
+
Thanks!
Maxime

Thank you,

Signature · 1 line

Carlo Caione

Carlo Caione

author

2014-03-15 13:41 UTC #5 lore raw

PATCH v6 3/3 ARM: sun7i/sun6i: irqchip: Update the documentation

In reply to Carlo Caione

Added documentation for NMI irqchip.

Signed-off-by Carlo Caione <[email protected]>

---
 .../allwinner,sun67i-sc-nmi.txt                    | 27 ++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt

Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt new file +27 -0

new file mode 100644
index 0000000..d1c5cda
@@ -0,0 +1,27 @@
+Allwinner Sunxi NMI Controller
+==============================
+
+Required properties:
+
+- compatible : should be "allwinner,sun7i-a20-sc-nmi" or
+  "allwinner,sun6i-a31-sc-nmi"
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 2. The first cell is the IRQ number, the
+  second cell the trigger type as defined in interrupt.txt in this directory.
+- interrupt-parent: Specifies the parent interrupt controller.
+- interrupts: Specifies the interrupt line (NMI) which is handled by
+  the interrupt controller in the parent controller's notation. This value
+  shall be the NMI.
+
+Example:
+
+sc-nmi-intc at 01c00030 {
+	compatible = "allwinner,sun7i-a20-sc-nmi";
+	interrupt-controller;
+	#interrupt-cells = <2>;
+	reg = <0x01c00030 0x0c>;
+	interrupt-parent = <&gic>;
+	interrupts = <0 0 4>;
+};

Signature · 1 line

1.8.3.2

Thomas Gleixner

2014-03-19 11:13 UTC #6 lore raw

v6 cover ARM: sun7i/sun6i: irqchip: Irqchip driver for NMI controller

In reply to Carlo Caione

Quoted 3 lines · Carlo Caione

Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI. Three register are present to (un)mask, control and acknowledge NMI. These two patches add a new irqchip driver in cascade with GIC.

If I get an ack for the DT parts, I'll pick it up.

Maxime Ripard

2014-03-19 12:32 UTC #7 lore raw

v6 cover ARM: sun7i/sun6i: irqchip: Irqchip driver for NMI controller

Quoted 7 lines · Thomas Gleixner

Quoted 3 lines · Carlo Caione
Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI. Three register are present to (un)mask, control and acknowledge NMI. These two patches add a new irqchip driver in cascade with GIC.
If I get an ack for the DT parts, I'll pick it up.

I had some comments on it, so Carlo will probably resubmit it.

Signature · 10 lines

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Thomas Gleixner

2014-03-19 12:41 UTC #8 lore raw

v6 cover ARM: sun7i/sun6i: irqchip: Irqchip driver for NMI controller

Quoted 10 lines · Maxime Ripard

Quoted 7 lines · Thomas Gleixner
Quoted 3 lines · Carlo Caione
Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI. Three register are present to (un)mask, control and acknowledge NMI. These two patches add a new irqchip driver in cascade with GIC.
If I get an ack for the DT parts, I'll pick it up.
I had some comments on it, so Carlo will probably resubmit it.

That's the resubmit as far as I can tell.

Carlo Caione

author

2014-03-19 12:49 UTC #9 lore raw

v6 cover ARM: sun7i/sun6i: irqchip: Irqchip driver for NMI controller

Quoted 9 lines · Thomas Gleixner

Quoted 7 lines · Maxime Ripard
Quoted 6 lines · Thomas Gleixner
Quoted 3 lines · Carlo Caione
Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI. Three register are present to (un)mask, control and acknowledge NMI. These two patches add a new irqchip driver in cascade with GIC.

Quoted 5 lines

Quoted 3 lines
Quoted 1 line
If I get an ack for the DT parts, I'll pick it up.
I had some comments on it, so Carlo will probably resubmit it.
That's the resubmit as far as I can tell.

I'll submit a v7 addressing the Maxime's comments on DT part.

Regards,

Signature · 1 line

Carlo Caione