ARM: cache-tauros2: remove ARMv6 code

PATCH New Arnd Bergmann 2 participants 4 messages Mar 11, 2014 – Mar 27, 2014 Arm (32-bit)

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Arnd Bergmann

author

2014-03-11 18:51 UTC #0 lore raw

PATCH 1/1 ARM: cache-tauros2: remove ARMv6 code

When building a kernel with support for both ARMv6 and ARMv7 but no MMU, the call from tauros2_internal_init to adjust_cr causes a link error. While that could probably be resolved, we don't actually support cache-tauros2 on ARMv6 any more. All PJ4 CPU implementations support both ARMv6 and ARMv7 and we already assume that we are using them only in ARMv7 mode.

Removing the ARMv6 code path reduces the code size and avoids the linker error.

Signed-off-by Arnd Bergmann <[email protected]>

---

arch/arm/mm/cache-tauros2.c +0 ~~-27~~

index 1be0f4e..7964ef2 100644
@@ -229,33 +229,6 @@ static void __init tauros2_internal_init(unsigned int features)
 	}
 #endif
 
-#ifdef CONFIG_CPU_32v6
-	/*
-	 * Check whether this CPU lacks support for the v7 hierarchical
-	 * cache ops.  (PJ4 is in its v6 personality mode if the MMFR3
-	 * register indicates no support for the v7 hierarchical cache
-	 * ops.)
-	 */
-	if (cpuid_scheme() && (read_mmfr3() & 0xf) == 0) {
-		/*
-		 * When Tauros2 is used in an ARMv6 system, the L2
-		 * enable bit is in the ARMv6 ARM-mandated position
-		 * (bit [26] of the System Control Register).
-		 */
-		if (!(get_cr() & 0x04000000)) {
-			printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
-			adjust_cr(0x04000000, 0x04000000);
-		}
-
-		mode = "ARMv6";
-		outer_cache.inv_range = tauros2_inv_range;
-		outer_cache.clean_range = tauros2_clean_range;
-		outer_cache.flush_range = tauros2_flush_range;
-		outer_cache.disable = tauros2_disable;
-		outer_cache.resume = tauros2_resume;
-	}
-#endif
-
 #ifdef CONFIG_CPU_32v7
 	/*
 	 * Check whether this CPU has support for the v7 hierarchical

Haojian Zhuang

2014-03-18 08:27 UTC #1 lore raw

PATCH 1/1 ARM: cache-tauros2: remove ARMv6 code

Quoted 43 lines · Arnd Bergmann

Removing the ARMv6 code path reduces the code size and avoids the linker error.

Signed-off-by Arnd Bergmann <[email protected]>

---

arch/arm/mm/cache-tauros2.c +0 ~~-20~~

index 1be0f4e..7964ef2 100644
@@ -229,33 +229,6 @@ static void __init tauros2_internal_init(unsigned int features)
        }
 #endif
 
-#ifdef CONFIG_CPU_32v6
-       /*
-        * Check whether this CPU lacks support for the v7 hierarchical
-        * cache ops.  (PJ4 is in its v6 personality mode if the MMFR3
-        * register indicates no support for the v7 hierarchical cache
-        * ops.)
-        */
-       if (cpuid_scheme() && (read_mmfr3() & 0xf) == 0) {
-               /*
-                * When Tauros2 is used in an ARMv6 system, the L2
-                * enable bit is in the ARMv6 ARM-mandated position
-                * (bit [26] of the System Control Register).
-                */
-               if (!(get_cr() & 0x04000000)) {
-                       printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
-                       adjust_cr(0x04000000, 0x04000000);
-               }
-
-               mode = "ARMv6";
-               outer_cache.inv_range = tauros2_inv_range;

arch/arm/mm/cache-tauros2.c static void __init tauros2_internal_init(unsigned int features) · line 234

Quoted 10 lines

arch/arm/mm/cache-tauros2.c +0 -7

-               outer_cache.clean_range = tauros2_clean_range;
-               outer_cache.flush_range = tauros2_flush_range;
-               outer_cache.disable = tauros2_disable;
-               outer_cache.resume = tauros2_resume;
-       }
-#endif
-
 #ifdef CONFIG_CPU_32v7
        /*
         * Check whether this CPU has support for the v7 hierarchical

Acked-by Haojian Zhuang <[email protected]>

Arnd Bergmann

author

2014-03-18 15:01 UTC #2 lore raw

PATCH 1/1 ARM: cache-tauros2: remove ARMv6 code

Quoted 8 lines · Haojian Zhuang

Quoted 7 lines · Arnd Bergmann
When building a kernel with support for both ARMv6 and ARMv7 but no MMU, the call from tauros2_internal_init to adjust_cr causes a link error. While that could probably be resolved, we don't actually support cache-tauros2 on ARMv6 any more. All PJ4 CPU implementations support both ARMv6 and ARMv7 and we already assume that we are using them only in ARMv7 mode.

Quoted 4 lines

Quoted 2 lines
Removing the ARMv6 code path reduces the code size and avoids the linker error.
Acked-by Haojian Zhuang <[email protected]>

Thanks!

Russell, do you want to add this patch to your l2x0 series, or should I put it into the patch tracker by itself?

Arnd

Arnd Bergmann

author

2014-03-27 01:53 UTC #3 lore raw

PATCH 1/1 ARM: cache-tauros2: remove ARMv6 code

In reply to Haojian Zhuang

Quoted 16 lines · Haojian Zhuang

Quoted 7 lines · Arnd Bergmann
When building a kernel with support for both ARMv6 and ARMv7 but no MMU, the call from tauros2_internal_init to adjust_cr causes a link error. While that could probably be resolved, we don't actually support cache-tauros2 on ARMv6 any more. All PJ4 CPU implementations support both ARMv6 and ARMv7 and we already assume that we are using them only in ARMv7 mode.
Quoted 7 lines
Removing the ARMv6 code path reduces the code size and avoids the linker error.
-
#ifdef CONFIG_CPU_32v7
/*
* Check whether this CPU has support for the v7 hierarchical

Quoted 1 line

Acked-by Haojian Zhuang <[email protected]>

I've merged it into next/soc now, since that branch originally introduced the bug, which now prevents 'allmodconfig' from building.

I had to another oneline change to the patch, see below. This has no functional impact, but just avoids a few "unused function" warnings when building with both v6 and v7 enabled. Previously some of the functions were shared between v5 and v6 code, but the v6 version is removed now.

Arnd

arch/arm/mm/cache-tauros2.c +1 -1

index 7964ef2..b273739 100644
@@ -33,7 +33,7 @@
  * outer cache operations into the kernel image if the kernel has been
  * configured to support a pre-v7 CPU.
  */
-#if __LINUX_ARM_ARCH__ < 7
+#ifdef CONFIG_CPU_32v5
 /*
  * Low-level cache maintenance operations.
  */