ARM: sun7i/sun6i: irqchip: Irqchip driver for NMI controller

This patch adds DTS entries for NMI controller as child of GIC.

Signed-off-by Carlo Caione <[email protected]>

This patch adds DTS entries for NMI controller as child of GIC.

Signed-off-by Carlo Caione <[email protected]>

---
 arch/arm/boot/dts/sun6i-a31.dtsi | 8 ++++++++
 arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
 2 files changed, 16 insertions(+)

arch/arm/boot/dts/sun6i-a31.dtsi +8 -0

index 5256ad9..eea6033 100644
@@ -190,6 +190,14 @@
 		#size-cells = <1>;
 		ranges;
 
+		nmi_intc: interrupt-controller at 01f00c0c {
+			compatible = "allwinner,sun6i-a31-sc-nmi";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x01f00c0c 0x38>;
+			interrupts = <0 0 4>;
+		};
+
 		pio: pinctrl at 01c20800 {
 			compatible = "allwinner,sun6i-a31-pinctrl";
 			reg = <0x01c20800 0x400>;

arch/arm/boot/dts/sun7i-a20.dtsi +8 -0

index 6f25cf5..7637f12 100644
@@ -339,6 +339,14 @@
 		#size-cells = <1>;
 		ranges;
 
+		nmi_intc: interrupt-controller at 01c00030 {
+			compatible = "allwinner,sun7i-a20-sc-nmi";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x01c00030 0x0c>;
+			interrupts = <0 0 4>;
+		};
+
 		emac: ethernet at 01c0b000 {
 			compatible = "allwinner,sun4i-a10-emac";
 			reg = <0x01c0b000 0x1000>;

Hi,

Quoted 2 lines · Carlo Caione

This patch adds DTS entries for NMI controller as child of GIC.

Quoted 1 line

Signed-off-by Carlo Caione <[email protected]>

Note this breaks the kernel on sun6i / A31 since we don't have a pmic driver there yet, and thus the nmi gets constantly fired without anything clearing it.

So the sun6i section needs a status = "disabled"; until we actually have pmic support.

Quoted 11 lines · Hans de Goede

Hi,

Quoted 3 lines · Carlo Caione

This patch adds DTS entries for NMI controller as child of GIC.

Signed-off-by Carlo Caione <[email protected]>

Note this breaks the kernel on sun6i / A31 since we don't have a pmic driver there yet, and thus the nmi gets constantly fired without anything clearing it.

Quoted 2 lines

So the sun6i section needs a status = "disabled"; until we actually have pmic support.

I guess it also applies to the A20, since the PMIC patches will probably get merged later on?

Hi,

Quoted 12 lines · Maxime Ripard

Quoted 11 lines · Hans de Goede

Hi,

Quoted 3 lines · Carlo Caione

This patch adds DTS entries for NMI controller as child of GIC.

Signed-off-by Carlo Caione <[email protected]>

Note this breaks the kernel on sun6i / A31 since we don't have a pmic driver there yet, and thus the nmi gets constantly fired without anything clearing it.

Quoted 5 lines

Quoted 2 lines

So the sun6i section needs a status = "disabled"; until we actually have pmic support.

I guess it also applies to the A20, since the PMIC patches will probably get merged later on?

Could be I've never tried it on the A20 without also having the pmic driver build into the kernel. Thinking more about this, I think this actually is a bug in the nmi irqchip driver, it should not unmask the gic irq until it gets an unmask for its child irq itself.

Otherwise we can still get the same problem if ie the pmic driver is a module, etc.

Hmm, looking at the code I see that it already masks (sets enable to 0) the irq in sunxi_sc_nmi_irq_init. Note that this really should be done before the irq_set_chained_handler call though, as from then on the gic irq is unmasked, so we may get spurious irqs until the sunxi_sc_nmi_write calls are done.

I don't think this will solve the A31 problem though, I wonder if the enable reg-offset we've for the A31 is correct, maybe it should be 8 like with the A20 ?

I'll give this a try when I can find some time for this.

Hi,

Quoted 39 lines

Hi,

Quoted 12 lines · Maxime Ripard

Quoted 11 lines · Hans de Goede

Hi,

Quoted 3 lines · Carlo Caione

This patch adds DTS entries for NMI controller as child of GIC.

Signed-off-by Carlo Caione <[email protected]>

Note this breaks the kernel on sun6i / A31 since we don't have a pmic driver there yet, and thus the nmi gets constantly fired without anything clearing it.

Quoted 5 lines

Quoted 2 lines

So the sun6i section needs a status = "disabled"; until we actually have pmic support.

I guess it also applies to the A20, since the PMIC patches will probably get merged later on?

Could be I've never tried it on the A20 without also having the pmic driver build into the kernel. Thinking more about this, I think this actually is a bug in the nmi irqchip driver, it should not unmask the gic irq until it gets an unmask for its child irq itself.

Otherwise we can still get the same problem if ie the pmic driver is a module, etc.

Hmm, looking at the code I see that it already masks (sets enable to 0) the irq in sunxi_sc_nmi_irq_init. Note that this really should be done before the irq_set_chained_handler call though, as from then on the gic irq is unmasked, so we may get spurious irqs until the sunxi_sc_nmi_write calls are done.

I don't think this will solve the A31 problem though, I wonder if the enable reg-offset we've for the A31 is correct, maybe it should be 8 like with the A20 ?

Quoted 1 line

I'll give this a try when I can find some time for this.

Ok, so I've spend some time debugging this, and the problem is not the disabling of the NMI in the NMI controller itself. The problem is that the irq line used in the sun6i-a31.dtsi is wrong, irq 0 is for uart0 the nmi uses irq 32. So this fixes this hang due to unhandled irqs

I've been seeing:

Note I also remove the interrupt-parent as the gic is the default interrupt-parent, and we don't explicitly set that anywhere else either.

Besides that after having looked into this more, I strongly believe that we should disable the NMI before registering the irq handler, as registering the irq handler unmasks the irq on the gic, so if u-boot has left the NMI enabled, and the NMI pin is active we will immediately get an interrupt, before any driver has claimed the downstream interrupt of the NMI.

IOW I strongly believe we should do this:

drivers/irqchip/irq-sunxi-nmi.c +0 -2

@@ -179,12 +179,12 @@ static int __init sunxi_sc_nmi_irq_init(struct device_node *node,
        gc->chip_types[1].regs.type             = reg_offs->ctrl;
        gc->chip_types[1].handler               = handle_edge_irq;
 
-       irq_set_handler_data(irq, domain);
-       irq_set_chained_handler(irq, sunxi_sc_nmi_handle_irq);

So it looks like we need a v8, sorry for not spotting this sooner.

Added documentation for NMI irqchip.

Signed-off-by Carlo Caione <[email protected]>

Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI. Three register are present to (un)mask, control and acknowledge NMI. These two patches add a new irqchip driver in cascade with GIC.