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sunxi clock fixes

PATCH New Emilio López 3 participants 12 messages Mar 19, 2014 – Apr 14, 2014

Subsystems (4)
Device tree bindings Common clk Arm/Allwinner sunXi SoC support Arm/Allwinner SoC Clock Support
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Emilio López

author maintainer
#0 lore raw

cover sunxi clock fixes

Hi everyone,

This is a small series of patches fixing a couple of bugs that are present on the sunxi clock driver. Mike, are there any chances we can take these during the 3.15 merge window or -rc period?

Cheers,

Emilio

Emilio L?pez (4):
clk: sunxi: fix A20 PLL4 calculation
ARM: sun7i: fix PLL4 clock and add PLL8
clk: sunxi: fix some calculations
clk: sunxi: fix thinko in comment

 arch/arm/boot/dts/sun7i-a20.dtsi | 10 +++++++++-
 drivers/clk/sunxi/clk-sunxi.c    | 15 +++++++++++----
 2 files changed, 20 insertions(+), 5 deletions(-)
Signature · 1 line
1.9.0
author maintainer
#1 lore raw

PATCH 1/4 clk: sunxi: fix A20 PLL4 calculation

Allwinner actually reworked the PLL4 on A20; now it's compatible with the sun4i PLL5/6 design previous to any divisions, as well as to the new PLL8 in sun7i.

Signed-off-by Emilio L?pez <[email protected]>
---
 drivers/clk/sunxi/clk-sunxi.c | 7 +++++++
 1 file changed, 7 insertions(+)
drivers/clk/sunxi/clk-sunxi.c +7 -0
index 7ca9ed9..a393df1 100644
@@ -621,6 +621,12 @@ static const struct factors_data sun6i_a31_pll1_data __initconst = {
 	.getter = sun6i_a31_get_pll1_factors,
 };
 
+static const struct factors_data sun7i_a20_pll4_data __initconst = {
+	.enable = 31,
+	.table = &sun4i_pll5_config,
+	.getter = sun4i_get_pll5_factors,
+};
+
 static const struct factors_data sun4i_pll5_data __initconst = {
 	.enable = 31,
 	.table = &sun4i_pll5_config,

@@ -1244,6 +1250,7 @@ free_clkdata:
 static const struct of_device_id clk_factors_match[] __initconst = {
 	{.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
 	{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
+	{.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
 	{.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
 	{.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,},
 	{.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
Signature · 1 line
1.9.0
#2 lore raw

PATCH 1/4 clk: sunxi: fix A20 PLL4 calculation

Quoting Emilio L?pez (2014-03-19 11:19:30)

Quoted 5 lines

Allwinner actually reworked the PLL4 on A20; now it's compatible with the sun4i PLL5/6 design previous to any divisions, as well as to the new PLL8 in sun7i.

Signed-off-by Emilio L?pez <[email protected]>

Trivial merge conflict after applying this patch on top of your 3.15 pull request. My resolution is below. Let me know if I've made a mistake.

Regards,
Mike

Quoted 1 line

From 5a8ddf26822dcf601a44d35efa8fe162cbc84e62 Mon Sep 17 00:00:00 2001

From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <[email protected]>
Date: Wed, 19 Mar 2014 15:19:30 -0300
Subject: [PATCH] clk: sunxi: fix A20 PLL4 calculation
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Allwinner actually reworked the PLL4 on A20; now it's compatible with the sun4i PLL5/6 design previous to any divisions, as well as to the new PLL8 in sun7i.

Signed-off-by Emilio L?pez <[email protected]>
Signed-off-by Mike Turquette <[email protected]>
---
 drivers/clk/sunxi/clk-sunxi.c | 7 +++++++
 1 file changed, 7 insertions(+)
drivers/clk/sunxi/clk-sunxi.c +7 -0
index 23baad9..ef6ad52b 100644
@@ -589,6 +589,12 @@ static const struct factors_data sun6i_a31_pll1_data __initconst = {
 	.getter = sun6i_a31_get_pll1_factors,
 };
 
+static const struct factors_data sun7i_a20_pll4_data __initconst = {
+	.enable = 31,
+	.table = &sun4i_pll5_config,
+	.getter = sun4i_get_pll5_factors,
+};
+
 static const struct factors_data sun4i_pll5_data __initconst = {
 	.enable = 31,
 	.table = &sun4i_pll5_config,

@@ -1209,6 +1215,7 @@ free_clkdata:
 static const struct of_device_id clk_factors_match[] __initconst = {
 	{.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
 	{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
+	{.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
 	{.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
 	{.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
 	{.compatible = "allwinner,sun4i-a10-mod0-clk", .data = &sun4i_mod0_data,},
Signature · 1 line
1.8.3.2
author maintainer
#3 lore raw

PATCH 1/4 clk: sunxi: fix A20 PLL4 calculation

Hi Mike,

El 19/03/14 16:42, Mike Turquette escribi?:

Quoted 10 lines

Quoting Emilio L?pez (2014-03-19 11:19:30)

Quoted 5 lines

Allwinner actually reworked the PLL4 on A20; now it's compatible with the sun4i PLL5/6 design previous to any divisions, as well as to the new PLL8 in sun7i.

Signed-off-by Emilio L?pez <[email protected]>

Trivial merge conflict after applying this patch on top of your 3.15 pull request. My resolution is below. Let me know if I've made a mistake.

Looks good to me.

Thanks!

Emilio

author maintainer
#4 lore raw

PATCH 2/4 ARM: sun7i: fix PLL4 clock and add PLL8

In reply to Emilio López

Allwinner reworked the PLL4 clock in sun7i; so we need to change the compatible. Additionally, PLL8 is compatible with this new PLL4 implementation, so let's add a node for it as well.

Signed-off-by Emilio L?pez <[email protected]>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)
arch/arm/boot/dts/sun7i-a20.dtsi +9 -1
index e766c6a..4e58ee5 100644
@@ -71,7 +71,7 @@
 
 		pll4: clk at 01c20018 {
 			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-pll1-clk";
+			compatible = "allwinner,sun7i-a20-pll4-clk";
 			reg = <0x01c20018 0x4>;
 			clocks = <&osc24M>;
 			clock-output-names = "pll4";

@@ -93,6 +93,14 @@
 			clock-output-names = "pll6_sata", "pll6_other", "pll6";
 		};
 
+		pll8: clk at 01c20040 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun7i-a20-pll4-clk";
+			reg = <0x01c20040 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll8";
+		};
+
 		cpu: cpu at 01c20054 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-cpu-clk";
Signature · 1 line
1.9.0
Applied
#5 lore raw

PATCH 2/4 ARM: sun7i: fix PLL4 clock and add PLL8

Quoted 5 lines · Emilio L?pez

Allwinner reworked the PLL4 clock in sun7i; so we need to change the compatible. Additionally, PLL8 is compatible with this new PLL4 implementation, so let's add a node for it as well.

Signed-off-by Emilio L?pez <[email protected]>

Applied to sunxi/fixes-for-3.15.

Thanks!
Maxime

Signature · 10 lines
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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author maintainer
#6 lore raw

PATCH 3/4 clk: sunxi: fix some calculations

In reply to Emilio López

Some divisor calculations were misrounded, causing higher than requested rates on some clocks. Fix them up using DIV_ROUND_UP, and replace one homebrew instance of it as well with the right macro.

Reported-by Boris BREZILLON <[email protected]>
Signed-off-by Emilio L?pez <[email protected]>
---
 drivers/clk/sunxi/clk-sunxi.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/clk/sunxi/clk-sunxi.c +3 -3
index a393df1..0393f85 100644
@@ -326,7 +326,7 @@ static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
 	if (parent_rate < *freq)
 		*freq = parent_rate;
 
-	parent_rate = (parent_rate + (*freq - 1)) / *freq;
+	parent_rate = DIV_ROUND_UP(parent_rate, *freq);
 
 	/* Invalid rate! */
 	if (parent_rate > 32)

@@ -371,7 +371,7 @@ static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
 	if (*freq > parent_rate)
 		*freq = parent_rate;
 
-	div = parent_rate / *freq;
+	div = DIV_ROUND_UP(parent_rate, *freq);
 
 	if (div < 16)
 		calcp = 0;

@@ -412,7 +412,7 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
 	if (*freq > parent_rate)
 		*freq = parent_rate;
 
-	div = parent_rate / *freq;
+	div = DIV_ROUND_UP(parent_rate, *freq);
 
 	if (div < 32)
 		calcp = 0;
Signature · 1 line
1.9.0
author maintainer
#7 lore raw

PATCH 4/4 clk: sunxi: fix thinko in comment

In reply to Emilio López

This should read MOD0 and not MMC; MMC is just one example of a MOD0 clock.

Signed-off-by Emilio L?pez <[email protected]>
---
 drivers/clk/sunxi/clk-sunxi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/sunxi/clk-sunxi.c +1 -1
index 0393f85..4369c1f 100644
@@ -357,7 +357,7 @@ static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
 
 /**
  * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
- * MMC rate is calculated as follows
+ * MOD0 rate is calculated as follows
  * rate = (parent_rate >> p) / (m + 1);
  */
Signature · 1 line
1.9.0
#8 lore raw

cover sunxi clock fixes

In reply to Emilio López

Quoting Emilio L?pez (2014-03-19 11:19:29)

Quoted 5 lines

Hi everyone,

This is a small series of patches fixing a couple of bugs that are present on the sunxi clock driver. Mike, are there any chances we can take these during the 3.15 merge window or -rc period?

I can take these towards 3.15. Do you want me to take the dts patch too?

Regards,
Mike

Quoted 18 lines

Cheers,

Emilio

Emilio L?pez (4):
clk: sunxi: fix A20 PLL4 calculation
ARM: sun7i: fix PLL4 clock and add PLL8
clk: sunxi: fix some calculations
clk: sunxi: fix thinko in comment

 arch/arm/boot/dts/sun7i-a20.dtsi | 10 +++++++++-
 drivers/clk/sunxi/clk-sunxi.c    | 15 +++++++++++----
 2 files changed, 20 insertions(+), 5 deletions(-)
Signature · 1 line
1.9.0
author maintainer
#9 lore raw

cover sunxi clock fixes

Hi Mike,

El 19/03/14 16:04, Mike Turquette escribi?:

Quoted 8 lines

Quoting Emilio L?pez (2014-03-19 11:19:29)

Quoted 5 lines

Hi everyone,

This is a small series of patches fixing a couple of bugs that are present on the sunxi clock driver. Mike, are there any chances we can take these during the 3.15 merge window or -rc period?

I can take these towards 3.15. Do you want me to take the dts patch too?

I'd rather have Maxime take it to avoid potential conflicts. That patch can wait in any case; there's no actual pll4 consumer in tree just yet.

Cheers,

Emilio

#10 lore raw

cover sunxi clock fixes

Hi,

Quoted 10 lines · Emilio L?pez

Hi Mike,

El 19/03/14 16:04, Mike Turquette escribi?:

Quoted 7 lines

Quoting Emilio L?pez (2014-03-19 11:19:29)

Quoted 5 lines

Hi everyone,

This is a small series of patches fixing a couple of bugs that are present on the sunxi clock driver. Mike, are there any chances we can take these during the 3.15 merge window or -rc period?

Quoted 5 lines
Quoted 1 line

I can take these towards 3.15. Do you want me to take the dts patch too?

I'd rather have Maxime take it to avoid potential conflicts. That patch can wait in any case; there's no actual pll4 consumer in tree just yet.

I sent my last pull request for the merge window, but I can queue it up as a fix for a later 3.15-rc*

Maxime

Signature · 10 lines
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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#11 lore raw

cover sunxi clock fixes

Quoting Maxime Ripard (2014-03-20 08:15:51)

Quoted 13 lines

Hi,

Quoted 10 lines · Emilio L?pez

Hi Mike,

El 19/03/14 16:04, Mike Turquette escribi?:

Quoted 7 lines

Quoting Emilio L?pez (2014-03-19 11:19:29)

Quoted 5 lines

Hi everyone,

This is a small series of patches fixing a couple of bugs that are present on the sunxi clock driver. Mike, are there any chances we can take these during the 3.15 merge window or -rc period?

Quoted 8 lines
Quoted 5 lines
Quoted 1 line

I can take these towards 3.15. Do you want me to take the dts patch too?

I'd rather have Maxime take it to avoid potential conflicts. That patch can wait in any case; there's no actual pll4 consumer in tree just yet.

I sent my last pull request for the merge window, but I can queue it up as a fix for a later 3.15-rc*

Just FYI, I took the three clock patches into clk-next yesterday so they should land in linux-next soon.

Regards,
Mike

Quoted 7 lines

Maxime

Signature · 3 lines
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com