clk: dt: add support for default rate/parent

Hi,

This set is a mix-match of new DT properties for generic and TI specific clock drivers. Basically provided for commenting purposes. The patches provide a way to configure clock parents / rates during boot through DT.

"default-rate" : sets rate of a clock during boot, supported for any DT
clock type (through generic clock driver)
"ti,default-parent" : selects a default parent for a multiplexer clock,
only supported for TI specific mux clock for now, as generic mux clock does not support DT clocks

Patch #4 provided as a reference how to move the default rates / parents from kernel code to DT.

Default-rate logic in patch #2 looks somewhat complicated, as the clocks need to be sorted based on their parents to avoid cases where a child clock would set its rate first, just to be overridden by its parent changing rate later and resulting in incorrect rate for the child clock.

If the default-rate generic property is not going to fly, it can be moved to TI only drivers also.

-Tero

ti,mux-clock now supports ti,default-parent property, which can be used to configure the default parent of the clock during boot. This property can be added to board specific files, or under the clock data itself.

---
 Documentation/devicetree/bindings/clock/ti/mux.txt |    7 ++++++
 drivers/clk/ti/mux.c                               |   24 ++++++++++++++++++--
 2 files changed, 29 insertions(+), 2 deletions(-)

index 2d0d170..4e291eb 100644
@@ -48,6 +48,8 @@ Optional properties:
   zero
 - ti,set-rate-parent : clk_set_rate is propagated to parent clock,
   not supported by the composite-mux-clock subtype
+- ti,default-parent : configures mux parent during boot to be the provided
+  phandle clock
 
 Examples:
 

@@ -65,6 +67,7 @@ abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck at 4a306108 {
 	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
 	ti,bit-shift = <24>;
 	reg = <0x0108>;
+	ti,default-parent = <&sys_32k_ck>;
 };
 
 mcbsp5_mux_fck: mcbsp5_mux_fck {

@@ -74,3 +77,7 @@ mcbsp5_mux_fck: mcbsp5_mux_fck {
 	ti,bit-shift = <4>;
 	reg = <0x02d8>;
 };
+
+&mcbsp5_mux_fck {
+	ti,default-parent = <&mcbsp_clks>;
+};

index 0197a47..557a7ce 100644
@@ -108,7 +108,8 @@ static struct clk *_register_mux(struct device *dev, const char *name,
 				 const char **parent_names, u8 num_parents,
 				 unsigned long flags, void __iomem *reg,
 				 u8 shift, u32 mask, u8 clk_mux_flags,
-				 u32 *table, spinlock_t *lock)
+				 u32 *table, int default_parent,
+				 spinlock_t *lock)
 {
 	struct clk_mux *mux;
 	struct clk *clk;

@@ -136,6 +137,9 @@ static struct clk *_register_mux(struct device *dev, const char *name,
 	mux->table = table;
 	mux->hw.init = &init;
 
+	if (default_parent >= 0)
+		ti_clk_mux_set_parent(&mux->hw, default_parent);
+
 	clk = clk_register(dev, &mux->hw);
 
 	if (IS_ERR(clk))

@@ -161,6 +165,8 @@ static void of_mux_clk_setup(struct device_node *node)
 	u32 mask = 0;
 	u32 shift = 0;
 	u32 flags = 0;
+	struct device_node *default_parent;
+	int default_parent_idx = -1;
 
 	num_parents = of_clk_get_parent_count(node);
 	if (num_parents < 2) {

@@ -174,6 +180,19 @@ static void of_mux_clk_setup(struct device_node *node)
 	for (i = 0; i < num_parents; i++)
 		parent_names[i] = of_clk_get_parent_name(node, i);
 
+	default_parent = of_parse_phandle(node, "ti,default-parent", 0);
+
+	if (default_parent) {
+		for (i = 0; i < num_parents; i++) {
+			struct device_node *tmp;
+			tmp = of_parse_phandle(node, "clocks", i);
+			if (tmp == default_parent) {
+				default_parent_idx = i;
+				break;
+			}
+		}
+	}
+
 	reg = ti_clk_get_reg_addr(node, 0);
 
 	if (!reg)

@@ -195,7 +214,8 @@ static void of_mux_clk_setup(struct device_node *node)
 	mask = (1 << fls(mask)) - 1;
 
 	clk = _register_mux(NULL, node->name, parent_names, num_parents, flags,
-			    reg, shift, mask, clk_mux_flags, NULL, NULL);
+			    reg, shift, mask, clk_mux_flags, NULL,
+			    default_parent_idx, NULL);
 
 	if (!IS_ERR(clk))
 		of_clk_add_provider(node, of_clk_src_simple_get, clk);

1.7.9.5

default-rate property can now be used to set initial rates for clocks. This is added by default for all clocks which get initialized through of_clk_init().

---
 .../devicetree/bindings/clock/clock-bindings.txt   |    9 ++
 drivers/clk/clk.c                                  |   86 ++++++++++++++++++++
 include/linux/clk-provider.h                       |    2 +
 3 files changed, 97 insertions(+)

index 7c52c29..d676112 100644
@@ -44,6 +44,15 @@ For example:
   clocks by index. The names should reflect the clock output signal
   names for the device.
 
+default-rate:	Sets the rate of the clock during boot to the provided
+		rate.
+
+For example:
+
+    clk-divider {
+        default-rate = <1000000>;
+    };
+
 ==Clock consumers==
 
 Required properties:

index 939533d..1bbd194 100644
@@ -506,6 +506,8 @@ struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
 int of_clk_get_parent_count(struct device_node *np);
 const char *of_clk_get_parent_name(struct device_node *np, int index);
+int of_clk_parse_init_rate(struct device_node *node, struct clk *clk);
+int of_clk_set_init_rates(void);
 
 void of_clk_init(const struct of_device_id *matches);
 

1.7.9.5

default-rate property can now be used to define default rates for clocks, which get configured during boot.

---
 arch/arm/mach-omap2/prm_common.c |    2 ++
 drivers/clk/ti/clk.c             |    1 +
 2 files changed, 3 insertions(+)

index b4c4ab9..4703545 100644
@@ -528,5 +528,7 @@ int __init of_prcm_init(void)
 
 	ti_dt_clockdomains_setup();
 
+	of_clk_set_init_rates();
+
 	return 0;
 }

index b1a6f71..23998b7 100644
@@ -156,6 +156,7 @@ void ti_dt_clk_init_provider(struct device_node *parent, int index)
 		clk_init_cb = (of_clk_init_cb_t)match->data;
 		pr_debug("%s: initializing: %s\n", __func__, np->name);
 		clk_init_cb(np);
+		of_clk_parse_init_rate(np, NULL);
 	}
 
 	list_for_each_entry_safe(retry, tmp, &retry_list, link) {

1.7.9.5

This can go with the drivers/clk patches as far as I'm concerned:

Setup dpll_usb_ck and dpll_abe_ck using DT properties instead of hardcoding the parents and rates in kernel.

---
 arch/arm/boot/dts/omap4.dtsi |   12 ++++++++++++
 drivers/clk/ti/clk-44xx.c    |   42 ------------------------------------------
 2 files changed, 12 insertions(+), 42 deletions(-)

index d3f8a6e..282ce66 100644
@@ -761,3 +761,15 @@
 };
 
 /include/ "omap44xx-clocks.dtsi"
+
+&dpll_usb_ck {
+	default-rate = <960000000>;
+};
+
+&dpll_abe_ck {
+	default-rate = <98304000>;
+};
+
+&abe_dpll_refclk_mux_ck {
+	ti,default-parent = <&sys_32k_ck>;
+};

1.7.9.5

Ping.

Mike, any feedback on this?

-Tero

Quoting Tero Kristo (2014-03-05 05:10:17)

Hi Tero,

Have you seen Sylwester's approach[1]? I prefer it since it is more device-oriented and less "centralized". The clock consumer enumerates the default parent or rate of a consumed clock. This can be made to work like your approach by having the clock driver consume these clocks and set them up with default rates or parents. What do you think?

Regards,
Mike

[1] https://lkml.org/lkml/2014/3/3/324

Just saw the patches yesterday. I think that approach would work in most cases, however I guess there might be cases where you need to setup the rate/parent of a clock very early in boot (basically when you are registering the clock itself) to avoid any race issues with drivers (or the clock framework itself) coming in and using a clock that is not properly setup yet. But well, I guess these can be handled by some init time tweaks.

I just converted the OMAP4 code to the format provided by Sylwester's patches and it seems to work fine. The patch should be changed eventually to probe at the time when the CM/PRM instances are probed. Inlined here as reference:

From 1b05e03bbd3fb5a4f5192444e7d4365f177c1756 Mon Sep 17 00:00:00 2001
From: Tero Kristo <[email protected]>
Date: Fri, 21 Mar 2014 09:52:47 +0200
Subject: [PATCH] CLK: TI: OMAP4: setup default clocks / rates using the clock
consumer approach

---
  arch/arm/boot/dts/omap4.dtsi |    8 ++++++++
  drivers/clk/ti/clk-44xx.c    |   44 
------------------------------------------
  drivers/clk/ti/clk.c         |   41 
+++++++++++++++++++++++++++++++++++++++
  3 files changed, 49 insertions(+), 44 deletions(-)

index d3f8a6e..4826168 100644
@@ -88,6 +88,14 @@
  		};
  	};
 
+	default-clocks {
+		compatible = "ti,default-clocks";
+		clocks = <&abe_dpll_refclk_mux_ck>, <&dpll_usb_ck>,
+			<&dpll_abe_ck>;
+		clock-parents = <&sys_32k_ck>;
+		clock-rates = <0>, <960000000>, <98304000>;
+	};
+
  	/*
  	 * XXX: Use a flat representation of the OMAP4 interconnect.
  	 * The real OMAP interconnect network is quite complex.

index b1a6f71..469fd4e 100644
@@ -21,6 +21,8 @@
  #include <linux/of.h>
  #include <linux/of_address.h>
  #include <linux/list.h>
+#include <linux/of_platform.h>
+#include <linux/module.h>
 
  #undef pr_fmt
  #define pr_fmt(fmt) "%s: " fmt, __func__

@@ -165,3 +167,41 @@ void ti_dt_clk_init_provider(struct device_node 

*parent, int index)
kfree(retry);
}
}
+
+static int ti_clk_probe(struct platform_device *pdev) +{
+ return 0;
+}
+
+static int ti_clk_remove(struct platform_device *dev) +{
+ return 0;
+}
+
+static const struct of_device_id ti_clk_match[] = {
+ { .compatible = "ti,default-clocks" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ti_clk_match);
+
+static struct platform_driver ti_clk_driver = {
+ .probe = ti_clk_probe,
+ .remove = ti_clk_remove,
+ .driver = {
+ .name = "ti-clk",
+ .of_match_table = of_match_ptr(ti_clk_match),
+ },
+};
+
+static int __init ti_clk_init(void)
+{
+ return platform_driver_register(&ti_clk_driver);
+}
+
+static void __exit ti_clk_exit(void)
+{
+ platform_driver_unregister(&ti_clk_driver);
+}
+
+module_init(ti_clk_init); +module_exit(ti_clk_exit);

1.7.9.5

That assumes driver writers are aware of the clock tree topology. IME that's seldomly the case.

Cheers,

Peter.

Quoting Peter De Schrijver (2014-03-21 01:12:17)

It assumes no such thing.

The point of Sylwester's patch is that if a driver consumes a clock and needs to do the very typical setup regarding that clock's rate or parent, then we now have a sensible way to express that in DT.

One of the strengths of DT is that the C code does not have to know all of the details about topology or how things are hooked up. We can hide some of those cute embedded nonsense hacks in DTS and the device integrator can manage it there.

Regards,
Mike

It would be much better to specify this as part of the clock provider binding though, as the person writing those, generally knows what topology needs to be setup. The driver writer writing the consumer node often doesn't.

Cheers,

Peter.