Add Hisilicon HiP04 SoC

Add new ARCH_MULTI_V7_LPAE config. It will select ARM_LPAE only both ARCH_MULTI_V6 & ARCH_MULTI_V7 is disabled.

ARCH_MULTI_V7 means non-LPAE platform.

Signed-off-by Haojian Zhuang <[email protected]>

 arch/arm/Kconfig | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

arch/arm/Kconfig +1 -1

index 5248923..a8b2b45 100644
@@ -918,12 +918,19 @@ config ARCH_MULTI_V6
 	select CPU_V6K
 
 config ARCH_MULTI_V7
-	bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
+	bool "ARMv7 non-LPAE based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 	default y
 	select ARCH_MULTI_V6_V7
 	select CPU_V7
 	select HAVE_SMP
 

Quoted 6 lines · On Tuesday 08 April 2014 16:00:42 Haojian Zhuang wrote:

Add new ARCH_MULTI_V7_LPAE config. It will select ARM_LPAE only both ARCH_MULTI_V6 & ARCH_MULTI_V7 is disabled.

ARCH_MULTI_V7 means non-LPAE platform.

Signed-off-by Haojian Zhuang <[email protected]>

I think it's good to have this option, but it should be added more carefully.

Quoted 18 lines

 arch/arm/Kconfig | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

arch/arm/Kconfig +1 -1

index 5248923..a8b2b45 100644
@@ -918,12 +918,19 @@ config ARCH_MULTI_V6
      select CPU_V6K
 
 config ARCH_MULTI_V7
-     bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
+     bool "ARMv7 non-LPAE based platforms (Cortex-A, PJ4, Scorpion, Krait)"
      default y
      select ARCH_MULTI_V6_V7
      select CPU_V7
      select HAVE_SMP
 

arch/arm/Kconfig config ARCH_MULTI_V6 · line 936

Quoted 10 lines

arch/arm/Kconfig +7 -0

+config ARCH_MULTI_V7_LPAE
+     bool "ARMv7 LPAE based platforms (HIP04)"
+     select ARCH_MULTI_V6_V7
+     select CPU_V7
+     select HAVE_SMP
+     select ARM_LPAE if !(ARCH_MULTI_V6 || ARCH_MULTI_V7)
+
 config ARCH_MULTI_V6_V7
      bool
      select MIGHT_HAVE_CACHE_L2X0

Two points here:

a) The other options all list the CPU types (Cortex-A, PJ4, ...), while the one you introduce lists the platform name. I think they should all list the CPU cores, like

bool "ARMv7 non-LPAE based platforms (Cortex-A5/A8/A9, PJ4, Scorpion)"

bool "ARMv7 non-LPAE based platforms (Cortex-A7/A12/A15/A17, Brahma-B15, PJ4B, Krait)" (I'm not completely sure about Krait, need to check that).

b) When you introduce this, please change the other platforms over to use the symbol correctly. We already have a number of platforms based on A7, A15, PJ4B and Krait.

arch/arm/mach-hisi/Kconfig +10 -2

index feee4db..da16efd 100644
@@ -1,8 +1,16 @@
-config ARCH_HI3xxx
-       bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7
+config ARCH_HISI
+       bool "Hisilicon SoC Support"
+       depends on ARCH_MULTIPLATFORM
        select ARM_AMBA
        select ARM_GIC
        select ARM_TIMER_SP804
+
+if ARCH_HISI
+
+menu "Hisilicon platform type"
+
+config ARCH_HI3xxx
+       bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7
        select CACHE_L2X0
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP

arch/arm/mach-hisi/Kconfig +10 -2

index feee4db..da16efd 100644
@@ -1,8 +1,16 @@
-config ARCH_HI3xxx
-       bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7
+config ARCH_HISI
+       bool "Hisilicon SoC Support"
+       depends on ARCH_MULTIPLATFORM
        select ARM_AMBA
        select ARM_GIC
        select ARM_TIMER_SP804
+
+if ARCH_HISI
+
+menu "Hisilicon platform type"
+
+config ARCH_HI3xxx
+       bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7
        select CACHE_L2X0
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP

Quoted 24 lines · On Tuesday 08 April 2014 16:00:43 Haojian Zhuang wrote:

arch/arm/mach-hisi/Kconfig +10 -2

index feee4db..da16efd 100644
@@ -1,8 +1,16 @@
-config ARCH_HI3xxx
-       bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7
+config ARCH_HISI
+       bool "Hisilicon SoC Support"
+       depends on ARCH_MULTIPLATFORM
        select ARM_AMBA
        select ARM_GIC
        select ARM_TIMER_SP804
+
+if ARCH_HISI
+
+menu "Hisilicon platform type"
+
+config ARCH_HI3xxx
+       bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7
        select CACHE_L2X0
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP

arch/arm/mach-hisi/Kconfig config ARCH_HI3xxx · line 22

Quoted 5 lines

arch/arm/mach-hisi/Kconfig +2 -0

@@ -10,3 +18,7 @@ config ARCH_HI3xxx
        select PINCTRL_SINGLE
        help
          Support for Hisilicon Hi36xx/Hi37xx processor family
+
+endmenu

On second thought: You don't actually have any sub-options under the main SoC specific option, so using 'menuconfig' as I suggested first makes no sense.

Just leave ARCH_HI3xxx and ARCH_HIP04 as top-level options and drop this patch. There is no real need for a new menu here. That also means you can drop patch 9.

Arnd

Quoted 35 lines · Arnd Bergmann

Quoted 24 lines · On Tuesday 08 April 2014 16:00:43 Haojian Zhuang wrote:

arch/arm/mach-hisi/Kconfig +10 -2

index feee4db..da16efd 100644
@@ -1,8 +1,16 @@
-config ARCH_HI3xxx
-       bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7
+config ARCH_HISI
+       bool "Hisilicon SoC Support"
+       depends on ARCH_MULTIPLATFORM
        select ARM_AMBA
        select ARM_GIC
        select ARM_TIMER_SP804
+
+if ARCH_HISI
+
+menu "Hisilicon platform type"
+
+config ARCH_HI3xxx
+       bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7
        select CACHE_L2X0
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP

arch/arm/mach-hisi/Kconfig config ARCH_HI3xxx · line 22

Quoted 5 lines

arch/arm/mach-hisi/Kconfig +2 -0

@@ -10,3 +18,7 @@ config ARCH_HI3xxx
        select PINCTRL_SINGLE
        help
          Support for Hisilicon Hi36xx/Hi37xx processor family
+
+endmenu

On second thought: You don't actually have any sub-options under the main SoC specific option, so using 'menuconfig' as I suggested first makes no sense.

Quoted 5 lines

Just leave ARCH_HI3xxx and ARCH_HIP04 as top-level options and drop this patch. There is no real need for a new menu here. That also means you can drop patch 9.

Arnd

Since they're two archs. In arch/arm/Kconfig, I have to write as below.

machine-$(CONFIG_ARCH_HI3xxx) += mach-hisi
machine-$(CONFIG_ARCH_HIP04) += mach-hisi

Then mach-hisi is duplicated in Kconfig. I'll get build error in below.

Makefile:877: target `arch/arm/mach-hisi' given more than once in the same rule.

In order to support 16 CPUs, Hisilicon extends the GIC to support the number of CPU interfaces from 8 to 16.

Signed-off-by Haojian Zhuang <[email protected]>

---
 drivers/irqchip/irq-gic.c | 78 ++++++++++++++++++++++++++++-------------------
 1 file changed, 47 insertions(+), 31 deletions(-)

drivers/irqchip/irq-gic.c +0 -0

index 8fd27bf..44eff46 100644
@@ -76,9 +76,12 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock);
  * The GIC mapping of CPU interfaces does not necessarily match

drivers/irqchip/irq-gic.c +0 -2

 /*
  * Supported arch specific GIC irq extension.

@@ -245,16 +248,19 @@ static int gic_retrigger(struct irq_data *d)
 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
                            bool force)
 {
-       void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
-       unsigned int shift = (gic_irq(d) % 4) * 8;

drivers/irqchip/irq-gic.c +1 -5

@@ -354,15 +360,17 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
        irq_set_chained_handler(irq, gic_handle_cascade_irq);
 }
 
-static u8 gic_get_cpumask(struct gic_chip_data *gic)
+static u16 gic_get_cpumask(struct gic_chip_data *gic)
 {
        void __iomem *base = gic_data_dist_base(gic);
-       u32 mask, i;
-
-       for (i = mask = 0; i < 32; i += 4) {
-               mask = readl_relaxed(base + GIC_DIST_TARGET + i);

drivers/irqchip/irq-gic.c +14 -11

                if (mask)
                        break;
        }

@@ -375,7 +383,7 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic)
 
 static void __init gic_dist_init(struct gic_chip_data *gic)
 {
-       unsigned int i;
+       unsigned int i, step;
        u32 cpumask;
        unsigned int gic_irqs = gic->gic_irqs;
        void __iomem *base = gic_data_dist_base(gic);

@@ -392,10 +400,11 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
         * Set all global interrupts to this CPU only.
         */
        cpumask = gic_get_cpumask(gic);
-       cpumask |= cpumask << 8;
-       cpumask |= cpumask << 16;
-       for (i = 32; i < gic_irqs; i += 4)
-               writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
+       for (i = nr_gic_cpu_if; i < BITS_PER_LONG; i <<= 1)
+               cpumask |= cpumask << i;
+       step = BITS_PER_LONG / nr_gic_cpu_if;
+       for (i = 32; i < gic_irqs; i += step)
+               writel_relaxed(cpumask, base + GIC_DIST_TARGET + i / step * 4);
 
        /*
         * Set priority on all global interrupts.

@@ -423,7 +432,7 @@ static void gic_cpu_init(struct gic_chip_data *gic)
        /*
         * Get what the GIC says our CPU mask is.
         */
-       BUG_ON(cpu >= NR_GIC_CPU_IF);
+       BUG_ON(cpu >= nr_gic_cpu_if);
        cpu_mask = gic_get_cpumask(gic);
        gic_cpu_map[cpu] = cpu_mask;
 

@@ -431,7 +440,7 @@ static void gic_cpu_init(struct gic_chip_data *gic)
         * Clear our mask from the other map entries in case they're
         * still undefined.
         */
-       for (i = 0; i < NR_GIC_CPU_IF; i++)
+       for (i = 0; i < nr_gic_cpu_if; i++)
                if (i != cpu)
                        gic_cpu_map[i] &= ~cpu_mask;
 

@@ -469,7 +478,7 @@ static void gic_dist_save(unsigned int gic_nr)
 {
        unsigned int gic_irqs;
        void __iomem *dist_base;
-       int i;
+       int i, step;
 
        if (gic_nr >= MAX_GIC_NR)
                BUG();

@@ -484,7 +493,8 @@ static void gic_dist_save(unsigned int gic_nr)
                gic_data[gic_nr].saved_spi_conf[i] =
                        readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
 
-       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+       step = BITS_PER_LONG / nr_gic_cpu_if;
+       for (i = 0; i < DIV_ROUND_UP(gic_irqs, step); i++)
                gic_data[gic_nr].saved_spi_target[i] =
                        readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
 

@@ -503,7 +513,7 @@ static void gic_dist_save(unsigned int gic_nr)
 static void gic_dist_restore(unsigned int gic_nr)
 {
        unsigned int gic_irqs;
-       unsigned int i;
+       unsigned int i, step;
        void __iomem *dist_base;
 
        if (gic_nr >= MAX_GIC_NR)

@@ -525,7 +535,8 @@ static void gic_dist_restore(unsigned int gic_nr)
                writel_relaxed(0xa0a0a0a0,
                        dist_base + GIC_DIST_PRI + i * 4);
 
-       for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
+       step = BITS_PER_LONG / nr_gic_cpu_if;
+       for (i = 0; i < DIV_ROUND_UP(gic_irqs, step); i++)
                writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
                        dist_base + GIC_DIST_TARGET + i * 4);
 

drivers/irqchip/irq-gic.c +4 -4

        raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
 }
 #endif

@@ -681,7 +692,7 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
  */
 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
 {
-       BUG_ON(cpu_id >= NR_GIC_CPU_IF);
+       BUG_ON(cpu_id >= nr_gic_cpu_if);
        cpu_id = 1 << cpu_id;
        /* this always happens on GIC0 */
        writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);

@@ -700,7 +711,7 @@ int gic_get_cpu_id(unsigned int cpu)
 {
        unsigned int cpu_bit;
 
-       if (cpu >= NR_GIC_CPU_IF)
+       if (cpu >= nr_gic_cpu_if)
                return -1;
        cpu_bit = gic_cpu_map[cpu];
        if (cpu_bit & (cpu_bit - 1))

@@ -971,8 +982,8 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
         * Initialize the CPU interface map to all CPUs.
         * It will be refined as each CPU probes its ID.
         */
-       for (i = 0; i < NR_GIC_CPU_IF; i++)
-               gic_cpu_map[i] = 0xff;
+       for (i = 0; i < nr_gic_cpu_if; i++)
+               gic_cpu_map[i] = (1 << MAX_NR_GIC_CPU_IF) - 1;
 
        /*
         * For primary GICs, skip over SGIs.

In order to support 4 clusters with 4 Cortex A15 Cores in each cluster, enlarge maximum clusters from 2 to 4 in MCPM.

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/include/asm/mcpm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/include/asm/mcpm.h +0 -0

index 608516e..68f82cf 100644

Quoted 2 lines · Haojian Zhuang

In order to support 4 clusters with 4 Cortex A15 Cores in each cluster, enlarge maximum clusters from 2 to 4 in MCPM.

CC Nico on mcpm patches please. I'm happy to be CC'd as well.

Quoted 10 lines

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/include/asm/mcpm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/include/asm/mcpm.h +0 -0

index 608516e..68f82cf 100644

arch/arm/include/asm/mcpm.h line 23

Quoted 5 lines

arch/arm/include/asm/mcpm.h +1 -1

@@ -20,7 +20,7 @@
  * to consider dynamic allocation.
  */
 #define MAX_CPUS_PER_CLUSTER	4
-#define MAX_NR_CLUSTERS		2
+#define MAX_NR_CLUSTERS		4

Because of the need for alignment to the biggest cacheline size in the system, the MCPM low-level locking structures consume a non-trivial amount of memory.

Therefore, I'm not keen on the idea of simply increasing this #define every time a platform appears with a larger number of clusters. If hip04 is not built into the kernel, this just wastes memory.

I'll leave it to Nico to decide whether we can increase the #define to 4 or whether this needs a proper fix now. Ideally, we would have a way of choosing the maximum value required by the set of boards built into the kernel, or switch to dynamic allocation.

Quoted 5 lines · Dave Martin

Quoted 2 lines · Haojian Zhuang

In order to support 4 clusters with 4 Cortex A15 Cores in each cluster, enlarge maximum clusters from 2 to 4 in MCPM.

CC Nico on mcpm patches please. I'm happy to be CC'd as well.

Indeed.

Quoted 20 lines

Quoted 10 lines

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/include/asm/mcpm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/include/asm/mcpm.h +0 -0

index 608516e..68f82cf 100644

arch/arm/include/asm/mcpm.h line 23

Quoted 5 lines

arch/arm/include/asm/mcpm.h +1 -1

@@ -20,7 +20,7 @@
  * to consider dynamic allocation.
  */
 #define MAX_CPUS_PER_CLUSTER	4
-#define MAX_NR_CLUSTERS		2
+#define MAX_NR_CLUSTERS		4

Because of the need for alignment to the biggest cacheline size in the system, the MCPM low-level locking structures consume a non-trivial amount of memory.

Quoted 8 lines

Therefore, I'm not keen on the idea of simply increasing this #define every time a platform appears with a larger number of clusters. If hip04 is not built into the kernel, this just wastes memory.

I'll leave it to Nico to decide whether we can increase the #define to 4 or whether this needs a proper fix now. Ideally, we would have a way of choosing the maximum value required by the set of boards built into the kernel, or switch to dynamic allocation.

I think we should go with the ability to select a maximum based on the configured platforms. That could be as simple as having a CONFIG_MCPM_QUAD_CLUSTER symbol to be selected by those platforms that need it.

The memory usage is still relatively low: 4 clusters containing 6 independent cache lines each, so for a 64-byte cache line this means 1536 bytes. That is rather insignificant compared to the amount of memory fitted to typical multi-cluster systems, especially quad cluster systems. Unless there is yet more expansion of clusters and/or CPUs per cluster to come amongst MCPM users, I don't think we've yet reached the tipping point where the complexity of dynamic memory allocation for this is worth it.

However, changing MAX_NR_CLUSTERS cannot be done without also modifying the code in bL_switcher_init() or the b.L switcher won't work anymore on dual cluster systems as soon as a quad cluster system is configured in. Simply removing the test against MAX_NR_CLUSTERS should be sufficient as there is already a runtime validation test in bL_switcher_halve_cpus().

Quoted 5 lines · Dave Martin

Quoted 2 lines · Haojian Zhuang

In order to support 4 clusters with 4 Cortex A15 Cores in each cluster, enlarge maximum clusters from 2 to 4 in MCPM.

CC Nico on mcpm patches please. I'm happy to be CC'd as well.

Indeed.

Quoted 20 lines

Quoted 10 lines

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/include/asm/mcpm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/include/asm/mcpm.h +0 -0

index 608516e..68f82cf 100644

arch/arm/include/asm/mcpm.h line 23

Quoted 5 lines

arch/arm/include/asm/mcpm.h +1 -1

@@ -20,7 +20,7 @@
  * to consider dynamic allocation.
  */
 #define MAX_CPUS_PER_CLUSTER       4
-#define MAX_NR_CLUSTERS            2
+#define MAX_NR_CLUSTERS            4

Because of the need for alignment to the biggest cacheline size in the system, the MCPM low-level locking structures consume a non-trivial amount of memory.

Quoted 8 lines

Therefore, I'm not keen on the idea of simply increasing this #define every time a platform appears with a larger number of clusters. If hip04 is not built into the kernel, this just wastes memory.

I'll leave it to Nico to decide whether we can increase the #define to 4 or whether this needs a proper fix now. Ideally, we would have a way of choosing the maximum value required by the set of boards built into the kernel, or switch to dynamic allocation.

I think we should go with the ability to select a maximum based on the configured platforms. That could be as simple as having a CONFIG_MCPM_QUAD_CLUSTER symbol to be selected by those platforms that need it.

Quoted 39 lines · Nicolas Pitre

Quoted 5 lines · Dave Martin

Quoted 2 lines · Haojian Zhuang

In order to support 4 clusters with 4 Cortex A15 Cores in each cluster, enlarge maximum clusters from 2 to 4 in MCPM.

CC Nico on mcpm patches please. I'm happy to be CC'd as well.

Indeed.

Quoted 20 lines

Quoted 10 lines

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/include/asm/mcpm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/include/asm/mcpm.h +0 -0

index 608516e..68f82cf 100644

arch/arm/include/asm/mcpm.h line 23

Quoted 5 lines

arch/arm/include/asm/mcpm.h +1 -1

@@ -20,7 +20,7 @@
  * to consider dynamic allocation.
  */
 #define MAX_CPUS_PER_CLUSTER       4
-#define MAX_NR_CLUSTERS            2
+#define MAX_NR_CLUSTERS            4

Because of the need for alignment to the biggest cacheline size in the system, the MCPM low-level locking structures consume a non-trivial amount of memory.

Quoted 8 lines

Therefore, I'm not keen on the idea of simply increasing this #define every time a platform appears with a larger number of clusters. If hip04 is not built into the kernel, this just wastes memory.

I'll leave it to Nico to decide whether we can increase the #define to 4 or whether this needs a proper fix now. Ideally, we would have a way of choosing the maximum value required by the set of boards built into the kernel, or switch to dynamic allocation.

Quoted 5 lines

I think we should go with the ability to select a maximum based on the configured platforms. That could be as simple as having a CONFIG_MCPM_QUAD_CLUSTER symbol to be selected by those platforms that need it.

I'll set MAX_NR_CLUSTERS from Kconfig.

If BIG_LITTLE isn't enabled & HIP04 is enabled, MAX_NR_CLUSTERS could be set to 4.

Quoted 39 lines · Nicolas Pitre

Quoted 5 lines · Dave Martin

Quoted 2 lines · Haojian Zhuang

In order to support 4 clusters with 4 Cortex A15 Cores in each cluster, enlarge maximum clusters from 2 to 4 in MCPM.

CC Nico on mcpm patches please. I'm happy to be CC'd as well.

Indeed.

Quoted 20 lines

Quoted 10 lines

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/include/asm/mcpm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/include/asm/mcpm.h +0 -0

index 608516e..68f82cf 100644

arch/arm/include/asm/mcpm.h line 23

Quoted 5 lines

arch/arm/include/asm/mcpm.h +1 -1

@@ -20,7 +20,7 @@
  * to consider dynamic allocation.
  */
 #define MAX_CPUS_PER_CLUSTER       4
-#define MAX_NR_CLUSTERS            2
+#define MAX_NR_CLUSTERS            4

Because of the need for alignment to the biggest cacheline size in the system, the MCPM low-level locking structures consume a non-trivial amount of memory.

Quoted 8 lines

Therefore, I'm not keen on the idea of simply increasing this #define every time a platform appears with a larger number of clusters. If hip04 is not built into the kernel, this just wastes memory.

I'll leave it to Nico to decide whether we can increase the #define to 4 or whether this needs a proper fix now. Ideally, we would have a way of choosing the maximum value required by the set of boards built into the kernel, or switch to dynamic allocation.

Quoted 5 lines

I think we should go with the ability to select a maximum based on the configured platforms. That could be as simple as having a CONFIG_MCPM_QUAD_CLUSTER symbol to be selected by those platforms that need it.

I'll set MAX_NR_CLUSTERS from Kconfig.

If BIG_LITTLE isn't enabled & HIP04 is enabled, MAX_NR_CLUSTERS could be set to 4.
Otherwise, it's always 2. Since there're only 16 A15 cores in HiP04.

arch/arm/mach-hisi/hisilicon.c +1 -0

index 741faf3..10a605f 100644
@@ -14,6 +14,7 @@
 #include <linux/clk-provider.h>
 #include <linux/clocksource.h>
 #include <linux/irqchip.h>
+#include <linux/memblock.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
 

@@ -88,3 +89,21 @@ DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
 	.smp		= smp_ops(hi3xxx_smp_ops),
 	.restart	= hi3xxx_restart,
 MACHINE_END

Quoted 21 lines · On Tuesday 08 April 2014 16:00:47 Haojian Zhuang wrote:

arch/arm/mach-hisi/hisilicon.c +6 -0

index 741faf3..10a605f 100644
@@ -14,6 +14,7 @@
 #include <linux/clk-provider.h>
 #include <linux/clocksource.h>
 #include <linux/irqchip.h>
+#include <linux/memblock.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
 

@@ -88,3 +89,21 @@ DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
      .smp            = smp_ops(hi3xxx_smp_ops),
      .restart        = hi3xxx_restart,
 MACHINE_END
+
+static const char *hip04_compat[] __initconst = {
+     "hisilicon,hip04-d01",
+     NULL,
+};

arch/arm/mach-hisi/hisilicon.c DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)") · line 101

Quoted 5 lines

arch/arm/mach-hisi/hisilicon.c +5 -0

+
+static void __init hip04_reserve(void)
+{
+     memblock_reserve(HIP04_BOOTWRAPPER_PHYS, HIP04_BOOTWRAPPER_SIZE);
+}

Can you explain why you do this? Shouldn't that memory just be listed in the DT?

arch/arm/mach-hisi/hisilicon.c DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)") · line 109

Quoted 8 lines

arch/arm/mach-hisi/hisilicon.c +7 -0

+DT_MACHINE_START(HIP04, "Hisilicon HiP04 (Flattened Device Tree)")
+     .dt_compat      = hip04_compat,
+#ifdef CONFIG_MCPM
+     .smp_init       = smp_init_ops(hip04_smp_init_ops),
+#endif
+     .reserve        = hip04_reserve,
+MACHINE_END

I think the #ifdef is not needed here, you already hide hip04_smp_init_ops if CONFIG_SMP is disabled, and SMP implies MCPM based on your Kconfig.

Quoted 4 lines

arch/arm/mach-hisi/platsmp.c +0 -0

index 471f1ee..3a5833f 100644

arch/arm/mach-hisi/platsmp.c struct smp_operations hi3xxx_smp_ops __initdata = { · line 98

Quoted 7 lines

};

arch/arm/mach-hisi/platsmp.c +5 -0

+
+#ifdef CONFIG_MCPM
+/* bits definition in SC_CPU_RESET_REQ[x]/SC_CPU_RESET_DREQ[x]
+ * 1 -- unreset; 0 -- reset
+ */
...

It would seem appropriate to put all of this into a separate source file -- there is no shared code between the two SMP implementations.

Quoted 6 lines

arch/arm/mach-hisi/platsmp.c +6 -0

+static int __init hip04_mcpm_init(void)
+{
+     struct device_node *np;
+     int ret = -ENODEV;
+
+     np = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-mcpm");

arch/arm/mach-hisi/platsmp.c struct smp_operations hi3xxx_smp_ops __initdata = { · line 307

Quoted 4 lines

arch/arm/mach-hisi/platsmp.c +4 -0

+     if (!np) {
+             pr_err("failed to find hisilicon,hip04-mcpm node\n");
+             goto err;
+     }

This shouldn't be a fatal error: if you run the kernel on a platform other than hip04, the code will still be executed here but it won't find the node and should just ignore the device silently.

arch/arm/mach-hisi/platsmp.c struct smp_operations hi3xxx_smp_ops __initdata = { · line 319

Quoted 12 lines

arch/arm/mach-hisi/platsmp.c +12 -0

+     relocation = of_iomap(np, 0);
+     if (!relocation) {
+             pr_err("failed to get relocation space\n");
+             ret = -ENOMEM;
+             goto err;
+     }
+     sysctrl = of_iomap(np, 1);
+     if (!sysctrl) {
+             pr_err("failed to get sysctrl base\n");
+             ret = -ENOMEM;
+             goto err_sysctrl;
+     }

sysctrl sounds like a shared device that you probably don't want to map here, but rather use a "syscon" node.

arch/arm/mach-hisi/platsmp.c

Quoted 2 lines

arch/arm/mach-hisi/platsmp.c +2 -0

+}
+early_initcall(hip04_mcpm_init);

Actually, I guess it would be better to do this from one of the various calls you already have for SMP initialization than doing an initcall.

Arnd

Quoted 22 lines · Arnd Bergmann

Quoted 21 lines · On Tuesday 08 April 2014 16:00:47 Haojian Zhuang wrote:

arch/arm/mach-hisi/hisilicon.c +6 -0

index 741faf3..10a605f 100644
@@ -14,6 +14,7 @@
 #include <linux/clk-provider.h>
 #include <linux/clocksource.h>
 #include <linux/irqchip.h>
+#include <linux/memblock.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
 

@@ -88,3 +89,21 @@ DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
      .smp            = smp_ops(hi3xxx_smp_ops),
      .restart        = hi3xxx_restart,
 MACHINE_END
+
+static const char *hip04_compat[] __initconst = {
+     "hisilicon,hip04-d01",
+     NULL,
+};

Quoted 8 lines

arch/arm/mach-hisi/hisilicon.c DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)") · line 101

Quoted 5 lines

arch/arm/mach-hisi/hisilicon.c +5 -0

+
+static void __init hip04_reserve(void)
+{
+     memblock_reserve(HIP04_BOOTWRAPPER_PHYS, HIP04_BOOTWRAPPER_SIZE);
+}

Can you explain why you do this? Shouldn't that memory just be listed in the DT?

In current implementation, boot code of secondary CPUs are stored in the memory of HIP04_BOOTWRAPPER_PHYS.

If the bootwrapper could be removed, we need to refresh the code on booting up secondary CPU.

Quoted 11 lines

arch/arm/mach-hisi/hisilicon.c DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)") · line 109

Quoted 7 lines

arch/arm/mach-hisi/hisilicon.c +7 -0

+DT_MACHINE_START(HIP04, "Hisilicon HiP04 (Flattened Device Tree)")
+     .dt_compat      = hip04_compat,
+#ifdef CONFIG_MCPM
+     .smp_init       = smp_init_ops(hip04_smp_init_ops),
+#endif
+     .reserve        = hip04_reserve,
+MACHINE_END

I think the #ifdef is not needed here, you already hide hip04_smp_init_ops if CONFIG_SMP is disabled, and SMP implies MCPM based on your Kconfig.

If I build only ARCH_HI3xxx without ARCH_HIP04, CONFIG_MCPM won't be selected. Then I'll meet the build error.

Hisilicon Hi3xxx is based on Cortex A9 Core. Now HiP04 SoC is based on Cortex A15 Core. Since multiple clusters is used in HiP04 SoC, it could be based on MCPM.

And HiP04 supports LPAE to support large memory.

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/Kconfig               |   2 +-
 arch/arm/mach-hisi/Kconfig     |   7 ++
 arch/arm/mach-hisi/core.h      |   6 +
 arch/arm/mach-hisi/hisilicon.c |  19 +++
 arch/arm/mach-hisi/platsmp.c   | 259 +++++++++++++++++++++++++++++++++++++++++
 5 files changed, 292 insertions(+), 1 deletion(-)

arch/arm/Kconfig +1 -1

index a8b2b45..6af6609 100644
@@ -1113,7 +1113,7 @@ source arch/arm/mm/Kconfig
 
 config ARM_NR_BANKS
        int
-       default 16 if ARCH_EP93XX
+       default 16 if ARCH_EP93XX || ARCH_HIP04
        default 8
 
 config IWMMXT

arch/arm/mach-hisi/Kconfig +0 -0

index da16efd..4dd966a 100644

arch/arm/mach-hisi/Kconfig +1 -0

+
 endmenu
 
 endif

arch/arm/mach-hisi/core.h +0 -0

index af23ec2..e008c7a 100644

+ : "cc");

arch/arm/mach-hisi/core.h +8 -0

+       relocation = of_iomap(np, 0);
+       if (!relocation) {
+               pr_err("failed to get relocation space\n");
+               ret = -ENOMEM;
+               goto err;
+       }
+       sysctrl = of_iomap(np, 1);
+       if (!sysctrl) {

arch/arm/mach-hisi/Kconfig config ARCH_HI3xxx · line 27

Quoted 11 lines · Haojian Zhuang

Hisilicon Hi3xxx is based on Cortex A9 Core. Now HiP04 SoC is based on Cortex A15 Core. Since multiple clusters is used in HiP04 SoC, it could be based on MCPM.

arch/arm/mach-hisi/Kconfig +6 -0

+config ARCH_HIP04
+       bool "Hisilicon HiP04 Cortex A15 family" if ARCH_MULTI_V7_LPAE
+       select HAVE_ARM_ARCH_TIMER
+       select MCPM if SMP
+       help
+         Support for Hisilicon HiP04 processor family

Nit: Surely this is an SoC family? The processor is Cortex-A15, as you state above.

Quoted 12 lines

arch/arm/mach-hisi/Kconfig +1 -0

+
 endmenu
 
 endif

arch/arm/mach-hisi/core.h +0 -0

index af23ec2..e008c7a 100644
@@ -12,4 +12,10 @@ extern void hi3xxx_cpu_die(unsigned int cpu);
 extern int hi3xxx_cpu_kill(unsigned int cpu);
 extern void hi3xxx_set_cpu(int cpu, bool enable);
 

arch/arm/mach-hisi/core.h extern void hi3xxx_cpu_die(unsigned int cpu); · line 17

Quoted 3 lines

arch/arm/mach-hisi/core.h +3 -0

+#define HIP04_BOOTWRAPPER_PHYS         0x10c00000
+#define HIP04_BOOTWRAPPER_MAGIC                0xa5a5a5a5
+#define HIP04_BOOTWRAPPER_SIZE         0x00010000

The address and size should come from DT.

What is the magic, exactly? How is it used by the kernel and bootwrapper?

arch/arm/mach-hisi/core.h extern void hi3xxx_cpu_die(unsigned int cpu); · line 21

Quoted 5 lines

arch/arm/mach-hisi/core.h +4 -0

+static void __init hip04_reserve(void)
+{
+       memblock_reserve(HIP04_BOOTWRAPPER_PHYS, HIP04_BOOTWRAPPER_SIZE);
+}

As Arnd said, do this in your DT. This is not a hardware property the kernel needs to statically know, but rather a system-specific property that needs to be in the DT such that it can vary.

Quoted 4 lines

arch/arm/mach-hisi/core.h +3 -0

+static int hip04_mcpm_power_up(unsigned int cpu, unsigned int cluster)
+{
+       unsigned long data, mask;

arch/arm/mach-hisi/core.h extern void hi3xxx_cpu_die(unsigned int cpu);

Quoted 10 lines

arch/arm/mach-hisi/core.h +10 -0

+
+       if (!relocation || !sysctrl)
+               return -ENODEV;
+       if (cluster >= HIP04_MAX_CLUSTERS || cpu >= HIP04_MAX_CPUS_PER_CLUSTER)
+               return -EINVAL;
+
+       spin_lock(&boot_lock);
+       writel_relaxed(HIP04_BOOTWRAPPER_PHYS, relocation);
+       writel_relaxed(HIP04_BOOTWRAPPER_MAGIC, relocation + 4);
+       writel_relaxed(virt_to_phys(mcpm_entry_point), relocation + 8);

So the kernel is poking the hardware directly to throw CPUs into a bootwrapper that it pokes to throw the CPUs into the kernel? That does not strike me as fantastic.

It's a shame we have to manage coherency here at all and don't have a PSCI implementation to abstract this. That would mean you wouldn't need a machine descriptor at all, could reuse existing infrastructure, and you'd be able to use Hyp.

arch/arm/mach-hisi/core.h

Quoted 8 lines

arch/arm/mach-hisi/core.h +7 -0

+static void hip04_mcpm_power_down(void)
+{
+       unsigned int mpidr, cpu, cluster;
+       unsigned int v;
+
+       spin_lock(&boot_lock);
+       spin_unlock(&boot_lock);

Huh? What's this for?

arch/arm/mach-hisi/core.h

Quoted 8 lines

arch/arm/mach-hisi/core.h +7 -0

+       asm volatile(
+       "       mrc     p15, 0, %0, c1, c0, 0\n"
+       "       bic     %0, %0, %1\n"
+       "       mcr     p15, 0, %0, c1, c0, 0\n"
+         : "=&r" (v)
+         : "Ir" (CR_C)
+         : "cc");

I don't think that cc clobber is necessary, none of these instructions set the flags.

arch/arm/mach-hisi/core.h

Quoted 10 lines

arch/arm/mach-hisi/core.h +9 -0

+       asm volatile(
+       /*
+       * Turn off coherency
+       */
+       "       mrc     p15, 0, %0, c1, c0, 1\n"
+       "       bic     %0, %0, %1\n"
+       "       mcr     p15, 0, %0, c1, c0, 1\n"
+       : "=&r" (v)
+       : "Ir" (0x40)

0x40?

Quoted 2 lines

+ : "cc");

Likewise I don't think this clobber is necessary.

arch/arm/mach-hisi/core.h

Quoted 11 lines

arch/arm/mach-hisi/core.h +10 -0

+static int __init hip04_mcpm_init(void)
+{
+       struct device_node *np;
+       int ret = -ENODEV;
+
+       np = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-mcpm");
+       if (!np) {
+               pr_err("failed to find hisilicon,hip04-mcpm node\n");
+               goto err;
+       }

MCPM is a Linux-specific software construct. It is not a piece of hardware, and not a generic interface name. Please come up with a better name for this that makes it clear exactly what you are describing.

Quoted 8 lines

arch/arm/mach-hisi/core.h +8 -0

+       relocation = of_iomap(np, 0);
+       if (!relocation) {
+               pr_err("failed to get relocation space\n");
+               ret = -ENOMEM;
+               goto err;
+       }
+       sysctrl = of_iomap(np, 1);
+       if (!sysctrl) {

arch/arm/mach-hisi/core.h

Quoted 10 lines

arch/arm/mach-hisi/core.h +10 -0

+               pr_err("failed to get sysctrl base\n");
+               ret = -ENOMEM;
+               goto err_sysctrl;
+       }
+       fabric = of_iomap(np, 2);
+       if (!fabric) {
+               pr_err("failed to get fabric base\n");
+               ret = -ENOMEM;
+               goto err_fabric;
+       }

These sounds like they would be better described by separate nodes.

Hisilicon Hi3xxx is based on Cortex A9 Core. Now HiP04 SoC is based on Cortex A15 Core. Since multiple clusters is used in HiP04 SoC, it could be based on MCPM.

And HiP04 supports LPAE to support large memory.

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/Kconfig               |   2 +-
 arch/arm/mach-hisi/Kconfig     |   7 ++
 arch/arm/mach-hisi/core.h      |   6 +
 arch/arm/mach-hisi/hisilicon.c |  19 +++
 arch/arm/mach-hisi/platsmp.c   | 259 +++++++++++++++++++++++++++++++++++++++++
 5 files changed, 292 insertions(+), 1 deletion(-)

arch/arm/Kconfig +1 -1

index a8b2b45..6af6609 100644
@@ -1113,7 +1113,7 @@ source arch/arm/mm/Kconfig
 
 config ARM_NR_BANKS
 	int
-	default 16 if ARCH_EP93XX
+	default 16 if ARCH_EP93XX || ARCH_HIP04
 	default 8
 
 config IWMMXT

arch/arm/mach-hisi/Kconfig +7 -0

index da16efd..4dd966a 100644
@@ -19,6 +19,13 @@ config ARCH_HI3xxx
 	help
 	  Support for Hisilicon Hi36xx/Hi37xx processor family
 
+config ARCH_HIP04
+	bool "Hisilicon HiP04 Cortex A15 family" if ARCH_MULTI_V7_LPAE
+	select HAVE_ARM_ARCH_TIMER
+	select MCPM if SMP
+	help
+	  Support for Hisilicon HiP04 processor family
+
 endmenu
 
 endif

arch/arm/mach-hisi/core.h +6 -0

index af23ec2..e008c7a 100644
@@ -12,4 +12,10 @@ extern void hi3xxx_cpu_die(unsigned int cpu);
 extern int hi3xxx_cpu_kill(unsigned int cpu);
 extern void hi3xxx_set_cpu(int cpu, bool enable);
 
+#define HIP04_BOOTWRAPPER_PHYS		0x10c00000
+#define HIP04_BOOTWRAPPER_MAGIC		0xa5a5a5a5
+#define HIP04_BOOTWRAPPER_SIZE		0x00010000
+
+extern bool __init hip04_smp_init_ops(void);
+
 #endif

arch/arm/mach-hisi/hisilicon.c +19 -0

index 741faf3..10a605f 100644
@@ -14,6 +14,7 @@
 #include <linux/clk-provider.h>
 #include <linux/clocksource.h>
 #include <linux/irqchip.h>
+#include <linux/memblock.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
 

@@ -88,3 +89,21 @@ DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
 	.smp		= smp_ops(hi3xxx_smp_ops),
 	.restart	= hi3xxx_restart,
 MACHINE_END
+
+static const char *hip04_compat[] __initconst = {
+	"hisilicon,hip04-d01",
+	NULL,
+};
+
+static void __init hip04_reserve(void)
+{
+	memblock_reserve(HIP04_BOOTWRAPPER_PHYS, HIP04_BOOTWRAPPER_SIZE);
+}
+
+DT_MACHINE_START(HIP04, "Hisilicon HiP04 (Flattened Device Tree)")
+	.dt_compat	= hip04_compat,
+#ifdef CONFIG_MCPM
+	.smp_init	= smp_init_ops(hip04_smp_init_ops),
+#endif
+	.reserve	= hip04_reserve,
+MACHINE_END

arch/arm/mach-hisi/platsmp.c +4 -0

index 471f1ee..3a5833f 100644
@@ -9,9 +9,13 @@
  */
 #include <linux/smp.h>
 #include <linux/io.h>
+#include <linux/irqchip/arm-gic.h>
 #include <linux/of_address.h>
 
 #include <asm/cacheflush.h>
+#include <asm/cp15.h>
+#include <asm/cputype.h>
+#include <asm/mcpm.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 

arch/arm/mach-hisi/platsmp.c +253 -0

+/* bits definition in SC_CPU_RESET_REQ[x]/SC_CPU_RESET_DREQ[x]
+ * 1 -- unreset; 0 -- reset
+ */
+#define CORE_RESET_BIT(x)		(1 << x)
+#define NEON_RESET_BIT(x)		(1 << (x + 4))
+#define CORE_DEBUG_RESET_BIT(x)		(1 << (x + 9))
+#define CLUSTER_L2_RESET_BIT		(1 << 8)
+#define CLUSTER_DEBUG_RESET_BIT		(1 << 13)
+
+/*
+ * bits definition in SC_CPU_RESET_STATUS[x]
+ * 1 -- reset status; 0 -- unreset status
+ */
+#define CORE_RESET_STATUS(x)		(1 << x)
+#define NEON_RESET_STATUS(x)		(1 << (x + 4))
+#define CORE_DEBUG_RESET_STATUS(x)	(1 << (x + 9))
+#define CLUSTER_L2_RESET_STATUS		(1 << 8)
+#define CLUSTER_DEBUG_RESET_STATUS	(1 << 13)
+#define CORE_WFI_STATUS(x)		(1 << (x + 16))
+#define CORE_WFE_STATUS(x)		(1 << (x + 20))
+#define CORE_DEBUG_ACK(x)		(1 << (x + 24))
+
+#define SC_CPU_RESET_REQ(x)		(0x520 + (x << 3))	/* reset */
+#define SC_CPU_RESET_DREQ(x)		(0x524 + (x << 3))	/* unreset */
+#define SC_CPU_RESET_STATUS(x)		(0x1520 + (x << 3))
+
+#define FAB_SF_MODE			0x0c
+#define FAB_SF_INVLD			0x10
+
+/* bits definition in FB_SF_INVLD */
+#define FB_SF_INVLD_START		(1 << 8)
+
+#define HIP04_MAX_CLUSTERS		4
+#define HIP04_MAX_CPUS_PER_CLUSTER	4
+
+static void __iomem *relocation, *sysctrl, *fabric;
+static int hip04_cpu_table[HIP04_MAX_CLUSTERS][HIP04_MAX_CPUS_PER_CLUSTER];
+static DEFINE_SPINLOCK(boot_lock);
+
+static bool hip04_cluster_down(unsigned int cluster)
+{
+	int i;
+
+	for (i = 0; i < HIP04_MAX_CPUS_PER_CLUSTER; i++)
+		if (hip04_cpu_table[cluster][i])
+			return false;
+	return true;
+}
+
+static void hip04_set_snoop_filter(unsigned int cluster, unsigned int on)
+{
+	unsigned long data;
+
+	if (!fabric)
+		return;
+	data = readl_relaxed(fabric + FAB_SF_MODE);
+	if (on)
+		data |= 1 << cluster;
+	else
+		data &= ~(1 << cluster);
+	writel_relaxed(data, fabric + FAB_SF_MODE);
+	while (1) {
+		if (data == readl_relaxed(fabric + FAB_SF_MODE))
+			break;
+	}
+}
+
+static int hip04_mcpm_power_up(unsigned int cpu, unsigned int cluster)
+{
+	unsigned long data, mask;
+
+	if (!relocation || !sysctrl)
+		return -ENODEV;
+	if (cluster >= HIP04_MAX_CLUSTERS || cpu >= HIP04_MAX_CPUS_PER_CLUSTER)
+		return -EINVAL;
+
+	spin_lock(&boot_lock);
+	writel_relaxed(HIP04_BOOTWRAPPER_PHYS, relocation);
+	writel_relaxed(HIP04_BOOTWRAPPER_MAGIC, relocation + 4);
+	writel_relaxed(virt_to_phys(mcpm_entry_point), relocation + 8);
+	writel_relaxed(0, relocation + 12);
+
+	if (hip04_cluster_down(cluster)) {
+		data = CLUSTER_L2_RESET_BIT | CLUSTER_DEBUG_RESET_BIT;
+		writel_relaxed(data, sysctrl + SC_CPU_RESET_DREQ(cluster));
+		do {
+			mask = CLUSTER_L2_RESET_STATUS | \
+			       CLUSTER_DEBUG_RESET_STATUS;
+			data = readl_relaxed(sysctrl + \
+					     SC_CPU_RESET_STATUS(cluster));
+		} while (data & mask);
+		hip04_set_snoop_filter(cluster, 1);
+	}
+
+	hip04_cpu_table[cluster][cpu]++;
+
+	data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \
+	       CORE_DEBUG_RESET_BIT(cpu);
+	writel_relaxed(data, sysctrl + SC_CPU_RESET_DREQ(cluster));
+	spin_unlock(&boot_lock);
+
+	return 0;
+}
+
+static void hip04_mcpm_power_down(void)
+{
+	unsigned int mpidr, cpu, cluster;
+	unsigned int v;
+
+	spin_lock(&boot_lock);
+	spin_unlock(&boot_lock);
+
+	mpidr = read_cpuid_mpidr();
+	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+	local_irq_disable();
+	gic_cpu_if_down();
+
+	__mcpm_cpu_down(cpu, cluster);
+
+	asm volatile(
+	"	mrc	p15, 0, %0, c1, c0, 0\n"
+	"	bic	%0, %0, %1\n"
+	"	mcr	p15, 0, %0, c1, c0, 0\n"
+	  : "=&r" (v)
+	  : "Ir" (CR_C)
+	  : "cc");
+
+	flush_cache_louis();
+
+	asm volatile(
+	/*
+	* Turn off coherency
+	*/
+	"	mrc	p15, 0, %0, c1, c0, 1\n"
+	"	bic	%0, %0, %1\n"
+	"	mcr	p15, 0, %0, c1, c0, 1\n"
+	: "=&r" (v)
+	: "Ir" (0x40)
+	: "cc");
+
+	isb();
+	dsb();
+}
+
+static int hip04_mcpm_power_down_finish(unsigned int cpu, unsigned int cluster)
+{
+	int ret = -EBUSY;
+
+	spin_lock(&boot_lock);
+	BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+	__mcpm_cpu_going_down(cpu, cluster);
+
+	hip04_cpu_table[cluster][cpu]--;
+	if (hip04_cpu_table[cluster][cpu]) {
+		pr_err("Cluster %d CPU%d is still running\n", cluster, cpu);
+		goto out;
+	}
+	ret = 0;
+out:
+	spin_unlock(&boot_lock);
+	return ret;
+}
+
+static void hip04_mcpm_powered_up(void)
+{
+	if (!relocation)
+		return;
+	spin_lock(&boot_lock);
+	writel_relaxed(0, relocation);
+	writel_relaxed(0, relocation + 4);
+	writel_relaxed(0, relocation + 8);
+	writel_relaxed(0, relocation + 12);
+	spin_unlock(&boot_lock);
+}
+
+static const struct mcpm_platform_ops hip04_mcpm_ops = {
+	.power_up		= hip04_mcpm_power_up,
+	.power_down		= hip04_mcpm_power_down,
+	.power_down_finish	= hip04_mcpm_power_down_finish,
+	.powered_up		= hip04_mcpm_powered_up,
+};
+
+static bool __init hip04_cpu_table_init(void)
+{
+	unsigned int mpidr, cpu, cluster;
+
+	mpidr = read_cpuid_mpidr();
+	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+	if (cluster >= HIP04_MAX_CLUSTERS ||
+	    cpu >= HIP04_MAX_CPUS_PER_CLUSTER) {
+		pr_err("%s: boot CPU is out of bound!\n", __func__);
+		return false;
+	}
+	hip04_set_snoop_filter(cluster, 1);
+	hip04_cpu_table[cluster][cpu] = 1;
+	return true;
+}
+
+static int __init hip04_mcpm_init(void)
+{
+	struct device_node *np;
+	int ret = -ENODEV;
+
+	np = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-mcpm");
+	if (!np) {
+		pr_err("failed to find hisilicon,hip04-mcpm node\n");
+		goto err;
+	}
+	relocation = of_iomap(np, 0);
+	if (!relocation) {
+		pr_err("failed to get relocation space\n");
+		ret = -ENOMEM;
+		goto err;
+	}
+	sysctrl = of_iomap(np, 1);
+	if (!sysctrl) {
+		pr_err("failed to get sysctrl base\n");
+		ret = -ENOMEM;
+		goto err_sysctrl;
+	}
+	fabric = of_iomap(np, 2);
+	if (!fabric) {
+		pr_err("failed to get fabric base\n");
+		ret = -ENOMEM;
+		goto err_fabric;
+	}
+	if (!hip04_cpu_table_init())
+		return -EINVAL;
+	ret = mcpm_platform_register(&hip04_mcpm_ops);
+	if (!ret) {
+		mcpm_sync_init(NULL);
+		pr_info("HiP04 MCPM initialized\n");
+	}
+	return ret;
+err_fabric:
+	iounmap(sysctrl);
+err_sysctrl:
+	iounmap(relocation);
+err:
+	return ret;
+}
+early_initcall(hip04_mcpm_init);
+
+bool __init hip04_smp_init_ops(void)
+{
+	mcpm_smp_set_ops();
+	return true;
+}
+#endif	/* CONFIG_MCPM */

Signature · 7 lines

1.8.3.2


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linux-arm-kernel at lists.infradead.org
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Add hip04.dtsi & hip04-d01.dts file to support HiP04 SoC platform.

Signed-off-by Haojian Zhuang <[email protected]>

---
 Documentation/devicetree/bindings/arm/gic.txt      |   1 +
 .../bindings/arm/hisilicon/hisilicon.txt           |  12 ++
 .../devicetree/bindings/clock/hip04-clock.txt      |  20 ++
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/hip04-d01.dts                    |  74 +++++++
 arch/arm/boot/dts/hip04.dtsi                       | 240 +++++++++++++++++++++
 6 files changed, 348 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/hip04-clock.txt
 create mode 100644 arch/arm/boot/dts/hip04-d01.dts
 create mode 100644 arch/arm/boot/dts/hip04.dtsi

Documentation/devicetree/bindings/arm/gic.txt +1 -0

index 5573c08..150f7d6 100644
@@ -16,6 +16,7 @@ Main node required properties:
        "arm,cortex-a9-gic"
        "arm,cortex-a7-gic"
        "arm,arm11mp-gic"
+       "hisilicon,hip04-gic"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
   interrupt source.  The type shall be a <u32> and the value shall be 3.

Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +4 -0

index df0a452..47c0a13 100644
@@ -4,6 +4,10 @@ Hisilicon Platforms Device Tree Bindings
 Hi4511 Board
 Required root node properties:
        - compatible = "hisilicon,hi3620-hi4511";
+HiP04 D01 Board
+Required root node properties:
+       - compatible = "hisilicon,hip04-d01";
+
 
 Hisilicon system controller
 

Documentation/devicetree/bindings/clock/hip04-clock.txt new file +8 -0

new file mode 100644
index 0000000..4d31ae3
@@ -0,0 +1,20 @@
+* Hisilicon HiP04 Clock Controller
+
+The HiP04 clock controller generates and supplies clock to various
+controllers within the HiP04 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.

arch/arm/boot/dts/hip04-d01.dts new file +10 -0

new file mode 100644
index 0000000..a10dcf3
@@ -0,0 +1,74 @@
+/*
+ *  Copyright (C) 2013-2014 Linaro Ltd.
+ *  Author: Haojian Zhuang <[email protected]>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;

arch/arm/boot/dts/hip04-d01.dts new file +23 -0

+               device_type = "memory";
+               reg = <0x00000004 0xc0000000 0x40000000>;
+       };
+
+       memory at 0000000500000000 {
+               device_type = "memory";
+               reg = <0x00000005 0x00000000 0x80000000>;
+       };
+
+       memory at 0000000580000000 {
+               device_type = "memory";
+               reg = <0x00000005 0x80000000 0x80000000>;
+       };
+
+       memory at 0000000600000000 {
+               device_type = "memory";
+               reg = <0x00000006 0x00000000 0x80000000>;
+       };
+
+       memory at 0000000680000000 {
+               device_type = "memory";
+               reg = <0x00000006 0x80000000 0x80000000>;
+       };

arch/arm/boot/dts/hip04-d01.dts new file +7 -0

+
+       soc {
+               uart0: uart at 4007000 {
+                       status = "ok";
+               };
+       };
+};

arch/arm/boot/dts/hip04.dtsi new file +19 -0

new file mode 100644
index 0000000..eb5e5a2
@@ -0,0 +1,240 @@
+/*
+ * Hisilicon Ltd. HiP01 SoC
+ *
+ * Copyright (C) 2013-2014 Hisilicon Ltd.
+ * Copyright (C) 2013-2014 Linaro Ltd.
+ *
+ * Author: Haojian Zhuang <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/hip04-clock.h>
+
+/ {
+       /* memory bus is 64-bit */
+       #address-cells = <2>;
+       #size-cells = <1>;

+ device_type = "soc";

Add hip04.dtsi & hip04-d01.dts file to support HiP04 SoC platform.

Signed-off-by Haojian Zhuang <[email protected]>

Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +0 -0

index df0a452..47c0a13 100644

Select HiP04 SoC configuration by hip04_defconfig.

Signed-off-by Haojian Zhuang <[email protected]>

---
 arch/arm/configs/hip04_defconfig | 67 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 67 insertions(+)
 create mode 100644 arch/arm/configs/hip04_defconfig