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Exynos5: Add GPIO numbering feature

PATCH New Akshay Saraswat 5 participants 19 messages Apr 12, 2014 – Apr 17, 2014

Subsystems (3)
Arm (32-bit) GPIO Arm Samsung Exynos
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Akshay Saraswat

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#0 lore raw

v6 cover Exynos5: Add GPIO numbering feature

From: Akshay Saraswat <[email protected]>

Changes in V2:
- Enabled CMD_GPIO as suggested by Simon Glass
and supported same for EXYNOS5.
Changes in V3:
- New patch added to rename S5P GPIO definitions to S5P_GPIO.
- GPIO Table added to calculate the base address of input gpio bank.
Changes in V4:
- To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.
- Function and table to support gpio command moved to s5p-gpio driver.
- Rebased on latest u-boot-samsung tree.
Changes in V5:
- Rebased on latest u-boot-samsung tree.
- Removed Exynos5 specific code in gpio driver api to get bank.
- Added #define HAVE_GENERIC_GPIO in config file to remove conditinal CPU check in gpio driver.
Changes in V6:
- Isolated config changes in a new patch.
- Updated patches with corresponding changes for Exynos 5420.

Rajeshwari Shinde (4):
S5P: Rename GPIO definitions
EXYNOS5: Add gpio pin numbering feature
EXYNOS5: GPIO: Support GPIO Command for EXYNOS5
Config: Exynos5: Enable Generic GPIO and CMD configs

 arch/arm/cpu/armv7/exynos/pinmux.c       | 355 ++++++--------
 arch/arm/include/asm/arch-exynos/cpu.h   |  17 +-
 arch/arm/include/asm/arch-exynos/gpio.h  | 796 ++++++++++++++++++++++++++++++-
 arch/arm/include/asm/arch-s5pc1xx/gpio.h |  26 +-
 board/samsung/goni/goni.c                |   4 +-
 board/samsung/smdk5250/exynos5-dt.c      |  20 +-
 board/samsung/smdk5250/smdk5250.c        |  19 +-
 board/samsung/smdk5420/smdk5420.c        |  15 +-
 board/samsung/smdkc100/smdkc100.c        |   2 +-
 board/samsung/smdkv310/smdkv310.c        |  10 +-
 board/samsung/trats/trats.c              |   6 +-
 board/samsung/universal_c210/universal.c |  34 +-
 drivers/gpio/s5p_gpio.c                  | 169 ++++++-
 include/configs/exynos5-dt.h             |   3 +
 14 files changed, 1157 insertions(+), 319 deletions(-)
Signature · 1 line
1.8.3.2
author
#1 lore raw

PATCH v6 1/4 EXYNOS5: Add gpio pin numbering feature

From: Rajeshwari Shinde <[email protected]>

This patch adds gpio pin numbering support for EXYNOS 5250 & 5420. To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.

Signed-off-by Leela Krishna Amudala <[email protected]>
Signed-off-by Rajeshwari Shinde <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>
---
 arch/arm/cpu/armv7/exynos/pinmux.c      | 287 +++++-------
 arch/arm/include/asm/arch-exynos/cpu.h  |  17 +-
 arch/arm/include/asm/arch-exynos/gpio.h | 742 +++++++++++++++++++++++++++++++-
 board/samsung/smdk5250/exynos5-dt.c     |  20 +-
 board/samsung/smdk5250/smdk5250.c       |  19 +-
 board/samsung/smdk5420/smdk5420.c       |  15 +-
 drivers/gpio/s5p_gpio.c                 |  44 +-
 7 files changed, 923 insertions(+), 221 deletions(-)
arch/arm/cpu/armv7/exynos/pinmux.c +118 -169
index 9edb475..34c24cd 100644
@@ -13,30 +13,23 @@
 
 static void exynos5_uart_config(int peripheral)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-	struct s5p_gpio_bank *bank;
 	int i, start, count;
 
 	switch (peripheral) {
 	case PERIPH_ID_UART0:
-		bank = &gpio1->a0;
-		start = 0;
+		start = EXYNOS5_GPIO_A00;
 		count = 4;
 		break;
 	case PERIPH_ID_UART1:
-		bank = &gpio1->d0;
-		start = 0;
+		start = EXYNOS5_GPIO_D00;
 		count = 4;
 		break;
 	case PERIPH_ID_UART2:
-		bank = &gpio1->a1;
-		start = 0;
+		start = EXYNOS5_GPIO_A10;
 		count = 4;
 		break;
 	case PERIPH_ID_UART3:
-		bank = &gpio1->a1;
-		start = 4;
+		start = EXYNOS5_GPIO_A14;
 		count = 2;
 		break;
 	default:

@@ -44,37 +37,30 @@ static void exynos5_uart_config(int peripheral)
 		return;
 	}
 	for (i = start; i < start + count; i++) {
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+		gpio_set_pull(i, GPIO_PULL_NONE);
+		gpio_cfg_pin(i, GPIO_FUNC(0x2));
 	}
 }
 
 static void exynos5420_uart_config(int peripheral)
 {
-	struct exynos5420_gpio_part1 *gpio1 =
-		(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
-	struct s5p_gpio_bank *bank;
 	int i, start, count;
 
 	switch (peripheral) {
 	case PERIPH_ID_UART0:
-		bank = &gpio1->a0;
-		start = 0;
+		start = EXYNOS5420_GPIO_A00;
 		count = 4;
 		break;
 	case PERIPH_ID_UART1:
-		bank = &gpio1->a0;
-		start = 4;
+		start = EXYNOS5420_GPIO_A04;
 		count = 4;
 		break;
 	case PERIPH_ID_UART2:
-		bank = &gpio1->a1;
-		start = 0;
+		start = EXYNOS5420_GPIO_A10;
 		count = 4;
 		break;
 	case PERIPH_ID_UART3:
-		bank = &gpio1->a1;
-		start = 4;
+		start = EXYNOS5420_GPIO_A14;
 		count = 2;
 		break;
 	default:

@@ -83,64 +69,59 @@ static void exynos5420_uart_config(int peripheral)
 	}
 
 	for (i = start; i < start + count; i++) {
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+		gpio_set_pull(i, GPIO_PULL_NONE);
+		gpio_cfg_pin(i, GPIO_FUNC(0x2));
 	}
 }
 
 static int exynos5_mmc_config(int peripheral, int flags)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-	struct s5p_gpio_bank *bank, *bank_ext;
-	int i, start = 0, gpio_func = 0;
+	int i, start, start_ext, gpio_func = 0;
 
 	switch (peripheral) {
 	case PERIPH_ID_SDMMC0:
-		bank = &gpio1->c0;
-		bank_ext = &gpio1->c1;
-		start = 0;
+		start = EXYNOS5_GPIO_C00;
+		start_ext = EXYNOS5_GPIO_C10;
 		gpio_func = GPIO_FUNC(0x2);
 		break;
 	case PERIPH_ID_SDMMC1:
-		bank = &gpio1->c2;
-		bank_ext = NULL;
+		start = EXYNOS5_GPIO_C20;
+		start_ext = 0;
 		break;
 	case PERIPH_ID_SDMMC2:
-		bank = &gpio1->c3;
-		bank_ext = &gpio1->c4;
-		start = 3;
+		start = EXYNOS5_GPIO_C30;
+		start_ext = EXYNOS5_GPIO_C43;
 		gpio_func = GPIO_FUNC(0x3);
 		break;
 	case PERIPH_ID_SDMMC3:
-		bank = &gpio1->c4;
-		bank_ext = NULL;
+		start = EXYNOS5_GPIO_C40;
+		start_ext = 0;
 		break;
 	default:
 		debug("%s: invalid peripheral %d", __func__, peripheral);
 		return -1;
 	}
-	if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+	if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
 		debug("SDMMC device %d does not support 8bit mode",
 				peripheral);
 		return -1;
 	}
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
-		for (i = start; i <= (start + 3); i++) {
-			s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
-			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
-			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+		for (i = start_ext; i <= (start_ext + 3); i++) {
+			gpio_cfg_pin(i, gpio_func);
+			gpio_set_pull(i, GPIO_PULL_UP);
+			gpio_set_drv(i, GPIO_DRV_4X);
 		}
 	}
 	for (i = 0; i < 2; i++) {
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+		gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
+		gpio_set_pull(start + i, GPIO_PULL_NONE);
+		gpio_set_drv(start + i, GPIO_DRV_4X);
 	}
 	for (i = 3; i <= 6; i++) {
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+		gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
+		gpio_set_pull(start + i, GPIO_PULL_UP);
+		gpio_set_drv(start + i, GPIO_DRV_4X);
 	}
 
 	return 0;

@@ -148,25 +129,22 @@ static int exynos5_mmc_config(int peripheral, int flags)
 
 static int exynos5420_mmc_config(int peripheral, int flags)
 {
-	struct exynos5420_gpio_part3 *gpio3 =
-		(struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3();
-	struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL;
-	int i, start;
+	int i, start = 0, start_ext = 0;
 
 	switch (peripheral) {
 	case PERIPH_ID_SDMMC0:
-		bank = &gpio3->c0;
-		bank_ext = &gpio3->c3;
+		start = EXYNOS5420_GPIO_C00;
+		start_ext = EXYNOS5420_GPIO_C30;
 		start = 0;
 		break;
 	case PERIPH_ID_SDMMC1:
-		bank = &gpio3->c1;
-		bank_ext = &gpio3->d1;
+		start = EXYNOS5420_GPIO_C10;
+		start_ext = EXYNOS5420_GPIO_D14;
 		start = 4;
 		break;
 	case PERIPH_ID_SDMMC2:
-		bank = &gpio3->c2;
-		bank_ext = NULL;
+		start = EXYNOS5420_GPIO_C20;
+		start_ext = 0;
 		start = 0;
 		break;
 	default:

@@ -175,7 +153,7 @@ static int exynos5420_mmc_config(int peripheral, int flags)
 		return -1;
 	}
 
-	if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+	if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
 		debug("SDMMC device %d does not support 8bit mode",
 		      peripheral);
 		return -1;

@@ -183,9 +161,9 @@ static int exynos5420_mmc_config(int peripheral, int flags)
 
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
 		for (i = start; i <= (start + 3); i++) {
-			s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x2));
-			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
-			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+			gpio_cfg_pin(i, GPIO_FUNC(0x2));
+			gpio_set_pull(i, GPIO_PULL_UP);
+			gpio_set_drv(i, GPIO_DRV_4X);
 		}
 	}
 

@@ -197,19 +175,19 @@ static int exynos5420_mmc_config(int peripheral, int flags)
 		 * this same assumption.
 		 */
 		if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) {
-			s5p_gpio_set_value(bank, i, 1);
-			s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT);
+			gpio_set_value(i, 1);
+			gpio_cfg_pin(i, GPIO_OUTPUT);
 		} else {
-			s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+			gpio_cfg_pin(i, GPIO_FUNC(0x2));
 		}
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+		gpio_set_pull(i, GPIO_PULL_NONE);
+		gpio_set_drv(i, GPIO_DRV_4X);
 	}
 
 	for (i = 3; i <= 6; i++) {
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+		gpio_cfg_pin(i, GPIO_FUNC(0x2));
+		gpio_set_pull(i, GPIO_PULL_UP);
+		gpio_set_drv(i, GPIO_DRV_4X);
 	}
 
 	return 0;

@@ -217,8 +195,6 @@ static int exynos5420_mmc_config(int peripheral, int flags)
 
 static void exynos5_sromc_config(int flags)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 	int i;
 
 	/*

@@ -236,13 +212,13 @@ static void exynos5_sromc_config(int flags)
 	 * GPY1[2]	SROM_WAIT(2)
 	 * GPY1[3]	EBI_DATA_RDn(2)
 	 */
-	s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK),
-				GPIO_FUNC(2));
-	s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
-	s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
+	gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK),
+		     GPIO_FUNC(2));
+	gpio_cfg_pin(EXYNOS5_GPIO_Y04, GPIO_FUNC(2));
+	gpio_cfg_pin(EXYNOS5_GPIO_Y05, GPIO_FUNC(2));
 
 	for (i = 0; i < 4; i++)
-		s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
+		gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, GPIO_FUNC(2));
 
 	/*
 	 * EBI: 8 Addrss Lines

@@ -277,108 +253,101 @@ static void exynos5_sromc_config(int flags)
 	 * GPY6[7]	EBI_DATA[15](2)
 	 */
 	for (i = 0; i < 8; i++) {
-		s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
-		s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y30 + i, GPIO_PULL_UP);
 
-		s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
-		s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y50 + i, GPIO_PULL_UP);
 
-		s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
-		s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y60 + i, GPIO_PULL_UP);
 	}
 }
 
 static void exynos5_i2c_config(int peripheral, int flags)
 {
-
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-
 	switch (peripheral) {
 	case PERIPH_ID_I2C0:
-		s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B30, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B31, GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C1:
-		s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B32, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B33, GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C2:
-		s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A06, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A07, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C3:
-		s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A12, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A13, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C4:
-		s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A20, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A21, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C5:
-		s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A22, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A23, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C6:
-		s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
-		s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5_GPIO_B13, GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5_GPIO_B14, GPIO_FUNC(0x4));
 		break;
 	case PERIPH_ID_I2C7:
-		s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_B22, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_B23, GPIO_FUNC(0x3));
 		break;
 	}
 }
 
 static void exynos5420_i2c_config(int peripheral)
 {
-	struct exynos5420_gpio_part1 *gpio1 =
-		(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
-
 	switch (peripheral) {
 	case PERIPH_ID_I2C0:
-		s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B30, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B31, GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C1:
-		s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B32, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B33, GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C2:
-		s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A06, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A07, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C3:
-		s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A12, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A13, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C4:
-		s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A20, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A21, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C5:
-		s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A22, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A23, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C6:
-		s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
-		s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B13, GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B14, GPIO_FUNC(0x4));
 		break;
 	case PERIPH_ID_I2C7:
-		s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B22, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B23, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C8:
-		s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B34, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B35, GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C9:
-		s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B36, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B37, GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C10:
-		s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B40, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B41, GPIO_FUNC(0x2));
 		break;
 	}
 }

@@ -386,19 +355,15 @@ static void exynos5420_i2c_config(int peripheral)
 static void exynos5_i2s_config(int peripheral)
 {
 	int i;
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
-	struct exynos5_gpio_part4 *gpio4 =
-		(struct exynos5_gpio_part4 *)samsung_get_base_gpio_part4();
 
 	switch (peripheral) {
 	case PERIPH_ID_I2S0:
 		for (i = 0; i < 5; i++)
-			s5p_gpio_cfg_pin(&gpio4->z, i, GPIO_FUNC(0x02));
+			gpio_cfg_pin(EXYNOS5_GPIO_Z0+i, GPIO_FUNC(0x02));
 		break;
 	case PERIPH_ID_I2S1:
 		for (i = 0; i < 5; i++)
-			s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
+			gpio_cfg_pin(EXYNOS5_GPIO_B00+i, GPIO_FUNC(0x02));
 		break;
 	}
 }

@@ -406,75 +371,57 @@ static void exynos5_i2s_config(int peripheral)
 void exynos5_spi_config(int peripheral)
 {
 	int cfg = 0, pin = 0, i;
-	struct s5p_gpio_bank *bank = NULL;
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-	struct exynos5_gpio_part2 *gpio2 =
-		(struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
 
 	switch (peripheral) {
 	case PERIPH_ID_SPI0:
-		bank = &gpio1->a2;
 		cfg = GPIO_FUNC(0x2);
-		pin = 0;
+		pin = EXYNOS5_GPIO_A20;
 		break;
 	case PERIPH_ID_SPI1:
-		bank = &gpio1->a2;
 		cfg = GPIO_FUNC(0x2);
-		pin = 4;
+		pin = EXYNOS5_GPIO_A24;
 		break;
 	case PERIPH_ID_SPI2:
-		bank = &gpio1->b1;
 		cfg = GPIO_FUNC(0x5);
-		pin = 1;
+		pin = EXYNOS5_GPIO_B11;
 		break;
 	case PERIPH_ID_SPI3:
-		bank = &gpio2->f1;
 		cfg = GPIO_FUNC(0x2);
-		pin = 0;
+		pin = EXYNOS5_GPIO_F10;
 		break;
 	case PERIPH_ID_SPI4:
 		for (i = 0; i < 2; i++) {
-			s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
-			s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
+			gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, GPIO_FUNC(0x4));
+			gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, GPIO_FUNC(0x4));
 		}
 		break;
 	}
 	if (peripheral != PERIPH_ID_SPI4) {
 		for (i = pin; i < pin + 4; i++)
-			s5p_gpio_cfg_pin(bank, i, cfg);
+			gpio_cfg_pin(i, cfg);
 	}
 }
 
 void exynos5420_spi_config(int peripheral)
 {
 	int cfg, pin, i;
-	struct s5p_gpio_bank *bank = NULL;
-	struct exynos5420_gpio_part1 *gpio1 =
-		(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
-	struct exynos5420_gpio_part4 *gpio4 =
-		(struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4();
 
 	switch (peripheral) {
 	case PERIPH_ID_SPI0:
-		bank = &gpio1->a2;
+		pin = EXYNOS5420_GPIO_A20;
 		cfg = GPIO_FUNC(0x2);
-		pin = 0;
 		break;
 	case PERIPH_ID_SPI1:
-		bank = &gpio1->a2;
+		pin = EXYNOS5420_GPIO_A24;
 		cfg = GPIO_FUNC(0x2);
-		pin = 4;
 		break;
 	case PERIPH_ID_SPI2:
-		bank = &gpio1->b1;
+		pin = EXYNOS5420_GPIO_B11;
 		cfg = GPIO_FUNC(0x5);
-		pin = 1;
 		break;
 	case PERIPH_ID_SPI3:
-		bank = &gpio4->f1;
+		pin = EXYNOS5420_GPIO_F10;
 		cfg = GPIO_FUNC(0x2);
-		pin = 0;
 		break;
 	case PERIPH_ID_SPI4:
 		cfg = 0;

@@ -489,11 +436,13 @@ void exynos5420_spi_config(int peripheral)
 
 	if (peripheral != PERIPH_ID_SPI4) {
 		for (i = pin; i < pin + 4; i++)
-			s5p_gpio_cfg_pin(bank, i, cfg);
+			gpio_cfg_pin(i, cfg);
 	} else {
 		for (i = 0; i < 2; i++) {
-			s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4));
-			s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4));
+			gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i,
+				     GPIO_FUNC(0x4));
+			gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i,
+				     GPIO_FUNC(0x4));
 		}
 	}
 }
arch/arm/include/asm/arch-exynos/cpu.h +11 -6
index fdf73b5..ba71714 100644
@@ -98,7 +98,7 @@
 #define EXYNOS5_I2C_SPACING		0x10000
 
 #define EXYNOS5_AUDIOSS_BASE		0x03810000
-#define EXYNOS5_GPIO_PART4_BASE		0x03860000
+#define EXYNOS5_GPIO_PART8_BASE		0x03860000
 #define EXYNOS5_PRO_ID			0x10000000
 #define EXYNOS5_CLOCK_BASE		0x10010000
 #define EXYNOS5_POWER_BASE		0x10040000

@@ -108,9 +108,13 @@
 #define EXYNOS5_WATCHDOG_BASE		0x101D0000
 #define EXYNOS5_ACE_SFR_BASE		0x10830000
 #define EXYNOS5_DMC_PHY_BASE		0x10C00000
-#define EXYNOS5_GPIO_PART3_BASE		0x10D10000
+#define EXYNOS5_GPIO_PART5_BASE		0x10D10000
+#define EXYNOS5_GPIO_PART6_BASE		0x10D10060
+#define EXYNOS5_GPIO_PART7_BASE		0x10D100C0
 #define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
 #define EXYNOS5_GPIO_PART1_BASE		0x11400000
+#define EXYNOS5_GPIO_PART2_BASE		0x114002E0
+#define EXYNOS5_GPIO_PART3_BASE		0x11400C00
 #define EXYNOS5_MIPI_DSIM_BASE		0x11D00000
 #define EXYNOS5_USB_HOST_XHCI_BASE	0x12000000
 #define EXYNOS5_USB3PHY_BASE		0x12100000

@@ -125,7 +129,7 @@
 #define EXYNOS5_I2S_BASE		0x12D60000
 #define EXYNOS5_PWMTIMER_BASE		0x12DD0000
 #define EXYNOS5_SPI_ISP_BASE		0x131A0000
-#define EXYNOS5_GPIO_PART2_BASE		0x13400000
+#define EXYNOS5_GPIO_PART4_BASE		0x13400000
 #define EXYNOS5_FIMD_BASE		0x14400000
 #define EXYNOS5_DP_BASE			0x145B0000
 

@@ -135,7 +139,7 @@
 
 /* EXYNOS5420 */
 #define EXYNOS5420_AUDIOSS_BASE		0x03810000
-#define EXYNOS5420_GPIO_PART5_BASE	0x03860000
+#define EXYNOS5420_GPIO_PART6_BASE	0x03860000
 #define EXYNOS5420_PRO_ID		0x10000000
 #define EXYNOS5420_CLOCK_BASE		0x10010000
 #define EXYNOS5420_POWER_BASE		0x10040000

@@ -158,8 +162,9 @@
 #define EXYNOS5420_PWMTIMER_BASE	0x12DD0000
 #define EXYNOS5420_SPI_ISP_BASE		0x131A0000
 #define EXYNOS5420_GPIO_PART2_BASE	0x13400000
-#define EXYNOS5420_GPIO_PART3_BASE	0x13410000
-#define EXYNOS5420_GPIO_PART4_BASE	0x14000000
+#define EXYNOS5420_GPIO_PART3_BASE	0x13400C00
+#define EXYNOS5420_GPIO_PART4_BASE	0x13410000
+#define EXYNOS5420_GPIO_PART5_BASE	0x14000000
 #define EXYNOS5420_GPIO_PART1_BASE	0x14010000
 #define EXYNOS5420_MIPI_DSIM_BASE	0x14500000
 #define EXYNOS5420_DP_BASE		0x145B0000
arch/arm/include/asm/arch-exynos/gpio.h +731 -11

801 lines not on this page · raw message

board/samsung/smdk5250/exynos5-dt.c +7 -13
index 379a45c..58821c4 100644
@@ -27,12 +27,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_SOUND_MAX98095
 static void board_enable_audio_codec(void)
 {
-	struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
-						samsung_get_base_gpio_part1();
-
 	/* Enable MAX98095 Codec */
-	s5p_gpio_direction_output(&gpio1->x1, 7, 1);
-	s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
+	gpio_direction_output(EXYNOS5_GPIO_X17, 1);
+	gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
 }
 #endif
 

@@ -47,19 +44,16 @@ int exynos_init(void)
 #ifdef CONFIG_LCD
 void exynos_cfg_lcd_gpio(void)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
-
 	/* For Backlight */
-	s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
-	s5p_gpio_set_value(&gpio1->b2, 0, 1);
+	gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
+	gpio_set_value(EXYNOS5_GPIO_B20, 1);
 
 	/* LCD power on */
-	s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
-	s5p_gpio_set_value(&gpio1->x1, 5, 1);
+	gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT);
+	gpio_set_value(EXYNOS5_GPIO_X15, 1);
 
 	/* Set Hotplug detect for DP */
-	s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+	gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
 }
 
 void exynos_set_dp_phy(unsigned int onoff)
board/samsung/smdk5250/smdk5250.c +7 -12
index 28a6d9e..bdfb49f 100644
@@ -29,12 +29,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_SOUND_MAX98095
 static void  board_enable_audio_codec(void)
 {
-	struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
-						samsung_get_base_gpio_part1();
-
 	/* Enable MAX98095 Codec */
-	s5p_gpio_direction_output(&gpio1->x1, 7, 1);
-	s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
+	gpio_direction_output(EXYNOS5_GPIO_X17, 1);
+	gpio_set_pull(EXYNOS5_GPIO_X17, GPIO_PULL_NONE);
 }
 #endif
 

@@ -275,19 +272,17 @@ int exynos_power_init(void)
 #ifdef CONFIG_LCD
 void exynos_cfg_lcd_gpio(void)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 
 	/* For Backlight */
-	s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
-	s5p_gpio_set_value(&gpio1->b2, 0, 1);
+	gpio_cfg_pin(EXYNOS5_GPIO_B20, GPIO_OUTPUT);
+	gpio_set_value(EXYNOS5_GPIO_B20, 1);
 
 	/* LCD power on */
-	s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
-	s5p_gpio_set_value(&gpio1->x1, 5, 1);
+	gpio_cfg_pin(EXYNOS5_GPIO_X15, GPIO_OUTPUT);
+	gpio_set_value(EXYNOS5_GPIO_X15, 1);
 
 	/* Set Hotplug detect for DP */
-	s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+	gpio_cfg_pin(EXYNOS5_GPIO_X07, GPIO_FUNC(0x3));
 }
 
 void exynos_set_dp_phy(unsigned int onoff)
board/samsung/smdk5420/smdk5420.c +6 -9
index e4606ec..fa3aa2c 100644
@@ -21,11 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_USB_EHCI_EXYNOS
 static int board_usb_vbus_init(void)
 {
-	struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
-						samsung_get_base_gpio_part1();
-
 	/* Enable VBUS power switch */
-	s5p_gpio_direction_output(&gpio1->x2, 6, 1);
+	gpio_direction_output(EXYNOS5420_GPIO_X26, 1);
 
 	/* VBUS turn ON time */
 	mdelay(3);

@@ -49,15 +46,15 @@ void cfg_lcd_gpio(void)
 		(struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
 
 	/* For Backlight */
-	s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
-	s5p_gpio_set_value(&gpio1->b2, 0, 1);
+	gpio_cfg_pin(EXYNOS5420_GPIO_B10, S5P_GPIO_OUTPUT);
+	gpio_set_value(EXYNOS5420_GPIO_B20, 1);
 
 	/* LCD power on */
-	s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
-	s5p_gpio_set_value(&gpio1->x1, 5, 1);
+	gpio_cfg_pin(EXYNOS5420_GPIO_X15, S5P_GPIO_OUTPUT);
+	gpio_set_value(EXYNOS5420_GPIO_X15, 1);
 
 	/* Set Hotplug detect for DP */
-	s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+	gpio_cfg_pin(EXYNOS5420_GPIO_X07, S5P_GPIO_FUNC(0x3));
 }
 
 vidinfo_t panel_info = {
drivers/gpio/s5p_gpio.c +43 -1

65 lines not on this page · raw message

Signature · 1 line
1.8.3.2
#2 lore raw

PATCH v6 1/4 EXYNOS5: Add gpio pin numbering feature

Quoted 10 lines · Akshay Saraswat

From: Rajeshwari Shinde <[email protected]>

This patch adds gpio pin numbering support for EXYNOS 5250 & 5420. To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.

Signed-off-by Leela Krishna Amudala <[email protected]>
Signed-off-by Rajeshwari Shinde <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>
Acked-by Simon Glass <[email protected]>

Tested on snow with backlight GPIOs.

#3 lore raw

PATCH v6 1/4 EXYNOS5: Add gpio pin numbering feature

In reply to Akshay Saraswat

Hi Akshay,

I'm not Samsung tree maintainer, but by chance I've come across those patches and...

First question - why have you omitted u-boot-samsung tree maintainer? I've added Minkyu to CC.

Also in the cover letter you claim that this patch was "build tested" for Exynos4 based boards. Why didn't you add at least one maintainer of those boards to CC?

arch/arm/include/asm/arch-exynos/gpio.h static inline unsigned int s5p_gpio_base(int gpio) · line 345

Quoted 9 lines
(quoted diff) +2 -0
+
+/* A list of valid GPIO numbers for the asm-generic/gpio.h interface

*/ +enum exynos5_gpio_pin {

arch/arm/include/asm/arch-exynos/gpio.h +6 -0
+	/* GPIO_PART1_STARTS */
+	EXYNOS5_GPIO_A00,	/* 0 */
+	EXYNOS5_GPIO_A01,
+	EXYNOS5_GPIO_A02,
+	EXYNOS5_GPIO_A03,
+	EXYNOS5_GPIO_A04,

According to the patch description, you had a compilation error when were adding the support for Exynos 5250 and 5420. Why you fix the problem by rewriting the whole framework?

IN the patch 2/4 you have:

- gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
- gpio_set_pull(start + i, GPIO_PULL_NONE);
- gpio_set_drv(start + i, GPIO_DRV_4X);
+ gpio_cfg_pin(start + i, S5P_GPIO_FUNC(0x2));
+ gpio_set_pull(start + i, S5P_GPIO_PULL_NONE);
+ gpio_set_drv(start + i, S5P_GPIO_DRV_4X);

What is the rationale to change the name to S5P_GPIO and not stick to GPIO_FUNC? In which way gpios for Exynos5 are different than for Exynos4? Cannot we finally reuse the Exynos 4 and 5 code?

With the same patch:

- case PERIPH_ID_UART1:
- bank = &gpio1->d0;
- start = 0;
+ start = EXYNOS5_GPIO_D00;

What is wrong with specifying the bank field? Why your gpio command cannot use the bank approach?

And one more question: Is this work compliant with new driver model, which will be accepted at the merge window after the v2014.04 release?

If not, then there is no point to review this code, since GPIO would need to be adjusted to use this framework.

--
Best regards,

Lukasz Majewski

Samsung R&D Institute Poland (SRPOL) | Linux Platform Group

#4 lore raw

PATCH v6 1/4 EXYNOS5: Add gpio pin numbering feature

Hi Lukasz,

On 14 April 2014 01:17, Lukasz Majewski <[email protected]> wrote:

[snip[

I think your questions are mostly answered but I wanted to chime in on a few.

What is wrong with specifying the bank field?

Quoted 2 lines

Why your gpio command cannot use the bank approach?

U-Boot has a generic GPIO API and we should try to use it where possible. This has been a long-standing TODO for exynos.

Quoted 7 lines

And one more question: Is this work compliant with new driver model, which will be accepted at the merge window after the v2014.04 release?

If not, then there is no point to review this code, since GPIO would need to be adjusted to use this framework.

The driver model framework is already in mainline. At present only sandbox uses it for GPIO. I started looking at exynos since I thought it might be quite easy to convert, but found that the generic GPIO stuff was still not merged.

This series will make it much easier to convert exynos GPIO to driver model, since we can just change the driver.

Regards,
Simon

#5 lore raw

PATCH v6 1/4 EXYNOS5: Add gpio pin numbering feature

Hi Simon,

Quoted 10 lines

Hi Lukasz,

On 14 April 2014 01:17, Lukasz Majewski <[email protected]> wrote:

[snip[

I think your questions are mostly answered but I wanted to chime in on a few.

Quoted 6 lines

What is wrong with specifying the bank field?

Quoted 2 lines

Why your gpio command cannot use the bank approach?

U-Boot has a generic GPIO API and we should try to use it where possible. This has been a long-standing TODO for exynos.

I'm also fully aware that Exynos suffers from inconsistent gpio API. However, I'm very glad that with Akshay's and our effort this goal will be accomplished :-)

Quoted 7 lines
Quoted 7 lines

And one more question: Is this work compliant with new driver model, which will be accepted at the merge window after the v2014.04 release?

Quoted 5 lines
Quoted 3 lines

If not, then there is no point to review this code, since GPIO would need to be adjusted to use this framework.

The driver model framework is already in mainline.

I was rather thinking about the "big switch" as we did with KBUILD after the v2014.01. Anyway, I'm looking forward to see the wide deployment of device model in u-boot.

Quoted 7 lines

At present only
sandbox uses it for GPIO. I started looking at exynos since I thought it might be quite easy to convert, but found that the generic GPIO stuff was still not merged.

This series will make it much easier to convert exynos GPIO to driver model, since we can just change the driver.

Thanks for clarification.

Quoted 4 lines

Regards,
Simon

Signature · 5 lines
Best regards,

Lukasz Majewski

Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
#6 lore raw

PATCH v6 1/4 EXYNOS5: Add gpio pin numbering feature

Hi Lukasz,

Quoted 34 lines · Lukasz Majewski

Hi Simon,

Quoted 10 lines

Hi Lukasz,

On 14 April 2014 01:17, Lukasz Majewski <[email protected]> wrote:

[snip[

I think your questions are mostly answered but I wanted to chime in on a few.

Quoted 6 lines

What is wrong with specifying the bank field?

Quoted 2 lines

Why your gpio command cannot use the bank approach?

U-Boot has a generic GPIO API and we should try to use it where possible. This has been a long-standing TODO for exynos.

I'm also fully aware that Exynos suffers from inconsistent gpio API. However, I'm very glad that with Akshay's and our effort this goal will be accomplished :-)

Quoted 11 lines
Quoted 10 lines

And one more question: Is this work compliant with new driver model, which will be accepted at the merge window after the v2014.04 release?

If not, then there is no point to review this code, since GPIO would need to be adjusted to use this framework.

Quoted 6 lines
Quoted 1 line

The driver model framework is already in mainline.

I was rather thinking about the "big switch" as we did with KBUILD after the v2014.01. Anyway, I'm looking forward to see the wide deployment of device model in u-boot.

I don't expect a big switch. Each subsystem needs to add support for it, and then (as a separate step) each driver needs to be ported into the new uclass. So it will likely be an incremental effort.

Quoted 10 lines
Quoted 7 lines

At present only
sandbox uses it for GPIO. I started looking at exynos since I thought it might be quite easy to convert, but found that the generic GPIO stuff was still not merged.

This series will make it much easier to convert exynos GPIO to driver model, since we can just change the driver.

Thanks for clarification.

I'm probably going to take a look at Tegra while waiting for this series to land. Let's see how it goes.

Regards,
Simon

#7 lore raw

PATCH v6 1/4 EXYNOS5: Add gpio pin numbering feature

In reply to Akshay Saraswat

Hello,
I like this idea. This is a good feature for easy and fast gpio maintaining. I have few comments to this.

Quoted 10 lines · Akshay Saraswat

From: Rajeshwari Shinde <[email protected]>

This patch adds gpio pin numbering support for EXYNOS 5250 & 5420. To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.

Signed-off-by Leela Krishna Amudala <[email protected]>
Signed-off-by Rajeshwari Shinde <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>

---

You use quite magic numbers in gpio names like "EXYNOS5_GPIO_A05", maybe better is to add "PIN" word here like this: EXYNOS5_GPIO_A0_PIN5. So then we really know what we are using and I think this just looks better.

arch/arm/include/asm/arch-exynos/gpio.h struct exynos5420_gpio_part1 { · line 141

Quoted 6 lines
arch/arm/include/asm/arch-exynos/gpio.h +0 -0
index d6868fa..211383d 100644
@@ -141,14 +141,16 @@ struct exynos5420_gpio_part1 {

It seems that those all exynos5*_gpio_partX structures and also exynos5*_gpio_get() macros can be removed now.

Quoted 75 lines
arch/arm/include/asm/arch-exynos/gpio.h +18 -10
  struct exynos5420_gpio_part2 {
  	struct s5p_gpio_bank y7; /* 0x1340_0000 */
-	struct s5p_gpio_bank res[0x5f]; /*  */
+};
+
+struct exynos5420_gpio_part3 {
  	struct s5p_gpio_bank x0; /* 0x1340_0C00 */
  	struct s5p_gpio_bank x1; /* 0x1340_0C20 */
  	struct s5p_gpio_bank x2; /* 0x1340_0C40 */
  	struct s5p_gpio_bank x3; /* 0x1340_0C60 */
  };
 
-struct exynos5420_gpio_part3 {
+struct exynos5420_gpio_part4 {
  	struct s5p_gpio_bank c0;
  	struct s5p_gpio_bank c1;
  	struct s5p_gpio_bank c2;

@@ -164,7 +166,7 @@ struct exynos5420_gpio_part3 {
  	struct s5p_gpio_bank y6;
  };
 
-struct exynos5420_gpio_part4 {
+struct exynos5420_gpio_part5 {
  	struct s5p_gpio_bank e0; /* 0x1400_0000 */
  	struct s5p_gpio_bank e1; /* 0x1400_0020 */
  	struct s5p_gpio_bank f0; /* 0x1400_0040 */

@@ -175,7 +177,7 @@ struct exynos5420_gpio_part4 {
  	struct s5p_gpio_bank j4; /* 0x1400_00E0 */
  };
 
-struct exynos5420_gpio_part5 {
+struct exynos5420_gpio_part6 {
  	struct s5p_gpio_bank z0; /* 0x0386_0000 */
  };
 

@@ -200,16 +202,20 @@ struct exynos5_gpio_part1 {
  	struct s5p_gpio_bank y4;
  	struct s5p_gpio_bank y5;
  	struct s5p_gpio_bank y6;
-	struct s5p_gpio_bank res1[0x3];
+};
+
+struct exynos5_gpio_part2 {
  	struct s5p_gpio_bank c4;
-	struct s5p_gpio_bank res2[0x48];
+};
+
+struct exynos5_gpio_part3 {
  	struct s5p_gpio_bank x0;
  	struct s5p_gpio_bank x1;
  	struct s5p_gpio_bank x2;
  	struct s5p_gpio_bank x3;
  };
 
-struct exynos5_gpio_part2 {
+struct exynos5_gpio_part4 {
  	struct s5p_gpio_bank e0;
  	struct s5p_gpio_bank e1;
  	struct s5p_gpio_bank f0;

@@ -221,20 +227,25 @@ struct exynos5_gpio_part2 {
  	struct s5p_gpio_bank h1;
  };
 
-struct exynos5_gpio_part3 {
+struct exynos5_gpio_part5 {
  	struct s5p_gpio_bank v0;
  	struct s5p_gpio_bank v1;
-	struct s5p_gpio_bank res1[0x1];
+};
+
+struct exynos5_gpio_part6 {
  	struct s5p_gpio_bank v2;
  	struct s5p_gpio_bank v3;
-	struct s5p_gpio_bank res2[0x1];
+};

arch/arm/include/asm/arch-exynos/gpio.h struct exynos5_gpio_part2 { · line 247

Quoted 10 lines
arch/arm/include/asm/arch-exynos/gpio.h +3 -1
+
+struct exynos5_gpio_part7 {
  	struct s5p_gpio_bank v4;
  };
 
-struct exynos5_gpio_part4 {
+struct exynos5_gpio_part8 {
  	struct s5p_gpio_bank z;
  };

There are also unchanged gpios initializations in files:
- arndale/arndale.c line 19
- smdk5420/smdk5420.c line 45

Thanks

Signature · 4 lines
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com
#8 lore raw

PATCH v6 1/4 EXYNOS5: Add gpio pin numbering feature

Hi,

Quoted 19 lines · Przemyslaw Marczak

Hello,
I like this idea. This is a good feature for easy and fast gpio maintaining. I have few comments to this.

Quoted 11 lines · Akshay Saraswat

From: Rajeshwari Shinde <[email protected]>

This patch adds gpio pin numbering support for EXYNOS 5250 & 5420. To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.

Signed-off-by Leela Krishna Amudala <[email protected]>
Signed-off-by Rajeshwari Shinde <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>

---

Quoted 4 lines

You use quite magic numbers in gpio names like "EXYNOS5_GPIO_A05", maybe better is to add "PIN" word here like this: EXYNOS5_GPIO_A0_PIN5. So then we really know what we are using and I think this just looks better.

I'm not sure I agree with the idea of a more verbose naming. The naming in this series fits better with the idea of numbered GPIOs. The bank number is of limited interest to users of GPIOs anyway. Exynos is slightly odd in that banks have both a letter and number (A0, A1), but that doesn't seem like a reason to change.

Regards,
Simon

author
#9 lore raw

PATCH v6 2/4 S5P: Rename GPIO definitions

In reply to Akshay Saraswat

From: Rajeshwari Shinde <[email protected]>

This patch rename GPIO definitions from GPIO_... to S5P_GPIO_... This changes was done to enable cmd_gpio for EXYNOS and cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence getting a error during compilation.

Build tested for s5p_goni, origen, smdk5250, s5pc210_universal, trats, smdkc100, smdkv310 config files.

Signed-off-by Rajeshwari Shinde <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>
---
 arch/arm/cpu/armv7/exynos/pinmux.c       | 220 +++++++++++++++----------------
 arch/arm/include/asm/arch-exynos/gpio.h  |  26 ++--
 arch/arm/include/asm/arch-s5pc1xx/gpio.h |  26 ++--
 board/samsung/goni/goni.c                |   4 +-
 board/samsung/smdk5250/smdk5250.c        |   8 +-
 board/samsung/smdkc100/smdkc100.c        |   2 +-
 board/samsung/smdkv310/smdkv310.c        |  10 +-
 board/samsung/trats/trats.c              |   6 +-
 board/samsung/universal_c210/universal.c |  34 ++---
 drivers/gpio/s5p_gpio.c                  |  20 +--
 10 files changed, 178 insertions(+), 178 deletions(-)
arch/arm/cpu/armv7/exynos/pinmux.c +110 -110
index 34c24cd..9added6 100644
@@ -37,8 +37,8 @@ static void exynos5_uart_config(int peripheral)
 		return;
 	}
 	for (i = start; i < start + count; i++) {
-		gpio_set_pull(i, GPIO_PULL_NONE);
-		gpio_cfg_pin(i, GPIO_FUNC(0x2));
+		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+		gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
 	}
 }
 

@@ -69,8 +69,8 @@ static void exynos5420_uart_config(int peripheral)
 	}
 
 	for (i = start; i < start + count; i++) {
-		gpio_set_pull(i, GPIO_PULL_NONE);
-		gpio_cfg_pin(i, GPIO_FUNC(0x2));
+		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+		gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
 	}
 }
 

@@ -82,7 +82,7 @@ static int exynos5_mmc_config(int peripheral, int flags)
 	case PERIPH_ID_SDMMC0:
 		start = EXYNOS5_GPIO_C00;
 		start_ext = EXYNOS5_GPIO_C10;
-		gpio_func = GPIO_FUNC(0x2);
+		gpio_func = S5P_GPIO_FUNC(0x2);
 		break;
 	case PERIPH_ID_SDMMC1:
 		start = EXYNOS5_GPIO_C20;

@@ -91,7 +91,7 @@ static int exynos5_mmc_config(int peripheral, int flags)
 	case PERIPH_ID_SDMMC2:
 		start = EXYNOS5_GPIO_C30;
 		start_ext = EXYNOS5_GPIO_C43;
-		gpio_func = GPIO_FUNC(0x3);
+		gpio_func = S5P_GPIO_FUNC(0x3);
 		break;
 	case PERIPH_ID_SDMMC3:
 		start = EXYNOS5_GPIO_C40;

@@ -109,19 +109,19 @@ static int exynos5_mmc_config(int peripheral, int flags)
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
 		for (i = start_ext; i <= (start_ext + 3); i++) {
 			gpio_cfg_pin(i, gpio_func);
-			gpio_set_pull(i, GPIO_PULL_UP);
-			gpio_set_drv(i, GPIO_DRV_4X);
+			gpio_set_pull(i, S5P_GPIO_PULL_UP);
+			gpio_set_drv(i, S5P_GPIO_DRV_4X);
 		}
 	}
 	for (i = 0; i < 2; i++) {
-		gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
-		gpio_set_pull(start + i, GPIO_PULL_NONE);
-		gpio_set_drv(start + i, GPIO_DRV_4X);
+		gpio_cfg_pin(start + i, S5P_GPIO_FUNC(0x2));
+		gpio_set_pull(start + i, S5P_GPIO_PULL_NONE);
+		gpio_set_drv(start + i, S5P_GPIO_DRV_4X);
 	}
 	for (i = 3; i <= 6; i++) {
-		gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
-		gpio_set_pull(start + i, GPIO_PULL_UP);
-		gpio_set_drv(start + i, GPIO_DRV_4X);
+		gpio_cfg_pin(start + i, S5P_GPIO_FUNC(0x2));
+		gpio_set_pull(start + i, S5P_GPIO_PULL_UP);
+		gpio_set_drv(start + i, S5P_GPIO_DRV_4X);
 	}
 
 	return 0;

@@ -161,9 +161,9 @@ static int exynos5420_mmc_config(int peripheral, int flags)
 
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
 		for (i = start; i <= (start + 3); i++) {
-			gpio_cfg_pin(i, GPIO_FUNC(0x2));
-			gpio_set_pull(i, GPIO_PULL_UP);
-			gpio_set_drv(i, GPIO_DRV_4X);
+			gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+			gpio_set_pull(i, S5P_GPIO_PULL_UP);
+			gpio_set_drv(i, S5P_GPIO_DRV_4X);
 		}
 	}
 

@@ -176,18 +176,18 @@ static int exynos5420_mmc_config(int peripheral, int flags)
 		 */
 		if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) {
 			gpio_set_value(i, 1);
-			gpio_cfg_pin(i, GPIO_OUTPUT);
+			gpio_cfg_pin(i, S5P_GPIO_OUTPUT);
 		} else {
-			gpio_cfg_pin(i, GPIO_FUNC(0x2));
+			gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
 		}
-		gpio_set_pull(i, GPIO_PULL_NONE);
-		gpio_set_drv(i, GPIO_DRV_4X);
+		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+		gpio_set_drv(i, S5P_GPIO_DRV_4X);
 	}
 
 	for (i = 3; i <= 6; i++) {
-		gpio_cfg_pin(i, GPIO_FUNC(0x2));
-		gpio_set_pull(i, GPIO_PULL_UP);
-		gpio_set_drv(i, GPIO_DRV_4X);
+		gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+		gpio_set_pull(i, S5P_GPIO_PULL_UP);
+		gpio_set_drv(i, S5P_GPIO_DRV_4X);
 	}
 
 	return 0;

@@ -213,12 +213,12 @@ static void exynos5_sromc_config(int flags)
 	 * GPY1[3]	EBI_DATA_RDn(2)
 	 */
 	gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK),
-		     GPIO_FUNC(2));
-	gpio_cfg_pin(EXYNOS5_GPIO_Y04, GPIO_FUNC(2));
-	gpio_cfg_pin(EXYNOS5_GPIO_Y05, GPIO_FUNC(2));
+		     S5P_GPIO_FUNC(2));
+	gpio_cfg_pin(EXYNOS5_GPIO_Y04, S5P_GPIO_FUNC(2));
+	gpio_cfg_pin(EXYNOS5_GPIO_Y05, S5P_GPIO_FUNC(2));
 
 	for (i = 0; i < 4; i++)
-		gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, GPIO_FUNC(2));
+		gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, S5P_GPIO_FUNC(2));
 
 	/*
 	 * EBI: 8 Addrss Lines

@@ -253,14 +253,14 @@ static void exynos5_sromc_config(int flags)
 	 * GPY6[7]	EBI_DATA[15](2)
 	 */
 	for (i = 0; i < 8; i++) {
-		gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, GPIO_FUNC(2));
-		gpio_set_pull(EXYNOS5_GPIO_Y30 + i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_PULL_UP);
 
-		gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, GPIO_FUNC(2));
-		gpio_set_pull(EXYNOS5_GPIO_Y50 + i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_PULL_UP);
 
-		gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, GPIO_FUNC(2));
-		gpio_set_pull(EXYNOS5_GPIO_Y60 + i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_PULL_UP);
 	}
 }
 

@@ -268,36 +268,36 @@ static void exynos5_i2c_config(int peripheral, int flags)
 {
 	switch (peripheral) {
 	case PERIPH_ID_I2C0:
-		gpio_cfg_pin(EXYNOS5_GPIO_B30, GPIO_FUNC(0x2));
-		gpio_cfg_pin(EXYNOS5_GPIO_B31, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C1:
-		gpio_cfg_pin(EXYNOS5_GPIO_B32, GPIO_FUNC(0x2));
-		gpio_cfg_pin(EXYNOS5_GPIO_B33, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C2:
-		gpio_cfg_pin(EXYNOS5_GPIO_A06, GPIO_FUNC(0x3));
-		gpio_cfg_pin(EXYNOS5_GPIO_A07, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C3:
-		gpio_cfg_pin(EXYNOS5_GPIO_A12, GPIO_FUNC(0x3));
-		gpio_cfg_pin(EXYNOS5_GPIO_A13, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C4:
-		gpio_cfg_pin(EXYNOS5_GPIO_A20, GPIO_FUNC(0x3));
-		gpio_cfg_pin(EXYNOS5_GPIO_A21, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A21, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C5:
-		gpio_cfg_pin(EXYNOS5_GPIO_A22, GPIO_FUNC(0x3));
-		gpio_cfg_pin(EXYNOS5_GPIO_A23, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A22, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A23, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C6:
-		gpio_cfg_pin(EXYNOS5_GPIO_B13, GPIO_FUNC(0x4));
-		gpio_cfg_pin(EXYNOS5_GPIO_B14, GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5_GPIO_B13, S5P_GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5_GPIO_B14, S5P_GPIO_FUNC(0x4));
 		break;
 	case PERIPH_ID_I2C7:
-		gpio_cfg_pin(EXYNOS5_GPIO_B22, GPIO_FUNC(0x3));
-		gpio_cfg_pin(EXYNOS5_GPIO_B23, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_B22, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_B23, S5P_GPIO_FUNC(0x3));
 		break;
 	}
 }

@@ -306,48 +306,48 @@ static void exynos5420_i2c_config(int peripheral)
 {
 	switch (peripheral) {
 	case PERIPH_ID_I2C0:
-		gpio_cfg_pin(EXYNOS5420_GPIO_B30, GPIO_FUNC(0x2));
-		gpio_cfg_pin(EXYNOS5420_GPIO_B31, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B30, S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B31, S5P_GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C1:
-		gpio_cfg_pin(EXYNOS5420_GPIO_B32, GPIO_FUNC(0x2));
-		gpio_cfg_pin(EXYNOS5420_GPIO_B33, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B32, S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B33, S5P_GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C2:
-		gpio_cfg_pin(EXYNOS5420_GPIO_A06, GPIO_FUNC(0x3));
-		gpio_cfg_pin(EXYNOS5420_GPIO_A07, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A06, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A07, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C3:
-		gpio_cfg_pin(EXYNOS5420_GPIO_A12, GPIO_FUNC(0x3));
-		gpio_cfg_pin(EXYNOS5420_GPIO_A13, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A12, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A13, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C4:
-		gpio_cfg_pin(EXYNOS5420_GPIO_A20, GPIO_FUNC(0x3));
-		gpio_cfg_pin(EXYNOS5420_GPIO_A21, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A20, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A21, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C5:
-		gpio_cfg_pin(EXYNOS5420_GPIO_A22, GPIO_FUNC(0x3));
-		gpio_cfg_pin(EXYNOS5420_GPIO_A23, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A22, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_A23, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C6:
-		gpio_cfg_pin(EXYNOS5420_GPIO_B13, GPIO_FUNC(0x4));
-		gpio_cfg_pin(EXYNOS5420_GPIO_B14, GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B13, S5P_GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B14, S5P_GPIO_FUNC(0x4));
 		break;
 	case PERIPH_ID_I2C7:
-		gpio_cfg_pin(EXYNOS5420_GPIO_B22, GPIO_FUNC(0x3));
-		gpio_cfg_pin(EXYNOS5420_GPIO_B23, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B22, S5P_GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B23, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C8:
-		gpio_cfg_pin(EXYNOS5420_GPIO_B34, GPIO_FUNC(0x2));
-		gpio_cfg_pin(EXYNOS5420_GPIO_B35, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B34, S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B35, S5P_GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C9:
-		gpio_cfg_pin(EXYNOS5420_GPIO_B36, GPIO_FUNC(0x2));
-		gpio_cfg_pin(EXYNOS5420_GPIO_B37, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B36, S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B37, S5P_GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C10:
-		gpio_cfg_pin(EXYNOS5420_GPIO_B40, GPIO_FUNC(0x2));
-		gpio_cfg_pin(EXYNOS5420_GPIO_B41, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B40, S5P_GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5420_GPIO_B41, S5P_GPIO_FUNC(0x2));
 		break;
 	}
 }

@@ -359,11 +359,11 @@ static void exynos5_i2s_config(int peripheral)
 	switch (peripheral) {
 	case PERIPH_ID_I2S0:
 		for (i = 0; i < 5; i++)
-			gpio_cfg_pin(EXYNOS5_GPIO_Z0+i, GPIO_FUNC(0x02));
+			gpio_cfg_pin(EXYNOS5_GPIO_Z0+i, S5P_GPIO_FUNC(0x02));
 		break;
 	case PERIPH_ID_I2S1:
 		for (i = 0; i < 5; i++)
-			gpio_cfg_pin(EXYNOS5_GPIO_B00+i, GPIO_FUNC(0x02));
+			gpio_cfg_pin(EXYNOS5_GPIO_B00+i, S5P_GPIO_FUNC(0x02));
 		break;
 	}
 }

@@ -374,25 +374,25 @@ void exynos5_spi_config(int peripheral)
 
 	switch (peripheral) {
 	case PERIPH_ID_SPI0:
-		cfg = GPIO_FUNC(0x2);
+		cfg = S5P_GPIO_FUNC(0x2);
 		pin = EXYNOS5_GPIO_A20;
 		break;
 	case PERIPH_ID_SPI1:
-		cfg = GPIO_FUNC(0x2);
+		cfg = S5P_GPIO_FUNC(0x2);
 		pin = EXYNOS5_GPIO_A24;
 		break;
 	case PERIPH_ID_SPI2:
-		cfg = GPIO_FUNC(0x5);
+		cfg = S5P_GPIO_FUNC(0x5);
 		pin = EXYNOS5_GPIO_B11;
 		break;
 	case PERIPH_ID_SPI3:
-		cfg = GPIO_FUNC(0x2);
+		cfg = S5P_GPIO_FUNC(0x2);
 		pin = EXYNOS5_GPIO_F10;
 		break;
 	case PERIPH_ID_SPI4:
 		for (i = 0; i < 2; i++) {
-			gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, GPIO_FUNC(0x4));
-			gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, GPIO_FUNC(0x4));
+			gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, S5P_GPIO_FUNC(0x4));
+			gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, S5P_GPIO_FUNC(0x4));
 		}
 		break;
 	}

@@ -409,19 +409,19 @@ void exynos5420_spi_config(int peripheral)
 	switch (peripheral) {
 	case PERIPH_ID_SPI0:
 		pin = EXYNOS5420_GPIO_A20;
-		cfg = GPIO_FUNC(0x2);
+		cfg = S5P_GPIO_FUNC(0x2);
 		break;
 	case PERIPH_ID_SPI1:
 		pin = EXYNOS5420_GPIO_A24;
-		cfg = GPIO_FUNC(0x2);
+		cfg = S5P_GPIO_FUNC(0x2);
 		break;
 	case PERIPH_ID_SPI2:
 		pin = EXYNOS5420_GPIO_B11;
-		cfg = GPIO_FUNC(0x5);
+		cfg = S5P_GPIO_FUNC(0x5);
 		break;
 	case PERIPH_ID_SPI3:
 		pin = EXYNOS5420_GPIO_F10;
-		cfg = GPIO_FUNC(0x2);
+		cfg = S5P_GPIO_FUNC(0x2);
 		break;
 	case PERIPH_ID_SPI4:
 		cfg = 0;

@@ -440,9 +440,9 @@ void exynos5420_spi_config(int peripheral)
 	} else {
 		for (i = 0; i < 2; i++) {
 			gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i,
-				     GPIO_FUNC(0x4));
+				     S5P_GPIO_FUNC(0x4));
 			gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i,
-				     GPIO_FUNC(0x4));
+				     S5P_GPIO_FUNC(0x4));
 		}
 	}
 }

@@ -542,36 +542,36 @@ static void exynos4_i2c_config(int peripheral, int flags)
 
 	switch (peripheral) {
 	case PERIPH_ID_I2C0:
-		s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->d1, 0, S5P_GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->d1, 1, S5P_GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C1:
-		s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->d1, 2, S5P_GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->d1, 3, S5P_GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C2:
-		s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a0, 6, S5P_GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a0, 7, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C3:
-		s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a1, 2, S5P_GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a1, 3, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C4:
-		s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->b, 2, S5P_GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->b, 3, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C5:
-		s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->b, 6, S5P_GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->b, 7, S5P_GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C6:
-		s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
-		s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
+		s5p_gpio_cfg_pin(&gpio1->c1, 3, S5P_GPIO_FUNC(0x4));
+		s5p_gpio_cfg_pin(&gpio1->c1, 4, S5P_GPIO_FUNC(0x4));
 		break;
 	case PERIPH_ID_I2C7:
-		s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->d0, 2, S5P_GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->d0, 3, S5P_GPIO_FUNC(0x3));
 		break;
 	}
 }

@@ -598,15 +598,15 @@ static int exynos4_mmc_config(int peripheral, int flags)
 	for (i = 0; i < 7; i++) {
 		if (i == 2)
 			continue;
-		s5p_gpio_cfg_pin(bank, i,  GPIO_FUNC(0x2));
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+		s5p_gpio_cfg_pin(bank, i,  S5P_GPIO_FUNC(0x2));
+		s5p_gpio_set_pull(bank, i, S5P_GPIO_PULL_NONE);
+		s5p_gpio_set_drv(bank, i, S5P_GPIO_DRV_4X);
 	}
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
 		for (i = 3; i < 7; i++) {
-			s5p_gpio_cfg_pin(bank_ext, i,  GPIO_FUNC(0x3));
-			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
-			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+			s5p_gpio_cfg_pin(bank_ext, i,  S5P_GPIO_FUNC(0x3));
+			s5p_gpio_set_pull(bank_ext, i, S5P_GPIO_PULL_NONE);
+			s5p_gpio_set_drv(bank_ext, i, S5P_GPIO_DRV_4X);
 		}
 	}
 

@@ -646,8 +646,8 @@ static void exynos4_uart_config(int peripheral)
 		return;
 	}
 	for (i = start; i < start + count; i++) {
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+		s5p_gpio_set_pull(bank, i, S5P_GPIO_PULL_NONE);
+		s5p_gpio_cfg_pin(bank, i, S5P_GPIO_FUNC(0x2));
 	}
 }
 static int exynos4_pinmux_config(int peripheral, int flags)
arch/arm/include/asm/arch-exynos/gpio.h +13 -13
index 211383d..697e6f3 100644
@@ -1046,21 +1046,21 @@ int gpio_set_value(unsigned gpio, int value);
 #endif
 
 /* Pin configurations */
-#define GPIO_INPUT	0x0
-#define GPIO_OUTPUT	0x1
-#define GPIO_IRQ	0xf
-#define GPIO_FUNC(x)	(x)
+#define S5P_GPIO_INPUT	0x0
+#define S5P_GPIO_OUTPUT	0x1
+#define S5P_GPIO_IRQ	0xf
+#define S5P_GPIO_FUNC(x)	(x)
 
 /* Pull mode */
-#define GPIO_PULL_NONE	0x0
-#define GPIO_PULL_DOWN	0x1
-#define GPIO_PULL_UP	0x3
+#define S5P_GPIO_PULL_NONE	0x0
+#define S5P_GPIO_PULL_DOWN	0x1
+#define S5P_GPIO_PULL_UP	0x3
 
 /* Drive Strength level */
-#define GPIO_DRV_1X	0x0
-#define GPIO_DRV_3X	0x1
-#define GPIO_DRV_2X	0x2
-#define GPIO_DRV_4X	0x3
-#define GPIO_DRV_FAST	0x0
-#define GPIO_DRV_SLOW	0x1
+#define S5P_GPIO_DRV_1X	0x0
+#define S5P_GPIO_DRV_3X	0x1
+#define S5P_GPIO_DRV_2X	0x2
+#define S5P_GPIO_DRV_4X	0x3
+#define S5P_GPIO_DRV_FAST	0x0
+#define S5P_GPIO_DRV_SLOW	0x1
 #endif
arch/arm/include/asm/arch-s5pc1xx/gpio.h +13 -13
index da8df74..dd94eb8 100644
@@ -167,22 +167,22 @@ static inline unsigned int s5p_gpio_base(int nr)
 #endif
 
 /* Pin configurations */
-#define GPIO_INPUT	0x0
-#define GPIO_OUTPUT	0x1
-#define GPIO_IRQ	0xf
-#define GPIO_FUNC(x)	(x)
+#define S5P_GPIO_INPUT	0x0
+#define S5P_GPIO_OUTPUT	0x1
+#define S5P_GPIO_IRQ	0xf
+#define S5P_GPIO_FUNC(x)	(x)
 
 /* Pull mode */
-#define GPIO_PULL_NONE	0x0
-#define GPIO_PULL_DOWN	0x1
-#define GPIO_PULL_UP	0x2
+#define S5P_GPIO_PULL_NONE	0x0
+#define S5P_GPIO_PULL_DOWN	0x1
+#define S5P_GPIO_PULL_UP	0x2
 
 /* Drive Strength level */
-#define GPIO_DRV_1X	0x0
-#define GPIO_DRV_3X	0x1
-#define GPIO_DRV_2X	0x2
-#define GPIO_DRV_4X	0x3
-#define GPIO_DRV_FAST	0x0
-#define GPIO_DRV_SLOW	0x1
+#define S5P_GPIO_DRV_1X	0x0
+#define S5P_GPIO_DRV_3X	0x1
+#define S5P_GPIO_DRV_2X	0x2
+#define S5P_GPIO_DRV_4X	0x3
+#define S5P_GPIO_DRV_FAST	0x0
+#define S5P_GPIO_DRV_SLOW	0x1
 
 #endif
board/samsung/goni/goni.c +2 -2
index 61b9ece..b0563da 100644
@@ -97,9 +97,9 @@ int board_mmc_init(bd_t *bis)
 		/* GPG0[0:6] special function 2 */
 		s5p_gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2);
 		/* GPG0[0:6] pull disable */
-		s5p_gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE);
+		s5p_gpio_set_pull(&s5pc110_gpio->g0, i, S5P_GPIO_PULL_NONE);
 		/* GPG0[0:6] drv 4x */
-		s5p_gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X);
+		s5p_gpio_set_drv(&s5pc110_gpio->g0, i, S5P_GPIO_DRV_4X);
 	}
 
 	ret = s5p_mmc_init(0, 4);
board/samsung/smdk5250/smdk5250.c +4 -4
index bdfb49f..014b7bd 100644
@@ -31,7 +31,7 @@ static void  board_enable_audio_codec(void)
 {
 	/* Enable MAX98095 Codec */
 	gpio_direction_output(EXYNOS5_GPIO_X17, 1);
-	gpio_set_pull(EXYNOS5_GPIO_X17, GPIO_PULL_NONE);
+	gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
 }
 #endif
 

@@ -274,15 +274,15 @@ void exynos_cfg_lcd_gpio(void)
 {
 
 	/* For Backlight */
-	gpio_cfg_pin(EXYNOS5_GPIO_B20, GPIO_OUTPUT);
+	gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
 	gpio_set_value(EXYNOS5_GPIO_B20, 1);
 
 	/* LCD power on */
-	gpio_cfg_pin(EXYNOS5_GPIO_X15, GPIO_OUTPUT);
+	gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT);
 	gpio_set_value(EXYNOS5_GPIO_X15, 1);
 
 	/* Set Hotplug detect for DP */
-	gpio_cfg_pin(EXYNOS5_GPIO_X07, GPIO_FUNC(0x3));
+	gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
 }
 
 void exynos_set_dp_phy(unsigned int onoff)
board/samsung/smdkc100/smdkc100.c +1 -1
index 860c851..e637b21 100644
@@ -25,7 +25,7 @@ static void smc9115_pre_init(void)
 		(struct s5pc100_gpio *)samsung_get_base_gpio();
 
 	/* gpio configuration GPK0CON */
-	s5p_gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
+	s5p_gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
 
 	/* Ethernet needs bus width of 16 bits */
 	smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
board/samsung/smdkv310/smdkv310.c +5 -5
index 81a3060..171a4a1 100644
@@ -23,7 +23,7 @@ static void smc9115_pre_init(void)
 	u32 smc_bw_conf, smc_bc_conf;
 
 	/* gpio configuration GPK0CON */
-	s5p_gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
+	s5p_gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
 
 	/* Ethernet needs bus width of 16 bits */
 	smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);

@@ -105,19 +105,19 @@ int board_mmc_init(bd_t *bis)
 	 */
 	for (i = 0; i < 7; i++) {
 		/* GPK2[0:6] special function 2 */
-		s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio2->k2, i, S5P_GPIO_FUNC(0x2));
 
 		/* GPK2[0:6] drv 4x */
-		s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
+		s5p_gpio_set_drv(&gpio2->k2, i, S5P_GPIO_DRV_4X);
 
 		/* GPK2[0:1] pull disable */
 		if (i == 0 || i == 1) {
-			s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
+			s5p_gpio_set_pull(&gpio2->k2, i, S5P_GPIO_PULL_NONE);
 			continue;
 		}
 
 		/* GPK2[2:6] pull up */
-		s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP);
+		s5p_gpio_set_pull(&gpio2->k2, i, S5P_GPIO_PULL_UP);
 	}
 	err = s5p_mmc_init(2, 4);
 	return err;
board/samsung/trats/trats.c +3 -3
index 7c79e7b..701a48a 100644
@@ -354,8 +354,8 @@ static unsigned int get_hw_revision(void)
 
 	/* hw_rev[3:0] == GPE1[3:0] */
 	for (i = 0; i < 4; i++) {
-		s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
-		s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
+		s5p_gpio_cfg_pin(&gpio->e1, i, S5P_GPIO_INPUT);
+		s5p_gpio_set_pull(&gpio->e1, i, S5P_GPIO_PULL_NONE);
 	}
 
 	udelay(1);

@@ -448,7 +448,7 @@ static void pmic_reset(void)
 		(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 
 	s5p_gpio_direction_output(&gpio->x0, 7, 1);
-	s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
+	s5p_gpio_set_pull(&gpio->x2, 7, S5P_GPIO_PULL_NONE);
 }
 
 static void board_clock_init(void)
board/samsung/universal_c210/universal.c +17 -17
index f9d71b6..e87e54c 100644
@@ -312,35 +312,35 @@ void exynos_cfg_lcd_gpio(void)
 
 	for (i = 0; i < 8; i++) {
 		/* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
-		s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2));
-		s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2));
-		s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2));
+		s5p_gpio_cfg_pin(&gpio1->f0, i, S5P_GPIO_FUNC(2));
+		s5p_gpio_cfg_pin(&gpio1->f1, i, S5P_GPIO_FUNC(2));
+		s5p_gpio_cfg_pin(&gpio1->f2, i, S5P_GPIO_FUNC(2));
 		/* pull-up/down disable */
-		s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE);
-		s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE);
-		s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE);
+		s5p_gpio_set_pull(&gpio1->f0, i, S5P_GPIO_PULL_NONE);
+		s5p_gpio_set_pull(&gpio1->f1, i, S5P_GPIO_PULL_NONE);
+		s5p_gpio_set_pull(&gpio1->f2, i, S5P_GPIO_PULL_NONE);
 
 		/* drive strength to max (24bit) */
-		s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X);
-		s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
-		s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X);
-		s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW);
-		s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X);
-		s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
+		s5p_gpio_set_drv(&gpio1->f0, i, S5P_GPIO_DRV_4X);
+		s5p_gpio_set_rate(&gpio1->f0, i, S5P_GPIO_DRV_SLOW);
+		s5p_gpio_set_drv(&gpio1->f1, i, S5P_GPIO_DRV_4X);
+		s5p_gpio_set_rate(&gpio1->f1, i, S5P_GPIO_DRV_SLOW);
+		s5p_gpio_set_drv(&gpio1->f2, i, S5P_GPIO_DRV_4X);
+		s5p_gpio_set_rate(&gpio1->f0, i, S5P_GPIO_DRV_SLOW);
 	}
 
 	for (i = 0; i < f3_end; i++) {
 		/* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
-		s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2));
+		s5p_gpio_cfg_pin(&gpio1->f3, i, S5P_GPIO_FUNC(2));
 		/* pull-up/down disable */
-		s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE);
+		s5p_gpio_set_pull(&gpio1->f3, i, S5P_GPIO_PULL_NONE);
 		/* drive strength to max (24bit) */
-		s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X);
-		s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW);
+
+		s5p_gpio_set_rate(&gpio1->f3, i, S5P_GPIO_DRV_SLOW);
 	}
 
 	/* gpio pad configuration for LCD reset. */
-	s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT);
+	s5p_gpio_cfg_pin(&gpio2->y4, 5, S5P_GPIO_OUTPUT);
 
 	spi_init();
 }
drivers/gpio/s5p_gpio.c +10 -10
index c29a04a..b1b6fbe 100644
@@ -40,13 +40,13 @@ void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
 
 void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en)
 {
-	s5p_gpio_cfg_pin(bank, gpio, GPIO_OUTPUT);
+	s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_OUTPUT);
 	s5p_gpio_set_value(bank, gpio, en);
 }
 
 void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio)
 {
-	s5p_gpio_cfg_pin(bank, gpio, GPIO_INPUT);
+	s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_INPUT);
 }
 
 void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)

@@ -76,8 +76,8 @@ void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
 	value &= ~PULL_MASK(gpio);
 
 	switch (mode) {
-	case GPIO_PULL_DOWN:
-	case GPIO_PULL_UP:
+	case S5P_GPIO_PULL_DOWN:
+	case S5P_GPIO_PULL_UP:
 		value |= PULL_MODE(gpio, mode);
 		break;
 	default:

@@ -95,10 +95,10 @@ void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode)
 	value &= ~DRV_MASK(gpio);
 
 	switch (mode) {
-	case GPIO_DRV_1X:
-	case GPIO_DRV_2X:
-	case GPIO_DRV_3X:
-	case GPIO_DRV_4X:
+	case S5P_GPIO_DRV_1X:
+	case S5P_GPIO_DRV_2X:
+	case S5P_GPIO_DRV_3X:
+	case S5P_GPIO_DRV_4X:
 		value |= DRV_SET(gpio, mode);
 		break;
 	default:

@@ -116,8 +116,8 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
 	value &= ~RATE_MASK(gpio);
 
 	switch (mode) {
-	case GPIO_DRV_FAST:
-	case GPIO_DRV_SLOW:
+	case S5P_GPIO_DRV_FAST:
+	case S5P_GPIO_DRV_SLOW:
 		value |= RATE_SET(gpio);
 		break;
 	default:
Signature · 1 line
1.8.3.2
#10 lore raw

PATCH v6 2/4 S5P: Rename GPIO definitions

Quoted 7 lines · Akshay Saraswat

From: Rajeshwari Shinde <[email protected]>

This patch rename GPIO definitions from GPIO_... to S5P_GPIO_... This changes was done to enable cmd_gpio for EXYNOS and cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence getting a error during compilation.

Quoted 6 lines

Build tested for s5p_goni, origen, smdk5250, s5pc210_universal, trats, smdkc100, smdkv310 config files.

Signed-off-by Rajeshwari Shinde <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>
Acked-by Simon Glass <[email protected]>

Tested on snow with backlight GPIOs.

#11 lore raw

PATCH v6 2/4 S5P: Rename GPIO definitions

In reply to Akshay Saraswat

Hi,

Quoted 7 lines · Akshay Saraswat

From: Rajeshwari Shinde <[email protected]>

This patch rename GPIO definitions from GPIO_... to S5P_GPIO_... This changes was done to enable cmd_gpio for EXYNOS and cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence getting a error during compilation.

Quoted 5 lines

Build tested for s5p_goni, origen, smdk5250, s5pc210_universal, trats, smdkc100, smdkv310 config files.

Signed-off-by Rajeshwari Shinde <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>

Please check boards files: origen.c, trats.c and trats2.c, there is still old gpio naming style.

Thanks

Signature · 4 lines
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com
author
#12 lore raw

PATCH v6 3/4 EXYNOS5: GPIO: Support GPIO Command for EXYNOS5

In reply to Akshay Saraswat

From: Rajeshwari Shinde <[email protected]>

This patch adds support for name to gpio conversion in s5p_gpio to enable gpio command EXYNOS 5250 & 5420.
Function has been added to asm/gpio.h to decode the input gpio name to gpio number.

Example: SMDK5420 # gpio set gpa00

Signed-off-by Rajeshwari Shinde <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>
---
 arch/arm/include/asm/arch-exynos/gpio.h |  28 +++++++++
 drivers/gpio/s5p_gpio.c                 | 105 ++++++++++++++++++++++++++++++++
 2 files changed, 133 insertions(+)
arch/arm/include/asm/arch-exynos/gpio.h +28 -0
index 697e6f3..3736a22 100644
@@ -1038,6 +1038,34 @@ static inline unsigned int get_bank_num(void)
 	}
 }
 
+/*
+ * This structure helps mapping symbolic GPIO names into indices from
+ * exynos5_gpio_pin/exynos5420_gpio_pin enums.
+ *
+ * By convention, symbolic GPIO name is defined as follows:
+ *
+ * g[p]<bank><set><bit>, where
+ *   p is optional
+ *   <bank> - a single character bank name, as defined by the SOC
+ *   <set> - a single digit set number
+ *   <bit> - bit number within the set (in 0..7 range).
+ *
+ * <set><bit> essentially form an octal number of the GPIO pin within the bank
+ * space. On the 5420 architecture some banks' sets do not start not from zero
+ * ('d' starts from 1 and 'j' starts from 4). To compensate for that and
+ * maintain flat number space withoout holes, those banks use offsets to be
+ * deducted from the pin number.
+ */
+struct gpio_name_num_table {
+	char bank;		/* bank name symbol */
+	u8 bank_size;		/* total number of pins in the bank */
+	char bank_offset;	/* offset of the first bank's pin */
+	unsigned int base;	/* index of the first bank's pin in the enum */
+};
+
+int s5p_name_to_gpio(const char *name);
+#define name_to_gpio(n) s5p_name_to_gpio(n)
+
 void gpio_cfg_pin(int gpio, int cfg);
 void gpio_set_pull(int gpio, int mode);
 void gpio_set_drv(int gpio, int mode);
drivers/gpio/s5p_gpio.c +105 -0

111 lines not on this page · raw message

Signature · 1 line
1.8.3.2
#13 lore raw

PATCH v6 3/4 EXYNOS5: GPIO: Support GPIO Command for EXYNOS5

Quoted 7 lines · Akshay Saraswat

From: Rajeshwari Shinde <[email protected]>

This patch adds support for name to gpio conversion in s5p_gpio to enable gpio command EXYNOS 5250 & 5420.
Function has been added to asm/gpio.h to decode the input gpio name to gpio number.

Quoted 5 lines

Example: SMDK5420 # gpio set gpa00

Signed-off-by Rajeshwari Shinde <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>
Acked-by Simon Glass <[email protected]>

Tested on snow with backlight GPIOs.

#14 lore raw

PATCH v6 3/4 EXYNOS5: GPIO: Support GPIO Command for EXYNOS5

In reply to Akshay Saraswat

Hi,

Quoted 60 lines · Akshay Saraswat

From: Rajeshwari Shinde <[email protected]>

This patch adds support for name to gpio conversion in s5p_gpio to enable gpio command EXYNOS 5250 & 5420.
Function has been added to asm/gpio.h to decode the input gpio name to gpio number.

Example: SMDK5420 # gpio set gpa00

Signed-off-by Rajeshwari Shinde <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>
---
  arch/arm/include/asm/arch-exynos/gpio.h |  28 +++++++++
  drivers/gpio/s5p_gpio.c                 | 105 ++++++++++++++++++++++++++++++++
  2 files changed, 133 insertions(+)
arch/arm/include/asm/arch-exynos/gpio.h +28 -0
index 697e6f3..3736a22 100644
@@ -1038,6 +1038,34 @@ static inline unsigned int get_bank_num(void)
  	}
  }
 
+/*
+ * This structure helps mapping symbolic GPIO names into indices from
+ * exynos5_gpio_pin/exynos5420_gpio_pin enums.
+ *
+ * By convention, symbolic GPIO name is defined as follows:
+ *
+ * g[p]<bank><set><bit>, where
+ *   p is optional
+ *   <bank> - a single character bank name, as defined by the SOC
+ *   <set> - a single digit set number
+ *   <bit> - bit number within the set (in 0..7 range).
+ *
+ * <set><bit> essentially form an octal number of the GPIO pin within the bank
+ * space. On the 5420 architecture some banks' sets do not start not from zero
+ * ('d' starts from 1 and 'j' starts from 4). To compensate for that and
+ * maintain flat number space withoout holes, those banks use offsets to be
+ * deducted from the pin number.
+ */
+struct gpio_name_num_table {
+	char bank;		/* bank name symbol */
+	u8 bank_size;		/* total number of pins in the bank */
+	char bank_offset;	/* offset of the first bank's pin */
+	unsigned int base;	/* index of the first bank's pin in the enum */
+};
+
+int s5p_name_to_gpio(const char *name);
+#define name_to_gpio(n) s5p_name_to_gpio(n)
+
  void gpio_cfg_pin(int gpio, int cfg);
  void gpio_set_pull(int gpio, int mode);
  void gpio_set_drv(int gpio, int mode);
drivers/gpio/s5p_gpio.c +0 -0
index b1b6fbe..9a80b0c 100644

drivers/gpio/s5p_gpio.c line 30

Quoted 3 lines
drivers/gpio/s5p_gpio.c +0 -0
@@ -28,6 +28,111 @@
  #define RATE_MASK(x)		(0x1 << (x + 16))
  #define RATE_SET(x)		(0x1 << (x + 16))

This driver is common so you can't put here SOC specific code. This is also the reason of build break for s5pc1xx architecture.

It should be initialized in arch/arm/include/asm/arch-exynos/gpio.h. The same should be defined for Exynos4 and for s5pc1xx: in arch/arm/include/asm/arch-s5pc1xx/gpio.h.

This also can require introduce a s5p_gpio.h header with structure gpio_name_num_table. And maybe better name for this structure type is gpio_name_to_num ?

Quoted 48 lines
drivers/gpio/s5p_gpio.c +48 -0
+#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base }
+static const struct gpio_name_num_table exynos5_gpio_table[] = {
+	GPIO_ENTRY('a', EXYNOS5_GPIO_A00, EXYNOS5_GPIO_B00, 0),
+	GPIO_ENTRY('b', EXYNOS5_GPIO_B00, EXYNOS5_GPIO_C00, 0),
+	GPIO_ENTRY('c', EXYNOS5_GPIO_C00, EXYNOS5_GPIO_D00, 0),
+	GPIO_ENTRY('d', EXYNOS5_GPIO_D00, EXYNOS5_GPIO_Y00, 0),
+	GPIO_ENTRY('y', EXYNOS5_GPIO_Y00, EXYNOS5_GPIO_C40, 0),
+	GPIO_ENTRY('x', EXYNOS5_GPIO_X00, EXYNOS5_GPIO_E00, 0),
+	GPIO_ENTRY('e', EXYNOS5_GPIO_E00, EXYNOS5_GPIO_F00, 0),
+	GPIO_ENTRY('f', EXYNOS5_GPIO_F00, EXYNOS5_GPIO_G00, 0),
+	GPIO_ENTRY('g', EXYNOS5_GPIO_G00, EXYNOS5_GPIO_H00, 0),
+	GPIO_ENTRY('h', EXYNOS5_GPIO_H00, EXYNOS5_GPIO_V00, 0),
+	GPIO_ENTRY('v', EXYNOS5_GPIO_V00, EXYNOS5_GPIO_Z0, 0),
+	GPIO_ENTRY('z', EXYNOS5_GPIO_Z0, EXYNOS5_GPIO_MAX_PORT, 0),
+	{ 0 }
+};
+
+static const struct gpio_name_num_table exynos5420_gpio_table[] = {
+	GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0),
+	GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0),
+	GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Y70, 0),
+	GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0),
+	GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0),
+	GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 010),
+	GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0),
+	GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0),
+	GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0),
+	GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0),
+	GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_Z0, 040),
+	GPIO_ENTRY('z', EXYNOS5420_GPIO_Z0, EXYNOS5420_GPIO_MAX_PORT, 0),
+	{ 0 }
+};
+
+int s5p_name_to_gpio(const char *name)
+{
+	unsigned num, irregular_set_number, irregular_bank_base;
+	const struct gpio_name_num_table *tabp;
+	char this_bank, bank_name, irregular_bank_name;
+	char *endp;
+
+	/*
+	 * The gpio name starts with either 'g' ot 'gp' followed by the bank
+	 * name character. Skip one or two characters depending on the prefix.
+	 */
+	if (name[1] == 'p')
+		name += 2;
+	else
+		name++;

drivers/gpio/s5p_gpio.c line 88

Quoted 10 lines
drivers/gpio/s5p_gpio.c +10 -0
+	bank_name = *name++;
+	if (!*name)
+		return -1; /* At least one digit is required/expected. */
+
+	/*
+	 * On both exynos5 and exynos5420 architectures there is a bank of
+	 * GPIOs which does not fall into the regular address pattern. Those
+	 * banks are c4 on Exynos5 and y7 on Exynos5420. The rest of the below
+	 * assignments help to handle these irregularities.
+	 */

We can't check cpu id for s5pc1xx when exynos is compiled so you shouldn't check proid in this driver, but you can do this in arch-XXXX/gpio.h.
So then this is a still s5p common driver.

Quoted 41 lines
drivers/gpio/s5p_gpio.c +40 -0
+	if (proid_is_exynos5420()) {
+		tabp = exynos5420_gpio_table;
+		irregular_bank_name = 'y';
+		irregular_set_number = '7';
+		irregular_bank_base = EXYNOS5420_GPIO_Y70;
+	} else {
+		tabp = exynos5_gpio_table;
+		irregular_bank_name = 'c';
+		irregular_set_number = '4';
+		irregular_bank_base = EXYNOS5_GPIO_C40;
+	}
+
+	this_bank = tabp->bank;
+	do {
+		if (bank_name == this_bank) {
+			unsigned pin_index; /* pin number within the bank */
+			if ((bank_name == irregular_bank_name) &&
+			    (name[0] == irregular_set_number)) {
+				pin_index = name[1] - '0';
+				/* Irregular sets have 8 pins. */
+				if (pin_index >= GPIO_PER_BANK)
+					return -1;
+				num = irregular_bank_base + pin_index;
+			} else {
+				pin_index = simple_strtoul(name, &endp, 8);
+				pin_index -= tabp->bank_offset;
+				/*
+				 * Sanity check: bunk 'z' has no set number,
+				 * for all other banks there must be exactly
+				 * two octal digits, and the resulting number
+				 * should not exceed the number of pins in the
+				 * bank.
+				 */
+				if (((bank_name != 'z') && !name[1]) ||
+				    *endp ||
+				    (pin_index >= tabp->bank_size))
+					return -1;
+				num = tabp->base + pin_index;
+			}
+			return num;

drivers/gpio/s5p_gpio.c line 138

Quoted 10 lines
drivers/gpio/s5p_gpio.c +7 -0
+		}
+		this_bank = (++tabp)->bank;
+	} while (this_bank);
+
+	return -1;
+}
+
  void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
  {
  	unsigned int value;

You made a lot of good job. Please just make this driver more common, then I will implement and test this feature for exynos4 and s5pc1xx boards.

Thanks

Signature · 4 lines
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com
author
#15 lore raw

PATCH v6 4/4 Config: Exynos5: Enable Generic GPIO and CMD configs

In reply to Akshay Saraswat

From: Rajeshwari Shinde <[email protected]>

Enable configs for GPIO CMD and Generic GPIO.

Signed-off-by Rajeshwari Shinde <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>
---
 include/configs/exynos5-dt.h | 3 +++
 1 file changed, 3 insertions(+)
include/configs/exynos5-dt.h +3 -0
index 414db42..e81b5cd 100644
@@ -288,4 +288,7 @@
 
 #define CONFIG_CMD_BOOTZ
 
+#define HAVE_GENERIC_GPIO
+#define CONFIG_CMD_GPIO
+
 #endif	/* __CONFIG_H */
Signature · 1 line
1.8.3.2
#16 lore raw

PATCH v6 4/4 Config: Exynos5: Enable Generic GPIO and CMD configs

Quoted 7 lines · Akshay Saraswat

From: Rajeshwari Shinde <[email protected]>

Enable configs for GPIO CMD and Generic GPIO.

Signed-off-by Rajeshwari Shinde <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>
Acked-by Simon Glass <[email protected]>

Tested on snow with backlight GPIOs.

Quoted 9 lines
---
 include/configs/exynos5-dt.h | 3 +++
 1 file changed, 3 insertions(+)
include/configs/exynos5-dt.h +0 -0
index 414db42..e81b5cd 100644

include/configs/exynos5-dt.h line 292

Quoted 5 lines
include/configs/exynos5-dt.h +1 -0
@@ -288,4 +288,7 @@
 
 #define CONFIG_CMD_BOOTZ
 
+#define HAVE_GENERIC_GPIO

Will someone be implementing this for other Samsung SoCs?

Regards,
Simon

#17 lore raw

PATCH v6 4/4 Config: Exynos5: Enable Generic GPIO and CMD configs

Hi Akshay,

Quoted 6 lines · Simon Glass
Quoted 4 lines · Akshay Saraswat

From: Rajeshwari Shinde <[email protected]>

Enable configs for GPIO CMD and Generic GPIO.

Quoted 8 lines
Quoted 3 lines
Signed-off-by Rajeshwari Shinde <[email protected]>
Signed-off-by Akshay Saraswat <[email protected]>
Acked-by Simon Glass <[email protected]>

Tested on snow with backlight GPIOs.

One more question - it looks like Pit doesn't boot on ToT. It is missing a device tree file, but it seems to be more than that - have you had it working?

Regards,
Simon

#18 lore raw

v6 cover Exynos5: Add GPIO numbering feature

In reply to Akshay Saraswat

Hello Akshay,
I tried to test your patches but build breaks for trats2 and trats configs. You didn't change some old gpio code in those boards files. Please fix this.

Quoted 33 lines · Akshay Saraswat

From: Akshay Saraswat <[email protected]>

Changes in V2:
- Enabled CMD_GPIO as suggested by Simon Glass
and supported same for EXYNOS5.
Changes in V3:
- New patch added to rename S5P GPIO definitions to S5P_GPIO.
- GPIO Table added to calculate the base address of input gpio bank.
Changes in V4:
- To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them.
- Function and table to support gpio command moved to s5p-gpio driver.
- Rebased on latest u-boot-samsung tree.
Changes in V5:
- Rebased on latest u-boot-samsung tree.
- Removed Exynos5 specific code in gpio driver api to get bank.
- Added #define HAVE_GENERIC_GPIO in config file to remove conditinal CPU check in gpio driver.
Changes in V6:
- Isolated config changes in a new patch.
- Updated patches with corresponding changes for Exynos 5420.

Rajeshwari Shinde (4):
S5P: Rename GPIO definitions
EXYNOS5: Add gpio pin numbering feature
EXYNOS5: GPIO: Support GPIO Command for EXYNOS5
Config: Exynos5: Enable Generic GPIO and CMD configs

Quoted 16 lines
  arch/arm/cpu/armv7/exynos/pinmux.c       | 355 ++++++--------
  arch/arm/include/asm/arch-exynos/cpu.h   |  17 +-
  arch/arm/include/asm/arch-exynos/gpio.h  | 796 ++++++++++++++++++++++++++++++-
  arch/arm/include/asm/arch-s5pc1xx/gpio.h |  26 +-
  board/samsung/goni/goni.c                |   4 +-
  board/samsung/smdk5250/exynos5-dt.c      |  20 +-
  board/samsung/smdk5250/smdk5250.c        |  19 +-
  board/samsung/smdk5420/smdk5420.c        |  15 +-
  board/samsung/smdkc100/smdkc100.c        |   2 +-
  board/samsung/smdkv310/smdkv310.c        |  10 +-
  board/samsung/trats/trats.c              |   6 +-
  board/samsung/universal_c210/universal.c |  34 +-
  drivers/gpio/s5p_gpio.c                  | 169 ++++++-
  include/configs/exynos5-dt.h             |   3 +
  14 files changed, 1157 insertions(+), 319 deletions(-)

Thanks

Signature · 4 lines
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com