Skip to contentSkip to conversation

Enable RC6/Turbo on CHV

PATCH In review [email protected] 2 participants 4 messages Apr 21, 2014 – Apr 23, 2014

lore
Share & tools
lore

[email protected]

author
#0 lore raw

cover Enable RC6/Turbo on CHV

From: Deepak S <[email protected]>

Squashed some of the patches and created a new patch series.

ToDo: Address the comments on some the patches. Changes will be shared in next series.

Ben Widawsky (1):
drm/i915/bdw: Implement a basic PM interrupt handler

Deepak S (6):
drm/i915: Enable PM Interrupts target via Display Interface. drm/i915/chv: Enable Render Standby (RC6) for Cheeryview drm/i915/chv: Added CHV specific register read and write drm/i915/chv: Enable RPS (Turbo) for Cheeryview drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating drm/i915/chv: Freq(opcode) request value for CHV.

Ville Syrjälä (3):
drm/i915/chv: Streamline CHV forcewake stuff drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV

 drivers/gpu/drm/i915/i915_drv.h       |  10 ++
 drivers/gpu/drm/i915/i915_irq.c       |  79 +++++++++++-
 drivers/gpu/drm/i915/i915_reg.h       |  13 ++
 drivers/gpu/drm/i915/intel_drv.h      |   2 +
 drivers/gpu/drm/i915/intel_pm.c       | 231 +++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_sideband.c |  15 +++
 drivers/gpu/drm/i915/intel_uncore.c   | 126 +++++++++++++++++--
 7 files changed, 455 insertions(+), 21 deletions(-)
Signature · 6 lines
1.9.1

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
author
#1 lore raw

Hi Ville,

let me know if you want some of other small patches to be squashed.

Thanks
Deepak

Quoted 22 lines · On Monday 21 April 2014 01:23 PM, [email protected] wrote:

From: Deepak S <[email protected]>

Squashed some of the patches and created a new patch series.

ToDo: Address the comments on some the patches. Changes will be shared in next series.

Ben Widawsky (1):
drm/i915/bdw: Implement a basic PM interrupt handler

Deepak S (6):
drm/i915: Enable PM Interrupts target via Display Interface. drm/i915/chv: Enable Render Standby (RC6) for Cheeryview drm/i915/chv: Added CHV specific register read and write drm/i915/chv: Enable RPS (Turbo) for Cheeryview drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating drm/i915/chv: Freq(opcode) request value for CHV.

Ville Syrjälä (3):
drm/i915/chv: Streamline CHV forcewake stuff drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV

Quoted 9 lines
  drivers/gpu/drm/i915/i915_drv.h       |  10 ++
  drivers/gpu/drm/i915/i915_irq.c       |  79 +++++++++++-
  drivers/gpu/drm/i915/i915_reg.h       |  13 ++
  drivers/gpu/drm/i915/intel_drv.h      |   2 +
  drivers/gpu/drm/i915/intel_pm.c       | 231 +++++++++++++++++++++++++++++++++-
  drivers/gpu/drm/i915/intel_sideband.c |  15 +++
  drivers/gpu/drm/i915/intel_uncore.c   | 126 +++++++++++++++++--
  7 files changed, 455 insertions(+), 21 deletions(-)

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

#2 lore raw
Quoted 3 lines · Deepak S

Hi Ville,

let me know if you want some of other small patches to be squashed.

Quick aside: Something seems to have gone with git send-email thread - the patches aren't in-reply-to the cover letter. No idea how that happened though ...
-Daniel

Quoted 42 lines

Thanks
Deepak

Quoted 22 lines · On Monday 21 April 2014 01:23 PM, [email protected] wrote:

From: Deepak S <[email protected]>

Squashed some of the patches and created a new patch series.

ToDo: Address the comments on some the patches. Changes will be shared in next series.

Ben Widawsky (1):
drm/i915/bdw: Implement a basic PM interrupt handler

Deepak S (6):
drm/i915: Enable PM Interrupts target via Display Interface. drm/i915/chv: Enable Render Standby (RC6) for Cheeryview drm/i915/chv: Added CHV specific register read and write drm/i915/chv: Enable RPS (Turbo) for Cheeryview drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating drm/i915/chv: Freq(opcode) request value for CHV.

Ville Syrjälä (3):
drm/i915/chv: Streamline CHV forcewake stuff drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV

Quoted 9 lines
 drivers/gpu/drm/i915/i915_drv.h       |  10 ++
 drivers/gpu/drm/i915/i915_irq.c       |  79 +++++++++++-
 drivers/gpu/drm/i915/i915_reg.h       |  13 ++
 drivers/gpu/drm/i915/intel_drv.h      |   2 +
 drivers/gpu/drm/i915/intel_pm.c       | 231 +++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_sideband.c |  15 +++
 drivers/gpu/drm/i915/intel_uncore.c   | 126 +++++++++++++++++--
 7 files changed, 455 insertions(+), 21 deletions(-)

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Signature · 3 lines
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
author
#3 lore raw
Quoted 8 lines · Daniel Vetter
Quoted 3 lines · Deepak S

Hi Ville,

let me know if you want some of other small patches to be squashed.

Quick aside: Something seems to have gone with git send-email thread - the patches aren't in-reply-to the cover letter. No idea how that happened though ...
-Daniel

Not Sure :( I can resend the patches again

Quoted 40 lines
Quoted 40 lines

Thanks
Deepak

Quoted 22 lines · On Monday 21 April 2014 01:23 PM, [email protected] wrote:

From: Deepak S <[email protected]>

Squashed some of the patches and created a new patch series.

ToDo: Address the comments on some the patches. Changes will be shared in next series.

Ben Widawsky (1):
drm/i915/bdw: Implement a basic PM interrupt handler

Deepak S (6):
drm/i915: Enable PM Interrupts target via Display Interface. drm/i915/chv: Enable Render Standby (RC6) for Cheeryview drm/i915/chv: Added CHV specific register read and write drm/i915/chv: Enable RPS (Turbo) for Cheeryview drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating drm/i915/chv: Freq(opcode) request value for CHV.

Ville Syrjälä (3):
drm/i915/chv: Streamline CHV forcewake stuff drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV

Quoted 9 lines
  drivers/gpu/drm/i915/i915_drv.h       |  10 ++
  drivers/gpu/drm/i915/i915_irq.c       |  79 +++++++++++-
  drivers/gpu/drm/i915/i915_reg.h       |  13 ++
  drivers/gpu/drm/i915/intel_drv.h      |   2 +
  drivers/gpu/drm/i915/intel_pm.c       | 231 +++++++++++++++++++++++++++++++++-
  drivers/gpu/drm/i915/intel_sideband.c |  15 +++
  drivers/gpu/drm/i915/intel_uncore.c   | 126 +++++++++++++++++--
  7 files changed, 455 insertions(+), 21 deletions(-)

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx