ARM: orion5x: big step towards DT conversion

This commit extends the pinctrl mvebu logic with a new driver to cover Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281 variants of Orion5x, which are the three ones supported by the old style MPP code in arch/arm/mach-orion5x/.

Signed-off-by Thomas Petazzoni <[email protected]>

Cc Linus Walleij <[email protected]>

---
  .../bindings/pinctrl/marvell,orion-pinctrl.txt     |  91 +++++++
  drivers/pinctrl/mvebu/Kconfig                      |   4 +
  drivers/pinctrl/mvebu/Makefile                     |   1 +
  drivers/pinctrl/mvebu/pinctrl-orion.c              | 261 +++++++++++++++++++++
  4 files changed, 357 insertions(+)

create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt create mode 100644 drivers/pinctrl/mvebu/pinctrl-orion.c

Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt new file +91 -0

new file mode 100644
index 0000000..27570a3
@@ -0,0 +1,91 @@
+* Marvell Orion SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f5181l-pinctrl", "marvell,88f5182-pinctrl",
+              "marvell,88f5281-pinctrl"
+
+- reg: two register areas, the first one describing the first two
+  contiguous MPP registers, and the second one describing the single
+  final MPP register, separated from the previous one.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Orion 88f5181l
+
+name          pins     functions
+================================================================================
+mpp0          0        pcie(rstout), pci(req2), gpio
+mpp1          1        gpio, pci(gnt2)
+mpp2          2        gpio, pci(req3), pci-1(pme)
+mpp3          3        gpio, pci(gnt3)
+mpp4          4        gpio, pci(req4)
+mpp5          5        gpio, pci(gnt4)
+mpp6          6        gpio, pci(req5), pci-1(clk)
+mpp7          7        gpio, pci(gnt5), pci-1(clk)
+mpp8          8        gpio, ge(col)
+mpp9          9        gpio, ge(rxerr)
+mpp10         10       gpio, ge(crs)
+mpp11         11       gpio, ge(txerr)
+mpp12         12       gpio, ge(txd4)
+mpp13         13       gpio, ge(txd5)
+mpp14         14       gpio, ge(txd6)
+mpp15         15       gpio, ge(txd7)
+mpp16         16       ge(rxd4)
+mpp17         17       ge(rxd5)
+mpp18         18       ge(rxd6)
+mpp19         19       ge(rxd7)
+
+* Marvell Orion 88f5182
+
+name          pins     functions
+================================================================================
+mpp0          0        pcie(rstout), pci(req2), gpio
+mpp1          1        gpio, pci(gnt2)
+mpp2          2        gpio, pci(req3), pci-1(pme)
+mpp3          3        gpio, pci(gnt3)
+mpp4          4        gpio, pci(req4), bootnand(re), sata0(prsnt)
+mpp5          5        gpio, pci(gnt4), bootnand(we), sata1(prsnt)
+mpp6          6        gpio, pci(req5), nand(re0), sata0(act)
+mpp7          7        gpio, pci(gnt5), nand(we0), sata1(act)
+mpp8          8        gpio, ge(col)
+mpp9          9        gpio, ge(rxerr)
+mpp10         10       gpio, ge(crs)
+mpp11         11       gpio, ge(txerr)
+mpp12         12       gpio, ge(txd4), nand(re1), sata0(ledprsnt)
+mpp13         13       gpio, ge(txd5), nand(we1), sata1(ledprsnt)
+mpp14         14       gpio, ge(txd6), nand(re2), sata0(ledact)
+mpp15         15       gpio, ge(txd7), nand(we2), sata1(ledact)
+mpp16         16       uart1(rxd), ge(rxd4), gpio
+mpp17         17       uart1(txd), ge(rxd5), gpio
+mpp18         18       uart1(cts), ge(rxd6), gpio
+mpp19         19       uart1(rts), ge(rxd7), gpio
+
+* Marvell Orion 88f5281
+
+name          pins     functions
+================================================================================
+mpp0          0        pcie(rstout), pci(req2), gpio
+mpp1          1        gpio, pci(gnt2)
+mpp2          2        gpio, pci(req3), pci(pme)
+mpp3          3        gpio, pci(gnt3)
+mpp4          4        gpio, pci(req4), bootnand(re)
+mpp5          5        gpio, pci(gnt4), bootnand(we)
+mpp6          6        gpio, pci(req5), nand(re0)
+mpp7          7        gpio, pci(gnt5), nand(we0)
+mpp8          8        gpio, ge(col)
+mpp9          9        gpio, ge(rxerr)
+mpp10         10       gpio, ge(crs)
+mpp11         11       gpio, ge(txerr)
+mpp12         12       gpio, ge(txd4), nand(re1)
+mpp13         13       gpio, ge(txd5), nand(we1)
+mpp14         14       gpio, ge(txd6), nand(re2)
+mpp15         15       gpio, ge(txd7), nand(we2)
+mpp16         16       uart1(rxd), ge(rxd4)
+mpp17         17       uart1(txd), ge(rxd5)
+mpp18         18       uart1(cts), ge(rxd6)
+mpp19         19       uart1(rts), ge(rxd7)

drivers/pinctrl/mvebu/Kconfig +4 -0

index cc298fad..d6dd835 100644
@@ -30,4 +30,8 @@ config PINCTRL_ARMADA_XP
  	bool
  	select PINCTRL_MVEBU
 
+config PINCTRL_ORION
+	bool
+	select PINCTRL_MVEBU
+
  endif

drivers/pinctrl/mvebu/Makefile +1 -0

index bc1b9f1..a0818e9 100644
@@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
  obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o
  obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o
  obj-$(CONFIG_PINCTRL_ARMADA_XP)  += pinctrl-armada-xp.o
+obj-$(CONFIG_PINCTRL_ORION)  += pinctrl-orion.o

drivers/pinctrl/mvebu/pinctrl-orion.c new file +261 -0

new file mode 100644
index 0000000..dda1e72
@@ -0,0 +1,261 @@
+/*
+ * Marvell Orion pinctrl driver based on mvebu pinctrl core
+ *
+ * Author: Thomas Petazzoni <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The first 16 MPP pins on Orion are easy to handle: they are
+ * configured through 2 consecutive registers, located at the base
+ * address of the MPP device.
+ *
+ * However the last 4 MPP pins are handled by a register at offset
+ * 0x50 from the base address, so it is not consecutive with the first
+ * two registers.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+static void __iomem *mpp_base;
+static void __iomem *high_mpp_base;
+
+static int orion_mpp_ctrl_get(unsigned pid, unsigned long *config)
+{
+	unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
+
+	if (pid < 16) {
+		unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
+		*config = (readl(mpp_base + off) >> shift) & MVEBU_MPP_MASK;
+	}
+	else {
+		*config = (readl(high_mpp_base) >> shift) & MVEBU_MPP_MASK;
+	}
+
+	return 0;
+}
+
+static int orion_mpp_ctrl_set(unsigned pid, unsigned long config)
+{
+	unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
+
+	if (pid < 16) {
+		unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
+		u32 reg = readl(mpp_base + off) & ~(MVEBU_MPP_MASK << shift);
+		writel(reg | (config << shift), mpp_base + off);
+	}
+	else {
+		u32 reg = readl(high_mpp_base) & ~(MVEBU_MPP_MASK << shift);
+		writel(reg | (config << shift), high_mpp_base);
+	}
+
+	return 0;
+}
+
+#define V(f5181l, f5182, f5281) \
+	((f5181l << 0) | (f5182 << 1) | (f5281 << 2))
+
+enum orion_variant {
+	V_5181L = V(1, 0, 0),
+	V_5182  = V(0, 1, 0),
+	V_5281  = V(0, 0, 1),
+	V_ALL   = V(1, 1, 1),
+};
+
+static struct mvebu_mpp_mode orion_mpp_modes[] = {
+	MPP_MODE(0,
+		 MPP_VAR_FUNCTION(0x0, "pcie", "rstout",    V_ALL),
+		 MPP_VAR_FUNCTION(0x2, "pci", "req2",       V_ALL),
+		 MPP_VAR_FUNCTION(0x3, "gpio", NULL,        V_ALL)),
+	MPP_MODE(1,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x2, "pci", "gnt2",       V_ALL)),
+	MPP_MODE(2,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x2, "pci", "req3",       V_ALL),
+		 MPP_VAR_FUNCTION(0x3, "pci-1", "pme",      V_ALL)),
+	MPP_MODE(3,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x2, "pci", "gnt3",       V_ALL)),
+	MPP_MODE(4,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x2, "pci", "req4",       V_ALL),
+		 MPP_VAR_FUNCTION(0x4, "bootnand", "re",    V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x5, "sata0", "prsnt",    V_5182)),
+	MPP_MODE(5,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x2, "pci", "gnt4",       V_ALL),
+		 MPP_VAR_FUNCTION(0x4, "bootnand", "we",    V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x5, "sata1", "prsnt",    V_5182)),
+	MPP_MODE(6,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x2, "pci", "req5",       V_ALL),
+		 MPP_VAR_FUNCTION(0x4, "nand", "re0",       V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181L),
+		 MPP_VAR_FUNCTION(0x5, "sata0", "act",      V_5182)),
+	MPP_MODE(7,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x2, "pci", "gnt5",       V_ALL),
+		 MPP_VAR_FUNCTION(0x4, "nand", "we0",       V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181L),
+		 MPP_VAR_FUNCTION(0x5, "sata1", "act",      V_5182)),
+	MPP_MODE(8,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x1, "ge", "col",         V_ALL)),
+	MPP_MODE(9,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x1, "ge", "rxerr",       V_ALL)),
+	MPP_MODE(10,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x1, "ge", "crs",         V_ALL)),
+	MPP_MODE(11,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x1, "ge", "txerr",       V_ALL)),
+	MPP_MODE(12,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x1, "ge", "txd4",        V_ALL),
+		 MPP_VAR_FUNCTION(0x4, "nand", "re1",       V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x5, "sata0", "ledprsnt", V_5182)),
+	MPP_MODE(13,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x1, "ge", "txd5",        V_ALL),
+		 MPP_VAR_FUNCTION(0x4, "nand", "we1",       V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x5, "sata1", "ledprsnt", V_5182)),
+	MPP_MODE(14,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x1, "ge", "txd6",        V_ALL),
+		 MPP_VAR_FUNCTION(0x4, "nand", "re2",       V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x5, "sata0", "ledact",   V_5182)),
+	MPP_MODE(15,
+		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
+		 MPP_VAR_FUNCTION(0x1, "ge", "txd7",        V_ALL),
+		 MPP_VAR_FUNCTION(0x4, "nand", "we2",       V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x5, "sata1", "ledact",   V_5182)),
+	MPP_MODE(16,
+		 MPP_VAR_FUNCTION(0x0, "uart1", "rxd",      V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x1, "ge", "rxd4",        V_ALL),
+		 MPP_VAR_FUNCTION(0x5, "gpio", NULL,        V_5182)),
+	MPP_MODE(17,
+		 MPP_VAR_FUNCTION(0x0, "uart1", "txd",      V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x1, "ge", "rxd5",        V_ALL),
+		 MPP_VAR_FUNCTION(0x5, "gpio", NULL,        V_5182)),
+	MPP_MODE(18,
+		 MPP_VAR_FUNCTION(0x0, "uart1", "cts",      V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x1, "ge", "rxd6",        V_ALL),
+		 MPP_VAR_FUNCTION(0x5, "gpio", NULL,        V_5182)),
+	MPP_MODE(19,
+		 MPP_VAR_FUNCTION(0x0, "uart1", "rts",      V_5182 | V_5281),
+		 MPP_VAR_FUNCTION(0x1, "ge", "rxd7",        V_ALL),
+		 MPP_VAR_FUNCTION(0x5, "gpio", NULL,        V_5182)),
+};
+
+static struct mvebu_mpp_ctrl orion_mpp_controls[] = {
+	MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl),
+};
+
+static struct pinctrl_gpio_range mv88f5181l_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0, 0, 0, 16),
+};
+
+static struct pinctrl_gpio_range mv88f5182_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0, 0, 0, 19),
+};
+
+static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0, 0, 0, 16),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f5181l_info = {
+	.variant = V_5181L,
+	.controls = orion_mpp_controls,
+	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
+	.modes = orion_mpp_modes,
+	.nmodes = ARRAY_SIZE(orion_mpp_modes),
+	.gpioranges = mv88f5181l_gpio_ranges,
+	.ngpioranges = ARRAY_SIZE(mv88f5181l_gpio_ranges),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f5182_info = {
+	.variant = V_5182,
+	.controls = orion_mpp_controls,
+	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
+	.modes = orion_mpp_modes,
+	.nmodes = ARRAY_SIZE(orion_mpp_modes),
+	.gpioranges = mv88f5182_gpio_ranges,
+	.ngpioranges = ARRAY_SIZE(mv88f5182_gpio_ranges),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f5281_info = {
+	.variant = V_5281,
+	.controls = orion_mpp_controls,
+	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
+	.modes = orion_mpp_modes,
+	.nmodes = ARRAY_SIZE(orion_mpp_modes),
+	.gpioranges = mv88f5281_gpio_ranges,
+	.ngpioranges = ARRAY_SIZE(mv88f5281_gpio_ranges),
+};
+
+/*
+ * There are multiple variants of the Orion SoCs, but in terms of pin
+ * muxing, they are identical.
+ */
+static struct of_device_id orion_pinctrl_of_match[] = {
+	{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181l_info },
+	{ .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info },
+	{ .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info },
+	{ }
+};
+
+static int orion_pinctrl_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *match =
+		of_match_device(orion_pinctrl_of_match, &pdev->dev);
+	struct resource *res;
+
+	pdev->dev.platform_data = (void*)match->data;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	mpp_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(mpp_base))
+		return PTR_ERR(mpp_base);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	high_mpp_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(high_mpp_base))
+		return PTR_ERR(high_mpp_base);
+
+	return mvebu_pinctrl_probe(pdev);
+}
+
+static int orion_pinctrl_remove(struct platform_device *pdev)
+{
+	return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver orion_pinctrl_driver = {
+	.driver = {
+		.name = "orion-pinctrl",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(orion_pinctrl_of_match),
+	},
+	.probe = orion_pinctrl_probe,
+	.remove = orion_pinctrl_remove,
+};
+
+module_platform_driver(orion_pinctrl_driver);
+
+MODULE_AUTHOR("Thomas Petazzoni <[email protected]>");
+MODULE_DESCRIPTION("Marvell Orion pinctrl driver");
+MODULE_LICENSE("GPL v2");

This commit extends the pinctrl mvebu logic with a new driver to cover Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281 variants of Orion5x, which are the three ones supported by the old style MPP code in arch/arm/mach-orion5x/.

Signed-off-by Thomas Petazzoni <[email protected]>

Cc Linus Walleij <[email protected]>

Quoted 5 lines · Thomas Petazzoni

This commit extends the pinctrl mvebu logic with a new driver to cover Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281 variants of Orion5x, which are the three ones supported by the old style MPP code in arch/arm/mach-orion5x/.

Quoted 2 lines

Signed-off-by Thomas Petazzoni <[email protected]>

Cc Linus Walleij <[email protected]>

Nothing very controversial about this,

shall I just apply it or do you need it to be kept together with other stuff?

Dear Linus Walleij,

Quoted 8 lines · Linus Walleij

Quoted 5 lines · Thomas Petazzoni

This commit extends the pinctrl mvebu logic with a new driver to cover Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281 variants of Orion5x, which are the three ones supported by the old style MPP code in arch/arm/mach-orion5x/.

Quoted 4 lines

Quoted 2 lines

Signed-off-by Thomas Petazzoni <[email protected]>

Cc Linus Walleij <[email protected]>

Nothing very controversial about this,

Yeah, just a boring list of pins and functions :-)

Quoted 1 line

shall I just apply it or do you need it to be kept together with other stuff?

I'll let the mvebu maintainers answer this. Since there is no build dependency with the rest of the series, I guess it could go through your tree, but I leave the decision to the mvebu maintainers.

This commit extends the pinctrl mvebu logic with a new driver to cover Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281 variants of Orion5x, which are the three ones supported by the old style MPP code in arch/arm/mach-orion5x/.

Signed-off-by Thomas Petazzoni <[email protected]>

Cc Linus Walleij <[email protected]>

This commit adds a core clock driver for the Orion5x SoC, with support for the tclk, the CPU frequency and the DDR frequency. All the details about the Sample-At-Reset register were extracted from the U-Boot sources for Orion5x.

Note that Orion5x does not have gatable clocks, so this core clock driver is sufficient to support clocking on Orion5x platforms.

Signed-off-by Thomas Petazzoni <[email protected]>

Cc Mike Turquette <[email protected]>

---
  .../devicetree/bindings/clock/mvebu-core-clock.txt |   8 +
  drivers/clk/mvebu/Kconfig                          |   4 +
  drivers/clk/mvebu/Makefile                         |   1 +
  drivers/clk/mvebu/orion.c                          | 210 +++++++++++++++++++++
  4 files changed, 223 insertions(+)

create mode 100644 drivers/clk/mvebu/orion.c

Documentation/devicetree/bindings/clock/mvebu-core-clock.txt +8 -0

index 307a503..dc5ea5b 100644
@@ -29,6 +29,11 @@ The following is a list of provided IDs and clock names on Kirkwood and Dove:
   2 = l2clk  (L2 Cache clock derived from CPU0 clock)
   3 = ddrclk (DDR controller clock derived from CPU0 clock)
 
+The following is a list of provided IDs and clock names on Orion5x:
+ 0 = tclk   (Internal Bus clock)
+ 1 = cpuclk (CPU0 clock)
+ 2 = ddrclk (DDR controller clock derived from CPU0 clock)
+
  Required properties:
  - compatible : shall be one of the following:
  	"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks

@@ -38,6 +43,9 @@ Required properties:
  	"marvell,dove-core-clock" - for Dove SoC core clocks
  	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
  	"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
+	"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
+	"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
+	"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
  - reg : shall be the register address of the Sample-At-Reset (SAR) register
  - #clock-cells : from common clock binding; shall be set to 1
 

drivers/clk/mvebu/Kconfig +4 -0

index 693f7be..3b34dba 100644
@@ -34,3 +34,7 @@ config DOVE_CLK
  config KIRKWOOD_CLK
  	bool
  	select MVEBU_CLK_COMMON
+
+config ORION_CLK
+	bool
+	select MVEBU_CLK_COMMON

drivers/clk/mvebu/Makefile +1 -0

index 4c66162..a9a56fc 100644
@@ -8,3 +8,4 @@ obj-$(CONFIG_ARMADA_38X_CLK)	+= armada-38x.o
  obj-$(CONFIG_ARMADA_XP_CLK)	+= armada-xp.o
  obj-$(CONFIG_DOVE_CLK)		+= dove.o
  obj-$(CONFIG_KIRKWOOD_CLK)	+= kirkwood.o
+obj-$(CONFIG_ORION_CLK)		+= orion.o

drivers/clk/mvebu/orion.c new file +210 -0

new file mode 100644
index 0000000..fd12956
@@ -0,0 +1,210 @@
+/*
+ * Marvell Orion SoC clocks
+ *
+ * Copyright (C) 2014 Thomas Petazzoni
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = {
+	{ .id = 0, .name = "ddrclk", }
+};
+
+/*
+ * Orion 5182
+ */
+
+#define SAR_MV88F5182_TCLK_FREQ      8
+#define SAR_MV88F5182_TCLK_FREQ_MASK 0x3
+
+static u32 __init mv88f5182_get_tclk_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5182_TCLK_FREQ) &
+		SAR_MV88F5182_TCLK_FREQ_MASK;
+	if (opt == 1)
+		return 150000000;
+	else if (opt == 2)
+		return 166666667;
+	else
+		return 0;
+}
+
+#define SAR_MV88F5182_CPU_FREQ       4
+#define SAR_MV88F5182_CPU_FREQ_MASK  0xf
+
+static u32 __init mv88f5182_get_cpu_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) &
+		SAR_MV88F5182_CPU_FREQ_MASK;
+	if (opt == 0)
+		return 333333333;
+	else if (opt == 1 || opt == 2)
+		return 400000000;
+	else if (opt == 3)
+		return 500000000;
+	else
+		return 0;
+}
+
+static void __init mv88f5182_get_clk_ratio(void __iomem *sar, int id,
+					   int *mult, int *div)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) &
+		SAR_MV88F5182_CPU_FREQ_MASK;
+	if (opt == 0 || opt == 1) {
+		*mult = 1;
+		*div  = 2;
+	} else if (opt == 2 || opt == 3) {
+		*mult = 1;
+		*div  = 3;
+	} else {
+		*mult = 0;
+		*div  = 1;
+	}
+}
+
+static const struct coreclk_soc_desc mv88f5182_coreclks = {
+	.get_tclk_freq = mv88f5182_get_tclk_freq,
+	.get_cpu_freq = mv88f5182_get_cpu_freq,
+	.get_clk_ratio = mv88f5182_get_clk_ratio,
+	.ratios = orion_coreclk_ratios,
+	.num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
+};
+
+static void __init mv88f5182_clk_init(struct device_node *np)
+{
+	return mvebu_coreclk_setup(np, &mv88f5182_coreclks);
+}
+
+CLK_OF_DECLARE(mv88f5182_clk, "marvell,mv88f5182-core-clock", mv88f5182_clk_init);
+
+/*
+ * Orion 5281
+ */
+
+static u32 __init mv88f5281_get_tclk_freq(void __iomem *sar)
+{
+	/* On 5281, tclk is always 166 Mhz */
+	return 166666667;
+}
+
+#define SAR_MV88F5281_CPU_FREQ       4
+#define SAR_MV88F5281_CPU_FREQ_MASK  0xf
+
+static u32 __init mv88f5281_get_cpu_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) &
+		SAR_MV88F5281_CPU_FREQ_MASK;
+	if (opt == 1 || opt == 2)
+		return 400000000;
+	else if (opt == 3)
+		return 500000000;
+	else
+		return 0;
+}
+
+static void __init mv88f5281_get_clk_ratio(void __iomem *sar, int id,
+					   int *mult, int *div)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) &
+		SAR_MV88F5281_CPU_FREQ_MASK;
+	if (opt == 1) {
+		*mult = 1;
+		*div = 2;
+	} else if (opt == 2 || opt == 3) {
+		*mult = 1;
+		*div = 3;
+	} else {
+		*mult = 0;
+		*div = 1;
+	}
+}
+
+static const struct coreclk_soc_desc mv88f5281_coreclks = {
+	.get_tclk_freq = mv88f5281_get_tclk_freq,
+	.get_cpu_freq = mv88f5281_get_cpu_freq,
+	.get_clk_ratio = mv88f5281_get_clk_ratio,
+	.ratios = orion_coreclk_ratios,
+	.num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
+};
+
+static void __init mv88f5281_clk_init(struct device_node *np)
+{
+	return mvebu_coreclk_setup(np, &mv88f5281_coreclks);
+}
+
+CLK_OF_DECLARE(mv88f5281_clk, "marvell,mv88f5281-core-clock", mv88f5281_clk_init);
+
+/*
+ * Orion 6183
+ */
+
+#define SAR_MV88F6183_TCLK_FREQ      9
+#define SAR_MV88F6183_TCLK_FREQ_MASK 0x1
+
+static u32 __init mv88f6183_get_tclk_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F6183_TCLK_FREQ) &
+		SAR_MV88F6183_TCLK_FREQ_MASK;
+	if (opt == 0)
+		return 133333333;
+	else if (opt == 1)
+		return 166666667;
+	else
+		return 0;
+}
+
+#define SAR_MV88F6183_CPU_FREQ       1
+#define SAR_MV88F6183_CPU_FREQ_MASK  0x3f
+
+static u32 __init mv88f6183_get_cpu_freq(void __iomem *sar)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) &
+		SAR_MV88F6183_CPU_FREQ_MASK;
+	if (opt == 9)
+		return 333333333;
+	else if (opt == 17)
+		return 400000000;
+	else
+		return 0;
+}
+
+static void __init mv88f6183_get_clk_ratio(void __iomem *sar, int id,
+					   int *mult, int *div)
+{
+	u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) &
+		SAR_MV88F6183_CPU_FREQ_MASK;
+	if (opt == 9 || opt == 17) {
+		*mult = 1;
+		*div  = 2;
+	} else {
+		*mult = 0;
+		*div  = 1;
+	}
+}
+
+static const struct coreclk_soc_desc mv88f6183_coreclks = {
+	.get_tclk_freq = mv88f6183_get_tclk_freq,
+	.get_cpu_freq = mv88f6183_get_cpu_freq,
+	.get_clk_ratio = mv88f6183_get_clk_ratio,
+	.ratios = orion_coreclk_ratios,
+	.num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
+};
+
+
+static void __init mv88f6183_clk_init(struct device_node *np)
+{
+	return mvebu_coreclk_setup(np, &mv88f6183_coreclks);
+}
+
+CLK_OF_DECLARE(mv88f6183_clk, "marvell,mv88f6183-core-clock", mv88f6183_clk_init);

This commit adds a core clock driver for the Orion5x SoC, with support for the tclk, the CPU frequency and the DDR frequency. All the details about the Sample-At-Reset register were extracted from the U-Boot sources for Orion5x.

Note that Orion5x does not have gatable clocks, so this core clock driver is sufficient to support clocking on Orion5x platforms.

Signed-off-by Thomas Petazzoni <[email protected]>

Cc Mike Turquette <[email protected]>

---
 .../devicetree/bindings/clock/mvebu-core-clock.txt |   8 +
 drivers/clk/mvebu/Kconfig                          |   4 +
 drivers/clk/mvebu/Makefile                         |   1 +
 drivers/clk/mvebu/orion.c                          | 210 +++++++++++++++++++++
 4 files changed, 223 insertions(+)
 create mode 100644 drivers/clk/mvebu/orion.c

The mvebu-devbus driver currently only supports the Armada 370/XP family, but it can also cover the Orion5x family. However, the Orion5x family has a different organization of the register. Therefore, in preparation to the introduction of Orion5x support, we rename the Armada 370/XP specific definitions to have an ARMADA_ prefix.

Signed-off-by Thomas Petazzoni <[email protected]>

---
  drivers/memory/mvebu-devbus.c | 48 +++++++++++++++++++++----------------------
  1 file changed, 24 insertions(+), 24 deletions(-)

drivers/memory/mvebu-devbus.c +24 -24

index b59a17f..e66de7f 100644
@@ -30,19 +30,19 @@
  #include <linux/platform_device.h>
 
  /* Register definitions */
-#define DEV_WIDTH_BIT		30
-#define BADR_SKEW_BIT		28
-#define RD_HOLD_BIT		23
-#define ACC_NEXT_BIT		17
-#define RD_SETUP_BIT		12
-#define ACC_FIRST_BIT		6
+#define ARMADA_DEV_WIDTH_BIT		30
+#define ARMADA_BADR_SKEW_BIT		28
+#define ARMADA_RD_HOLD_BIT		23
+#define ARMADA_ACC_NEXT_BIT		17
+#define ARMADA_RD_SETUP_BIT		12
+#define ARMADA_ACC_FIRST_BIT		6
 
-#define SYNC_ENABLE_BIT		24
-#define WR_HIGH_BIT		16
-#define WR_LOW_BIT		8
+#define ARMADA_SYNC_ENABLE_BIT		24
+#define ARMADA_WR_HIGH_BIT		16
+#define ARMADA_WR_LOW_BIT		8
 
-#define READ_PARAM_OFFSET	0x0
-#define WRITE_PARAM_OFFSET	0x4
+#define ARMADA_READ_PARAM_OFFSET	0x0
+#define ARMADA_WRITE_PARAM_OFFSET	0x4
 
  struct devbus_read_params {
  	u32 bus_width;

@@ -178,31 +178,31 @@ static int devbus_set_timing_params(struct devbus *devbus,
  		return err;
 
  	/* Set read timings */
-	value = r.bus_width << DEV_WIDTH_BIT |
-		r.badr_skew << BADR_SKEW_BIT |
-		r.rd_hold   << RD_HOLD_BIT   |
-		r.acc_next  << ACC_NEXT_BIT  |
-		r.rd_setup  << RD_SETUP_BIT  |
-		r.acc_first << ACC_FIRST_BIT |
+	value = r.bus_width << ARMADA_DEV_WIDTH_BIT |
+		r.badr_skew << ARMADA_BADR_SKEW_BIT |
+		r.rd_hold   << ARMADA_RD_HOLD_BIT   |
+		r.acc_next  << ARMADA_ACC_NEXT_BIT  |
+		r.rd_setup  << ARMADA_RD_SETUP_BIT  |
+		r.acc_first << ARMADA_ACC_FIRST_BIT |
  		r.turn_off;
 
  	dev_dbg(devbus->dev, "read parameters register 0x%p = 0x%x\n",
-		devbus->base + READ_PARAM_OFFSET,
+		devbus->base + ARMADA_READ_PARAM_OFFSET,
  		value);
 
-	writel(value, devbus->base + READ_PARAM_OFFSET);
+	writel(value, devbus->base + ARMADA_READ_PARAM_OFFSET);
 
  	/* Set write timings */
-	value = w.sync_enable  << SYNC_ENABLE_BIT |
-		w.wr_low       << WR_LOW_BIT      |
-		w.wr_high      << WR_HIGH_BIT     |
+	value = w.sync_enable  << ARMADA_SYNC_ENABLE_BIT |
+		w.wr_low       << ARMADA_WR_LOW_BIT      |
+		w.wr_high      << ARMADA_WR_HIGH_BIT     |
  		w.ale_wr;
 
  	dev_dbg(devbus->dev, "write parameters register: 0x%p = 0x%x\n",
-		devbus->base + WRITE_PARAM_OFFSET,
+		devbus->base + ARMADA_WRITE_PARAM_OFFSET,
  		value);
 
-	writel(value, devbus->base + WRITE_PARAM_OFFSET);
+	writel(value, devbus->base + ARMADA_WRITE_PARAM_OFFSET);
 
  	return 0;
  }

The mvebu-devbus driver currently only supports the Armada 370/XP family, but it can also cover the Orion5x family. However, the Orion5x family has a different organization of the register. Therefore, in preparation to the introduction of Orion5x support, we rename the Armada 370/XP specific definitions to have an ARMADA_ prefix.

Signed-off-by Thomas Petazzoni <[email protected]>

---
 drivers/memory/mvebu-devbus.c | 48 +++++++++++++++++++++----------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

Quoted 6 lines · Thomas Petazzoni

The mvebu-devbus driver currently only supports the Armada 370/XP family, but it can also cover the Orion5x family. However, the Orion5x family has a different organization of the register. Therefore, in preparation to the introduction of Orion5x support, we rename the Armada 370/XP specific definitions to have an ARMADA_ prefix.

Quoted 4 lines

Signed-off-by Thomas Petazzoni <[email protected]>

---
 drivers/memory/mvebu-devbus.c | 48 +++++++++++++++++++++----------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

Patches 5 through 9 (devbus) applied to mvebu/drivers With Sebastian's Acks and a dep on mvebu/fixes.

Hi guys,

Quoted 12 lines · Jason Cooper

Quoted 10 lines · Thomas Petazzoni

The mvebu-devbus driver currently only supports the Armada 370/XP family, but it can also cover the Orion5x family. However, the Orion5x family has a different organization of the register. Therefore, in preparation to the introduction of Orion5x support, we rename the Armada 370/XP specific definitions to have an ARMADA_ prefix.

Signed-off-by Thomas Petazzoni <[email protected]>

---
 drivers/memory/mvebu-devbus.c | 48 +++++++++++++++++++++----------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

Quoted 3 lines

Patches 5 through 9 (devbus) applied to mvebu/drivers With Sebastian's Acks and a dep on mvebu/fixes.

Tested the branch (plus some -next fixes) on the AXP-GP. The NOR works perfectly fine.

Quoted 15 lines · Ezequiel Garcia

Hi guys,

Quoted 12 lines · Jason Cooper

Quoted 10 lines · Thomas Petazzoni

The mvebu-devbus driver currently only supports the Armada 370/XP family, but it can also cover the Orion5x family. However, the Orion5x family has a different organization of the register. Therefore, in preparation to the introduction of Orion5x support, we rename the Armada 370/XP specific definitions to have an ARMADA_ prefix.

Signed-off-by Thomas Petazzoni <[email protected]>

---
 drivers/memory/mvebu-devbus.c | 48 +++++++++++++++++++++----------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

Quoted 5 lines

Quoted 3 lines

Patches 5 through 9 (devbus) applied to mvebu/drivers With Sebastian's Acks and a dep on mvebu/fixes.

Tested the branch (plus some -next fixes) on the AXP-GP. The NOR works perfectly fine.

Which fixes?

Does this count as a Tested-by?

Quoted 16 lines · Jason Cooper

Quoted 15 lines · Ezequiel Garcia

Hi guys,

Quoted 12 lines · Jason Cooper

Quoted 10 lines · Thomas Petazzoni

The mvebu-devbus driver currently only supports the Armada 370/XP family, but it can also cover the Orion5x family. However, the Orion5x family has a different organization of the register. Therefore, in preparation to the introduction of Orion5x support, we rename the Armada 370/XP specific definitions to have an ARMADA_ prefix.

Signed-off-by Thomas Petazzoni <[email protected]>

---
 drivers/memory/mvebu-devbus.c | 48 +++++++++++++++++++++----------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

Quoted 8 lines

Quoted 5 lines

Quoted 3 lines

Patches 5 through 9 (devbus) applied to mvebu/drivers With Sebastian's Acks and a dep on mvebu/fixes.

Tested the branch (plus some -next fixes) on the AXP-GP. The NOR works perfectly fine.

Which fixes?

Gah, nevermind. I took the mvneta -netdev fixes, but the XP-GP wasn't affected. So, no fixes required.

Quoted 2 lines

Does this count as a Tested-by?

Sure: Tested-by: Ezequiel Garcia <[email protected]>

As noted by Sebastian Hesselbarth, the definitions in mvebu-devbus.c are not bit definition, but rather shift values, so a _SHIFT prefix would make more sense. This commit therefore replaces the *_BIT definitions by *_SHIFT definitions.

Signed-off-by Thomas Petazzoni <[email protected]>

---
  drivers/memory/mvebu-devbus.c | 36 ++++++++++++++++++------------------
  1 file changed, 18 insertions(+), 18 deletions(-)

drivers/memory/mvebu-devbus.c +18 -18

index e66de7f..0f196b3 100644
@@ -30,16 +30,16 @@
  #include <linux/platform_device.h>
 
  /* Register definitions */
-#define ARMADA_DEV_WIDTH_BIT		30
-#define ARMADA_BADR_SKEW_BIT		28
-#define ARMADA_RD_HOLD_BIT		23
-#define ARMADA_ACC_NEXT_BIT		17
-#define ARMADA_RD_SETUP_BIT		12
-#define ARMADA_ACC_FIRST_BIT		6
+#define ARMADA_DEV_WIDTH_SHIFT		30
+#define ARMADA_BADR_SKEW_SHIFT		28
+#define ARMADA_RD_HOLD_SHIFT		23
+#define ARMADA_ACC_NEXT_SHIFT		17
+#define ARMADA_RD_SETUP_SHIFT		12
+#define ARMADA_ACC_FIRST_SHIFT		6
 
-#define ARMADA_SYNC_ENABLE_BIT		24
-#define ARMADA_WR_HIGH_BIT		16
-#define ARMADA_WR_LOW_BIT		8
+#define ARMADA_SYNC_ENABLE_SHIFT	24
+#define ARMADA_WR_HIGH_SHIFT		16
+#define ARMADA_WR_LOW_SHIFT		8
 
  #define ARMADA_READ_PARAM_OFFSET	0x0
  #define ARMADA_WRITE_PARAM_OFFSET	0x4

@@ -178,12 +178,12 @@ static int devbus_set_timing_params(struct devbus *devbus,
  		return err;
 
  	/* Set read timings */
-	value = r.bus_width << ARMADA_DEV_WIDTH_BIT |
-		r.badr_skew << ARMADA_BADR_SKEW_BIT |
-		r.rd_hold   << ARMADA_RD_HOLD_BIT   |
-		r.acc_next  << ARMADA_ACC_NEXT_BIT  |
-		r.rd_setup  << ARMADA_RD_SETUP_BIT  |
-		r.acc_first << ARMADA_ACC_FIRST_BIT |
+	value = r.bus_width << ARMADA_DEV_WIDTH_SHIFT |
+		r.badr_skew << ARMADA_BADR_SKEW_SHIFT |
+		r.rd_hold   << ARMADA_RD_HOLD_SHIFT   |
+		r.acc_next  << ARMADA_ACC_NEXT_SHIFT  |
+		r.rd_setup  << ARMADA_RD_SETUP_SHIFT  |
+		r.acc_first << ARMADA_ACC_FIRST_SHIFT |
  		r.turn_off;
 
  	dev_dbg(devbus->dev, "read parameters register 0x%p = 0x%x\n",

@@ -193,9 +193,9 @@ static int devbus_set_timing_params(struct devbus *devbus,
  	writel(value, devbus->base + ARMADA_READ_PARAM_OFFSET);
 
  	/* Set write timings */
-	value = w.sync_enable  << ARMADA_SYNC_ENABLE_BIT |
-		w.wr_low       << ARMADA_WR_LOW_BIT      |
-		w.wr_high      << ARMADA_WR_HIGH_BIT     |
+	value = w.sync_enable  << ARMADA_SYNC_ENABLE_SHIFT |
+		w.wr_low       << ARMADA_WR_LOW_SHIFT      |
+		w.wr_high      << ARMADA_WR_HIGH_SHIFT     |
  		w.ale_wr;
 
  	dev_dbg(devbus->dev, "write parameters register: 0x%p = 0x%x\n",

The mvebu-devbus driver currently only supports the Armada 370/XP family, but it can also cover the Orion5x family. However, the Orion5x family has a different organization of the registers.

Therefore, in preparation to the introduction of Orion5x support, we separate into two functions the code that 1/ retrieves the timing parameters from the Device Tree and 2/ applies those timings parameters into the hardware registers.

Signed-off-by Thomas Petazzoni <[email protected]>

---
  drivers/memory/mvebu-devbus.c | 90 ++++++++++++++++++++++++-------------------
  1 file changed, 51 insertions(+), 39 deletions(-)

drivers/memory/mvebu-devbus.c +51 -39

index 0f196b3..5dc9c63 100644
@@ -89,19 +89,15 @@ static int get_timing_param_ps(struct devbus *devbus,
  	return 0;
  }
 
-static int devbus_set_timing_params(struct devbus *devbus,
-				    struct device_node *node)
+static int devbus_get_timing_params(struct devbus *devbus,
+				    struct device_node *node,
+				    struct devbus_read_params *r,
+				    struct devbus_write_params *w)
  {
-	struct devbus_read_params r;
-	struct devbus_write_params w;
-	u32 value;
  	int err;
 
-	dev_dbg(devbus->dev, "Setting timing parameter, tick is %lu ps\n",
-		devbus->tick_ps);
-
  	/* Get read timings */
-	err = of_property_read_u32(node, "devbus,bus-width", &r.bus_width);
+	err = of_property_read_u32(node, "devbus,bus-width", &r->bus_width);
  	if (err < 0) {
  		dev_err(devbus->dev,
  			"%s has no 'devbus,bus-width' property\n",

@@ -113,48 +109,48 @@ static int devbus_set_timing_params(struct devbus *devbus,
  	 * The bus width is encoded into the register as 0 for 8 bits,
  	 * and 1 for 16 bits, so we do the necessary conversion here.
  	 */
-	if (r.bus_width == 8)
-		r.bus_width = 0;
-	else if (r.bus_width == 16)
-		r.bus_width = 1;
+	if (r->bus_width == 8)
+		r->bus_width = 0;
+	else if (r->bus_width == 16)
+		r->bus_width = 1;
  	else {
-		dev_err(devbus->dev, "invalid bus width %d\n", r.bus_width);
+		dev_err(devbus->dev, "invalid bus width %d\n", r->bus_width);
  		return -EINVAL;
  	}
 
  	err = get_timing_param_ps(devbus, node, "devbus,badr-skew-ps",
-				 &r.badr_skew);
+				 &r->badr_skew);
  	if (err < 0)
  		return err;
 
  	err = get_timing_param_ps(devbus, node, "devbus,turn-off-ps",
-				 &r.turn_off);
+				 &r->turn_off);
  	if (err < 0)
  		return err;
 
  	err = get_timing_param_ps(devbus, node, "devbus,acc-first-ps",
-				 &r.acc_first);
+				 &r->acc_first);
  	if (err < 0)
  		return err;
 
  	err = get_timing_param_ps(devbus, node, "devbus,acc-next-ps",
-				 &r.acc_next);
+				 &r->acc_next);
  	if (err < 0)
  		return err;
 
  	err = get_timing_param_ps(devbus, node, "devbus,rd-setup-ps",
-				 &r.rd_setup);
+				 &r->rd_setup);
  	if (err < 0)
  		return err;
 
  	err = get_timing_param_ps(devbus, node, "devbus,rd-hold-ps",
-				 &r.rd_hold);
+				 &r->rd_hold);
  	if (err < 0)
  		return err;
 
  	/* Get write timings */
  	err = of_property_read_u32(node, "devbus,sync-enable",
-				  &w.sync_enable);
+				  &w->sync_enable);
  	if (err < 0) {
  		dev_err(devbus->dev,
  			"%s has no 'devbus,sync-enable' property\n",

@@ -163,28 +159,38 @@ static int devbus_set_timing_params(struct devbus *devbus,
  	}
 
  	err = get_timing_param_ps(devbus, node, "devbus,ale-wr-ps",
-				 &w.ale_wr);
+				 &w->ale_wr);
  	if (err < 0)
  		return err;
 
  	err = get_timing_param_ps(devbus, node, "devbus,wr-low-ps",
-				 &w.wr_low);
+				 &w->wr_low);
  	if (err < 0)
  		return err;
 
  	err = get_timing_param_ps(devbus, node, "devbus,wr-high-ps",
-				 &w.wr_high);
+				 &w->wr_high);
  	if (err < 0)
  		return err;
 
+	return 0;
+}
+
+static void devbus_armada_set_timing_params(struct devbus *devbus,
+					   struct device_node *node,
+					   struct devbus_read_params *r,
+					   struct devbus_write_params *w)
+{
+	u32 value;
+
  	/* Set read timings */
-	value = r.bus_width << ARMADA_DEV_WIDTH_SHIFT |
-		r.badr_skew << ARMADA_BADR_SKEW_SHIFT |
-		r.rd_hold   << ARMADA_RD_HOLD_SHIFT   |
-		r.acc_next  << ARMADA_ACC_NEXT_SHIFT  |
-		r.rd_setup  << ARMADA_RD_SETUP_SHIFT  |
-		r.acc_first << ARMADA_ACC_FIRST_SHIFT |
-		r.turn_off;
+	value = r->bus_width << ARMADA_DEV_WIDTH_SHIFT |
+		r->badr_skew << ARMADA_BADR_SKEW_SHIFT |
+		r->rd_hold   << ARMADA_RD_HOLD_SHIFT   |
+		r->acc_next  << ARMADA_ACC_NEXT_SHIFT  |
+		r->rd_setup  << ARMADA_RD_SETUP_SHIFT  |
+		r->acc_first << ARMADA_ACC_FIRST_SHIFT |
+		r->turn_off;
 
  	dev_dbg(devbus->dev, "read parameters register 0x%p = 0x%x\n",
  		devbus->base + ARMADA_READ_PARAM_OFFSET,

@@ -193,24 +199,24 @@ static int devbus_set_timing_params(struct devbus *devbus,
  	writel(value, devbus->base + ARMADA_READ_PARAM_OFFSET);
 
  	/* Set write timings */
-	value = w.sync_enable  << ARMADA_SYNC_ENABLE_SHIFT |
-		w.wr_low       << ARMADA_WR_LOW_SHIFT      |
-		w.wr_high      << ARMADA_WR_HIGH_SHIFT     |
-		w.ale_wr;
+	value = w->sync_enable  << ARMADA_SYNC_ENABLE_SHIFT |
+		w->wr_low       << ARMADA_WR_LOW_SHIFT      |
+		w->wr_high      << ARMADA_WR_HIGH_SHIFT     |
+		w->ale_wr;
 
  	dev_dbg(devbus->dev, "write parameters register: 0x%p = 0x%x\n",
  		devbus->base + ARMADA_WRITE_PARAM_OFFSET,
  		value);
 
  	writel(value, devbus->base + ARMADA_WRITE_PARAM_OFFSET);
-
-	return 0;
  }
 
  static int mvebu_devbus_probe(struct platform_device *pdev)
  {
  	struct device *dev = &pdev->dev;
  	struct device_node *node = pdev->dev.of_node;
+	struct devbus_read_params r;
+	struct devbus_write_params w;
  	struct devbus *devbus;
  	struct resource *res;
  	struct clk *clk;

@@ -240,11 +246,17 @@ static int mvebu_devbus_probe(struct platform_device *pdev)
  	rate = clk_get_rate(clk) / 1000;
  	devbus->tick_ps = 1000000000 / rate;
 
-	/* Read the device tree node and set the new timing parameters */
-	err = devbus_set_timing_params(devbus, node);
+	dev_dbg(devbus->dev, "Setting timing parameter, tick is %lu ps\n",
+		devbus->tick_ps);
+
+	/* Read the Device Tree node */
+	err = devbus_get_timing_params(devbus, node, &r, &w);
  	if (err < 0)
  		return err;
 
+	/* Set the new timing parameters */
+	devbus_armada_set_timing_params(devbus, node, &r, &w);
+
  	/*
  	 * We need to create a child device explicitly from here to
  	 * guarantee that the child will be probed after the timing

This commit adds support for the Orion5x family of Marvell processors into the mvebu-devbus driver. It differs from the already supported Armada 370/XP by:

* Having a single register (instead of two) for doing all the timing configuration.

* Having a few less timing configuration parameters.

For this reason, a separate compatible string "marvell,orion-devbus" is introduced.

Signed-off-by Thomas Petazzoni <[email protected]>

---
  .../bindings/memory-controllers/mvebu-devbus.txt   |  25 ++++-
  drivers/memory/mvebu-devbus.c                      | 107 +++++++++++++++++----
  2 files changed, 106 insertions(+), 26 deletions(-)

Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt +20 -5

index 653c90c..55adde2 100644
@@ -6,10 +6,11 @@ The actual devices are instantiated from the child nodes of a Device Bus node.
 
  Required properties:
 
- - compatible:          Currently only Armada 370/XP SoC are supported,
-                        with this compatible string:
+ - compatible:          Armada 370/XP SoC are supported using the
+                        "marvell,mvebu-devbus" compatible string.
 
-                        marvell,mvebu-devbus
+                        Orion5x SoC are supported using the
+                        "marvell,orion-devbus" compatible string.
 
   - reg:                 A resource specifier for the register space.
                          This is the base address of a chip select within

@@ -22,7 +23,7 @@ Required properties:
                          integer values for each chip-select line in use:
                          0 <physical address of mapping> <size>
 
-Mandatory timing properties for child nodes:
+Timing properties for child nodes:
 
  Read parameters:
 

@@ -30,21 +31,26 @@ Read parameters:
                          drive the AD bus after the completion of a device read.
                          This prevents contentions on the Device Bus after a read
                          cycle from a slow device.
+                        Mandatory.
 
- - devbus,bus-width:    Defines the bus width (e.g. <16>)
+ - devbus,bus-width:    Defines the bus width, in bits (e.g. <16>).
+                        Mandatory.
 
   - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
                          to read data sample. This parameter is useful for
                          synchronous pipelined devices, where the address
                          precedes the read data by one or two cycles.
+                        Mandatory.
 
   - devbus,acc-first-ps: Defines the time delay from the negation of
                          ALE[0] to the cycle that the first read data is sampled
                          by the controller.
+                        Mandatory.
 
   - devbus,acc-next-ps:  Defines the time delay between the cycle that
                          samples data N and the cycle that samples data N+1
                          (in burst accesses).
+                        Mandatory.
 
   - devbus,rd-setup-ps:  Defines the time delay between DEV_CSn assertion to
  			DEV_OEn assertion. If set to 0 (default),

@@ -52,6 +58,8 @@ Read parameters:
                          This parameter has no affect on <acc-first-ps> parameter
                          (no affect on first data sample). Set <rd-setup-ps>
                          to a value smaller than <acc-first-ps>.
+                        Mandatory for "marvell,mvebu-devbus"
+                        compatible string, ignored otherwise.
 
   - devbus,rd-hold-ps:   Defines the time between the last data sample to the
  			de-assertion of DEV_CSn. If set to 0 (default),

@@ -62,16 +70,20 @@ Read parameters:
                          last data sampled. Also this parameter has no
                          affect on <turn-off-ps> parameter.
                          Set <rd-hold-ps> to a value smaller than <turn-off-ps>.
+                        Mandatory for "marvell,mvebu-devbus"
+                        compatible string, ignored otherwise.
 
  Write parameters:
 
   - devbus,ale-wr-ps:    Defines the time delay from the ALE[0] negation cycle
  			to the DEV_WEn assertion.
+                        Mandatory.
 
   - devbus,wr-low-ps:    Defines the time during which DEV_WEn is active.
                          A[2:0] and Data are kept valid as long as DEV_WEn
                          is active. This parameter defines the setup time of
                          address and data to DEV_WEn rise.
+                        Mandatory.
 
   - devbus,wr-high-ps:   Defines the time during which DEV_WEn is kept
                          inactive (high) between data beats of a burst write.

@@ -79,10 +91,13 @@ Write parameters:
                          <wr-high-ps> - <tick> ps.
  			This parameter defines the hold time of address and
  			data after DEV_WEn rise.
+                        Mandatory.
 
   - devbus,sync-enable: Synchronous device enable.
                         1: True
                         0: False
+                       Mandatory for "marvell,mvebu-devbus" compatible
+                       string, ignored otherwise.
 
  An example for an Armada XP GP board, with a 16 MiB NOR device as child
  is showed below. Note that the Device Bus driver is in charge of allocating

drivers/memory/mvebu-devbus.c +86 -21

index 5dc9c63..c8f3dad 100644
@@ -2,7 +2,7 @@
   * Marvell EBU SoC Device Bus Controller
   * (memory controller for NOR/NAND/SRAM/FPGA devices)
   *
- * Copyright (C) 2013 Marvell
+ * Copyright (C) 2013-2014 Marvell
   *
   * This program is free software: you can redistribute it and/or modify
   * it under the terms of the GNU General Public License as published by

@@ -44,6 +44,34 @@
  #define ARMADA_READ_PARAM_OFFSET	0x0
  #define ARMADA_WRITE_PARAM_OFFSET	0x4
 
+#define ORION_RESERVED			(0x2 << 30)
+#define ORION_BADR_SKEW_SHIFT		28
+#define ORION_WR_HIGH_EXT_BIT		BIT(27)
+#define ORION_WR_HIGH_EXT_MASK		0x8
+#define ORION_WR_LOW_EXT_BIT		BIT(26)
+#define ORION_WR_LOW_EXT_MASK		0x8
+#define ORION_ALE_WR_EXT_BIT		BIT(25)
+#define ORION_ALE_WR_EXT_MASK		0x8
+#define ORION_ACC_NEXT_EXT_BIT		BIT(24)
+#define ORION_ACC_NEXT_EXT_MASK		0x10
+#define ORION_ACC_FIRST_EXT_BIT		BIT(23)
+#define ORION_ACC_FIRST_EXT_MASK	0x10
+#define ORION_TURN_OFF_EXT_BIT		BIT(22)
+#define ORION_TURN_OFF_EXT_MASK		0x8
+#define ORION_DEV_WIDTH_SHIFT		20
+#define ORION_WR_HIGH_SHIFT		17
+#define ORION_WR_HIGH_MASK		0x7
+#define ORION_WR_LOW_SHIFT		14
+#define ORION_WR_LOW_MASK		0x7
+#define ORION_ALE_WR_SHIFT		11
+#define ORION_ALE_WR_MASK		0x7
+#define ORION_ACC_NEXT_SHIFT		7
+#define ORION_ACC_NEXT_MASK		0xF
+#define ORION_ACC_FIRST_SHIFT		3
+#define ORION_ACC_FIRST_MASK		0xF
+#define ORION_TURN_OFF_SHIFT		0
+#define ORION_TURN_OFF_MASK		0x7
+
  struct devbus_read_params {
  	u32 bus_width;
  	u32 badr_skew;

@@ -96,7 +124,6 @@ static int devbus_get_timing_params(struct devbus *devbus,
  {
  	int err;
 
-	/* Get read timings */
  	err = of_property_read_u32(node, "devbus,bus-width", &r->bus_width);
  	if (err < 0) {
  		dev_err(devbus->dev,

@@ -138,24 +165,25 @@ static int devbus_get_timing_params(struct devbus *devbus,
  	if (err < 0)
  		return err;
 
-	err = get_timing_param_ps(devbus, node, "devbus,rd-setup-ps",
-				 &r->rd_setup);
-	if (err < 0)
-		return err;
-
-	err = get_timing_param_ps(devbus, node, "devbus,rd-hold-ps",
-				 &r->rd_hold);
-	if (err < 0)
-		return err;
-
-	/* Get write timings */
-	err = of_property_read_u32(node, "devbus,sync-enable",
-				  &w->sync_enable);
-	if (err < 0) {
-		dev_err(devbus->dev,
-			"%s has no 'devbus,sync-enable' property\n",
-			node->full_name);
-		return err;
+	if (of_device_is_compatible(devbus->dev->of_node, "marvell,mvebu-devbus")) {
+		err = get_timing_param_ps(devbus, node, "devbus,rd-setup-ps",
+					  &r->rd_setup);
+		if (err < 0)
+			return err;
+
+		err = get_timing_param_ps(devbus, node, "devbus,rd-hold-ps",
+					  &r->rd_hold);
+		if (err < 0)
+			return err;
+
+		err = of_property_read_u32(node, "devbus,sync-enable",
+					   &w->sync_enable);
+		if (err < 0) {
+			dev_err(devbus->dev,
+				"%s has no 'devbus,sync-enable' property\n",
+				node->full_name);
+			return err;
+		}
  	}
 
  	err = get_timing_param_ps(devbus, node, "devbus,ale-wr-ps",

@@ -176,6 +204,39 @@ static int devbus_get_timing_params(struct devbus *devbus,
  	return 0;
  }
 
+static void devbus_orion_set_timing_params(struct devbus *devbus,
+					  struct device_node *node,
+					  struct devbus_read_params *r,
+					  struct devbus_write_params *w)
+{
+	u32 value;
+
+	/*
+	 * The hardware designers found it would be a good idea to
+	 * split most of the values in the register into two fields:
+	 * one containing all the low-order bits, and another one
+	 * containing just the high-order bit. For all of those
+	 * fields, we have to split the value into these two parts.
+	 */
+	value =	(r->turn_off   & ORION_TURN_OFF_MASK)  << ORION_TURN_OFF_SHIFT  |
+		(r->acc_first  & ORION_ACC_FIRST_MASK) << ORION_ACC_FIRST_SHIFT |
+		(r->acc_next   & ORION_ACC_NEXT_MASK)  << ORION_ACC_NEXT_SHIFT  |
+		(w->ale_wr     & ORION_ALE_WR_MASK)    << ORION_ALE_WR_SHIFT    |
+		(w->wr_low     & ORION_WR_LOW_MASK)    << ORION_WR_LOW_SHIFT    |
+		(w->wr_high    & ORION_WR_HIGH_MASK)   << ORION_WR_HIGH_SHIFT   |
+		r->bus_width                           << ORION_DEV_WIDTH_SHIFT |
+		((r->turn_off  & ORION_TURN_OFF_EXT_MASK)  ? ORION_TURN_OFF_EXT_BIT  : 0) |
+		((r->acc_first & ORION_ACC_FIRST_EXT_MASK) ? ORION_ACC_FIRST_EXT_BIT : 0) |
+		((r->acc_next  & ORION_ACC_NEXT_EXT_MASK)  ? ORION_ACC_NEXT_EXT_BIT  : 0) |
+		((w->ale_wr    & ORION_ALE_WR_EXT_MASK)    ? ORION_ALE_WR_EXT_BIT    : 0) |
+		((w->wr_low    & ORION_WR_LOW_EXT_MASK)    ? ORION_WR_LOW_EXT_BIT    : 0) |
+		((w->wr_high   & ORION_WR_HIGH_EXT_MASK)   ? ORION_WR_HIGH_EXT_BIT   : 0) |
+		(r->badr_skew << ORION_BADR_SKEW_SHIFT) |
+		ORION_RESERVED;
+
+	writel(value, devbus->base);
+}
+
  static void devbus_armada_set_timing_params(struct devbus *devbus,
  					   struct device_node *node,
  					   struct devbus_read_params *r,

@@ -255,7 +316,10 @@ static int mvebu_devbus_probe(struct platform_device *pdev)
  		return err;
 
  	/* Set the new timing parameters */
-	devbus_armada_set_timing_params(devbus, node, &r, &w);
+	if (of_device_is_compatible(node, "marvell,orion-devbus"))
+		devbus_orion_set_timing_params(devbus, node, &r, &w);
+	else
+		devbus_armada_set_timing_params(devbus, node, &r, &w);
 
  	/*
  	 * We need to create a child device explicitly from here to

@@ -271,6 +335,7 @@ static int mvebu_devbus_probe(struct platform_device *pdev)
 
  static const struct of_device_id mvebu_devbus_of_match[] = {
  	{ .compatible = "marvell,mvebu-devbus" },
+	{ .compatible = "marvell,orion-devbus" },
  	{},
  };
  MODULE_DEVICE_TABLE(of, mvebu_devbus_of_match);

Currently, the mvebu-devbus Device Tree binding makes defining the timing parameters mandatory.

However, in practice, when converting Orion5x platforms to the Device Tree, we may not necessarily have easy access to the hardware platforms to fetch those values which were not defined in old-style board files: all these platforms rely on the bootloader setting the timing parameters correctly.

In order to facilitate the migration to the Device Tree of this platform, this commit relaxes the mvebu-devbus Device Tree binding by introducing a 'devbus,keep-config' boolean property, which, if defined, will ignore all timing parameters passed in the Device Tree, and simply rely on the timing values already defined by the bootloader.

Signed-off-by Thomas Petazzoni <[email protected]>

---
  .../bindings/memory-controllers/mvebu-devbus.txt   | 29 ++++++++++++++--------
  drivers/memory/mvebu-devbus.c                      | 20 ++++++++-------
  2 files changed, 29 insertions(+), 20 deletions(-)

Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt +18 -11

index 55adde2..1ee3bc0 100644
@@ -23,6 +23,13 @@ Required properties:
                          integer values for each chip-select line in use:
                          0 <physical address of mapping> <size>
 
+Optional properties:
+
+ - devbus,keep-config   This property can optionally be used to keep
+                        using the timing parameters set by the
+                        bootloader. It makes all the timing properties
+                        described below unused.
+
  Timing properties for child nodes:
 
  Read parameters:

@@ -31,26 +38,26 @@ Read parameters:
                          drive the AD bus after the completion of a device read.
                          This prevents contentions on the Device Bus after a read
                          cycle from a slow device.
-                        Mandatory.
+                        Mandatory, except if devbus,keep-config is used.
 
   - devbus,bus-width:    Defines the bus width, in bits (e.g. <16>).
-                        Mandatory.
+                        Mandatory, except if devbus,keep-config is used.
 
   - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
                          to read data sample. This parameter is useful for
                          synchronous pipelined devices, where the address
                          precedes the read data by one or two cycles.
-                        Mandatory.
+                        Mandatory, except if devbus,keep-config is used.
 
   - devbus,acc-first-ps: Defines the time delay from the negation of
                          ALE[0] to the cycle that the first read data is sampled
                          by the controller.
-                        Mandatory.
+                        Mandatory, except if devbus,keep-config is used.
 
   - devbus,acc-next-ps:  Defines the time delay between the cycle that
                          samples data N and the cycle that samples data N+1
                          (in burst accesses).
-                        Mandatory.
+                        Mandatory, except if devbus,keep-config is used.
 
   - devbus,rd-setup-ps:  Defines the time delay between DEV_CSn assertion to
  			DEV_OEn assertion. If set to 0 (default),

@@ -58,8 +65,8 @@ Read parameters:
                          This parameter has no affect on <acc-first-ps> parameter
                          (no affect on first data sample). Set <rd-setup-ps>
                          to a value smaller than <acc-first-ps>.
-                        Mandatory for "marvell,mvebu-devbus"
-                        compatible string, ignored otherwise.
+                        Mandatory for "marvell,mvebu-devbus" compatible string,
+                        except if devbus,keep-config is used.
 
   - devbus,rd-hold-ps:   Defines the time between the last data sample to the
  			de-assertion of DEV_CSn. If set to 0 (default),

@@ -70,8 +77,8 @@ Read parameters:
                          last data sampled. Also this parameter has no
                          affect on <turn-off-ps> parameter.
                          Set <rd-hold-ps> to a value smaller than <turn-off-ps>.
-                        Mandatory for "marvell,mvebu-devbus"
-                        compatible string, ignored otherwise.
+                        Mandatory for "marvell,mvebu-devbus" compatible string,
+                        except if devbus,keep-config is used.
 
  Write parameters:
 

@@ -96,8 +103,8 @@ Write parameters:
   - devbus,sync-enable: Synchronous device enable.
                         1: True
                         0: False
-                       Mandatory for "marvell,mvebu-devbus" compatible
-                       string, ignored otherwise.
+                       Mandatory for "marvell,mvebu-devbus" compatible string,
+                       except if devbus,keep-config is used.
 
  An example for an Armada XP GP board, with a 16 MiB NOR device as child
  is showed below. Note that the Device Bus driver is in charge of allocating

drivers/memory/mvebu-devbus.c +11 -9

index c8f3dad..ff7138f 100644
@@ -310,16 +310,18 @@ static int mvebu_devbus_probe(struct platform_device *pdev)
  	dev_dbg(devbus->dev, "Setting timing parameter, tick is %lu ps\n",
  		devbus->tick_ps);
 
-	/* Read the Device Tree node */
-	err = devbus_get_timing_params(devbus, node, &r, &w);
-	if (err < 0)
-		return err;
+	if (!of_property_read_bool(node, "devbus,keep-config")) {
+		/* Read the Device Tree node */
+		err = devbus_get_timing_params(devbus, node, &r, &w);
+		if (err < 0)
+			return err;
 
-	/* Set the new timing parameters */
-	if (of_device_is_compatible(node, "marvell,orion-devbus"))
-		devbus_orion_set_timing_params(devbus, node, &r, &w);
-	else
-		devbus_armada_set_timing_params(devbus, node, &r, &w);
+		/* Set the new timing parameters */
+		if (of_device_is_compatible(node, "marvell,orion-devbus"))
+			devbus_orion_set_timing_params(devbus, node, &r, &w);
+		else
+			devbus_armada_set_timing_params(devbus, node, &r, &w);
+	}
 
  	/*
  	 * We need to create a child device explicitly from here to

This commit switches the Orion5x Device Tree files to use the DT representation and probing for the mvebu-mbus driver. The changes are mainly:

* Re-organize the DT to follow the same organization as the one used on Armada 370/XP, which is needed for mvebu-mbus to work: a top-level soc { ... } node, which corresponds to the MBus bus, and a sub-node internal-regs { ... } for all peripherals whose register sit only in the "Internal Register Window". This change re-indents by one level the definition of all nodes in the Device Tree, which explains the large change.

* Use custom functions orion5x_dt_init_early() and orion5x_dt_init_time() instead of orion5x_init_early() and orion5x_timer_init() as we now want the MBus driver to be probed from the Device Tree. We still use the old-style timer initialization, but that will be changed in a followup commit.

Signed-off-by Thomas Petazzoni <[email protected]>

---
  .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts    |  23 +-
  arch/arm/boot/dts/orion5x-mv88f5182.dtsi           |  24 ++
  arch/arm/boot/dts/orion5x.dtsi                     | 245 +++++++++++----------
  arch/arm/mach-orion5x/board-dt.c                   |  20 +-
  4 files changed, 182 insertions(+), 130 deletions(-)

create mode 100644 arch/arm/boot/dts/orion5x-mv88f5182.dtsi

arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +14 -9

index 24f1ce7..d66d2fa 100644
@@ -10,7 +10,7 @@
 
  #include <dt-bindings/gpio/gpio.h>
  #include <dt-bindings/input/input.h>
-#include "orion5x.dtsi"
+#include "orion5x-mv88f5182.dtsi"
 
  / {
  	model = "LaCie Ethernet Disk mini V2";

@@ -24,15 +24,20 @@
  		bootargs = "console=ttyS0,115200n8 earlyprintk";
  	};
 
-	ocp at f1000000 {
-		serial at 12000 {
-			clock-frequency = <166666667>;
-			status = "okay";
-		};
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
+			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>;
+
+		internal-regs {
+			serial at 12000 {
+				clock-frequency = <166666667>;
+				status = "okay";
+			};
 
-		sata at 80000 {
-			status = "okay";
-			nr-ports = <2>;
+			sata at 80000 {
+				status = "okay";
+				nr-ports = <2>;
+			};
  		};
  	};
 

arch/arm/boot/dts/orion5x-mv88f5182.dtsi new file +24 -0

new file mode 100644
index 0000000..ddfb4d1
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2014 Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "orion5x.dtsi"
+
+/ {
+	compatible = "marvell,orion5x-88f5182", "marvell,orion5x";
+
+	soc {
+		compatible = "marvell,orion5x-88f5182-mbus", "simple-bus";
+
+		internal-regs {
+			mbusc: mbus-controller at 20000 {
+				compatible = "marvell,mbus-controller";
+				reg = <0x20000 0x100>, <0x1500 0x20>;
+			};
+		};
+	};
+};

arch/arm/boot/dts/orion5x.dtsi +126 -119

index 2364e3d..31d46e6 100644
@@ -8,6 +8,8 @@
 
  #include "skeleton.dtsi"
 
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
  / {
  	model = "Marvell Orion5x SoC";
  	compatible = "marvell,orion5x";

@@ -17,149 +19,154 @@
  		gpio0 = &gpio0;
  	};
 
-	ocp at f1000000 {
-		compatible = "simple-bus";
-		ranges = <0x00000000 0xf1000000 0x4000000
-		          0xf2200000 0xf2200000 0x0000800>;
-		#address-cells = <1>;
+	soc {
+		#address-cells = <2>;
  		#size-cells = <1>;
+		controller = <&mbusc>;
 
-		gpio0: gpio at 10100 {
-			compatible = "marvell,orion-gpio";
-			#gpio-cells = <2>;
-			gpio-controller;
-			reg = <0x10100 0x40>;
-			ngpios = <32>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			interrupts = <6>, <7>, <8>, <9>;
-		};
-
-		spi at 10600 {
-			compatible = "marvell,orion-spi";
+		internal-regs {
+			compatible = "simple-bus";
  			#address-cells = <1>;
-			#size-cells = <0>;
-			cell-index = <0>;
-			reg = <0x10600 0x28>;
-			status = "disabled";
-		};
-
-		i2c at 11000 {
-			compatible = "marvell,mv64xxx-i2c";
-			reg = <0x11000 0x20>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <5>;
-			clock-frequency = <100000>;
-			status = "disabled";
-		};
+			#size-cells = <1>;
+			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+			gpio0: gpio at 10100 {
+				compatible = "marvell,orion-gpio";
+				#gpio-cells = <2>;
+				gpio-controller;
+				reg = <0x10100 0x40>;
+				ngpios = <32>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <6>, <7>, <8>, <9>;
+			};
 
-		serial at 12000 {
-			compatible = "ns16550a";
-			reg = <0x12000 0x100>;
-			reg-shift = <2>;
-			interrupts = <3>;
-			/* set clock-frequency in board dts */
-			status = "disabled";
-		};
+			spi at 10600 {
+				compatible = "marvell,orion-spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				cell-index = <0>;
+				reg = <0x10600 0x28>;
+				status = "disabled";
+			};
 
-		serial at 12100 {
-			compatible = "ns16550a";
-			reg = <0x12100 0x100>;
-			reg-shift = <2>;
-			interrupts = <4>;
-			/* set clock-frequency in board dts */
-			status = "disabled";
-		};
+			i2c at 11000 {
+				compatible = "marvell,mv64xxx-i2c";
+				reg = <0x11000 0x20>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <5>;
+				clock-frequency = <100000>;
+				status = "disabled";
+			};
 
-		intc: interrupt-controller at 20200 {
-			compatible = "marvell,orion-intc";
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			reg = <0x20200 0x08>;
-		};
+			serial at 12000 {
+				compatible = "ns16550a";
+				reg = <0x12000 0x100>;
+				reg-shift = <2>;
+				interrupts = <3>;
+				/* set clock-frequency in board dts */
+				status = "disabled";
+			};
 
-		wdt at 20300 {
-			compatible = "marvell,orion-wdt";
-			reg = <0x20300 0x28>;
-			status = "okay";
-		};
+			serial at 12100 {
+				compatible = "ns16550a";
+				reg = <0x12100 0x100>;
+				reg-shift = <2>;
+				interrupts = <4>;
+				/* set clock-frequency in board dts */
+				status = "disabled";
+			};
 
-		ehci at 50000 {
-			compatible = "marvell,orion-ehci";
-			reg = <0x50000 0x1000>;
-			interrupts = <17>;
-			status = "disabled";
-		};
+			intc: interrupt-controller at 20200 {
+				compatible = "marvell,orion-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x20200 0x08>;
+			};
 
-		xor at 60900 {
-			compatible = "marvell,orion-xor";
-			reg = <0x60900 0x100
-			       0x60b00 0x100>;
-			status = "okay";
+			wdt at 20300 {
+				compatible = "marvell,orion-wdt";
+				reg = <0x20300 0x28>;
+				status = "okay";
+			};
 
-			xor00 {
-			      interrupts = <30>;
-			      dmacap,memcpy;
-			      dmacap,xor;
+			ehci at 50000 {
+				compatible = "marvell,orion-ehci";
+				reg = <0x50000 0x1000>;
+				interrupts = <17>;
+				status = "disabled";
  			};
-			xor01 {
-			      interrupts = <31>;
-			      dmacap,memcpy;
-			      dmacap,xor;
-			      dmacap,memset;
+
+			xor at 60900 {
+				compatible = "marvell,orion-xor";
+				reg = <0x60900 0x100
+				       0x60b00 0x100>;
+				status = "okay";
+
+				xor00 {
+				      interrupts = <30>;
+				      dmacap,memcpy;
+				      dmacap,xor;
+				};
+				xor01 {
+				      interrupts = <31>;
+				      dmacap,memcpy;
+				      dmacap,xor;
+				      dmacap,memset;
+				};
  			};
-		};
 
-		eth: ethernet-controller at 72000 {
-			compatible = "marvell,orion-eth";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x72000 0x4000>;
-			marvell,tx-checksum-limit = <1600>;
-			status = "disabled";
-
-			ethernet-port at 0 {
-				compatible = "marvell,orion-eth-port";
-				reg = <0>;
-				/* overwrite MAC address in bootloader */
-				local-mac-address = [00 00 00 00 00 00];
-				/* set phy-handle property in board file */
+			eth: ethernet-controller at 72000 {
+				compatible = "marvell,orion-eth";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x72000 0x4000>;
+				marvell,tx-checksum-limit = <1600>;
+				status = "disabled";
+
+				ethernet-port at 0 {
+					compatible = "marvell,orion-eth-port";
+					reg = <0>;
+					/* overwrite MAC address in bootloader */
+					local-mac-address = [00 00 00 00 00 00];
+					/* set phy-handle property in board file */
+				};
  			};
-		};
 
-		mdio: mdio-bus at 72004 {
-			compatible = "marvell,orion-mdio";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x72004 0x84>;
-			interrupts = <22>;
-			status = "disabled";
+			mdio: mdio-bus at 72004 {
+				compatible = "marvell,orion-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x72004 0x84>;
+				interrupts = <22>;
+				status = "disabled";
 
-			/* add phy nodes in board file */
-		};
+				/* add phy nodes in board file */
+			};
+
+			sata at 80000 {
+				compatible = "marvell,orion-sata";
+				reg = <0x80000 0x5000>;
+				interrupts = <29>;
+				status = "disabled";
+			};
 
-		sata at 80000 {
-			compatible = "marvell,orion-sata";
-			reg = <0x80000 0x5000>;
-			interrupts = <29>;
-			status = "disabled";
+			ehci at a0000 {
+				compatible = "marvell,orion-ehci";
+				reg = <0xa0000 0x1000>;
+				interrupts = <12>;
+				status = "disabled";
+			};
  		};
 
  		crypto at 90000 {
  			compatible = "marvell,orion-crypto";
-			reg = <0x90000 0x10000>,
-			      <0xf2200000 0x800>;
+			reg = <MBUS_ID(0xf0, 0x01) 0x90000 0x10000>,
+			      <MBUS_ID(0x09, 0x00) 0x0 0x800>;
  			reg-names = "regs", "sram";
  			interrupts = <28>;
  			status = "okay";
  		};
-
-		ehci at a0000 {
-			compatible = "marvell,orion-ehci";
-			reg = <0xa0000 0x1000>;
-			interrupts = <12>;
-			status = "disabled";
-		};
  	};
  };

arch/arm/mach-orion5x/board-dt.c +18 -2

index c134a82..7f00897 100644
@@ -15,10 +15,14 @@
  #include <linux/of.h>
  #include <linux/of_platform.h>
  #include <linux/cpu.h>
+#include <linux/mbus.h>
  #include <asm/system_misc.h>
  #include <asm/mach/arch.h>
+#include <asm/mach/map.h>
  #include <mach/orion5x.h>
+#include <mach/bridge-regs.h>
  #include <plat/irq.h>
+#include <plat/time.h>
  #include "common.h"
 
  static struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = {

@@ -31,6 +35,16 @@ static struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = {
  	{},
  };
 
+static void orion5x_dt_init_early(void)
+{
+	orion_time_set_base(TIMER_VIRT_BASE);
+}
+
+static void orion5x_dt_init_time(void)
+{
+	orion5x_timer_init();
+}
+
  static void __init orion5x_dt_init(void)
  {
  	char *dev_name;

@@ -39,6 +53,8 @@ static void __init orion5x_dt_init(void)
  	orion5x_id(&dev, &rev, &dev_name);
  	printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
 
+	BUG_ON(mvebu_mbus_dt_init());
+
  	/*
  	 * Setup Orion address map
  	 */

@@ -71,9 +87,9 @@ static const char *orion5x_dt_compat[] = {
  DT_MACHINE_START(ORION5X_DT, "Marvell Orion5x (Flattened Device Tree)")
  	/* Maintainer: Thomas Petazzoni <[email protected]> */
  	.map_io		= orion5x_map_io,
-	.init_early	= orion5x_init_early,
+	.init_early	= orion5x_dt_init_early,
  	.init_irq	= orion_dt_init_irq,
-	.init_time	= orion5x_timer_init,
+	.init_time	= orion5x_dt_init_time,
  	.init_machine	= orion5x_dt_init,
  	.restart	= orion5x_restart,
  	.dt_compat	= orion5x_dt_compat,

In order to ease identification of devices, it is useful to have Device Tree labels on all devices. This commit adds such labels to the Orion5x SoC Device Tree file.

Signed-off-by Thomas Petazzoni <[email protected]>

---
  arch/arm/boot/dts/orion5x.dtsi | 22 +++++++++++-----------
  1 file changed, 11 insertions(+), 11 deletions(-)

arch/arm/boot/dts/orion5x.dtsi +11 -11

index 31d46e6..aef5d17 100644
@@ -41,7 +41,7 @@
  				interrupts = <6>, <7>, <8>, <9>;
  			};
 
-			spi at 10600 {
+			spi: spi at 10600 {
  				compatible = "marvell,orion-spi";
  				#address-cells = <1>;
  				#size-cells = <0>;

@@ -50,7 +50,7 @@
  				status = "disabled";
  			};
 
-			i2c at 11000 {
+			i2c: i2c at 11000 {
  				compatible = "marvell,mv64xxx-i2c";
  				reg = <0x11000 0x20>;
  				#address-cells = <1>;

@@ -60,7 +60,7 @@
  				status = "disabled";
  			};
 
-			serial at 12000 {
+			uart0: serial at 12000 {
  				compatible = "ns16550a";
  				reg = <0x12000 0x100>;
  				reg-shift = <2>;

@@ -69,7 +69,7 @@
  				status = "disabled";
  			};
 
-			serial at 12100 {
+			uart1: serial at 12100 {
  				compatible = "ns16550a";
  				reg = <0x12100 0x100>;
  				reg-shift = <2>;

@@ -85,20 +85,20 @@
  				reg = <0x20200 0x08>;
  			};
 
-			wdt at 20300 {
+			wdt: wdt at 20300 {
  				compatible = "marvell,orion-wdt";
  				reg = <0x20300 0x28>;
  				status = "okay";
  			};
 
-			ehci at 50000 {
+			ehci0: ehci at 50000 {
  				compatible = "marvell,orion-ehci";
  				reg = <0x50000 0x1000>;
  				interrupts = <17>;
  				status = "disabled";
  			};
 
-			xor at 60900 {
+			xor: xor at 60900 {
  				compatible = "marvell,orion-xor";
  				reg = <0x60900 0x100
  				       0x60b00 0x100>;

@@ -125,7 +125,7 @@
  				marvell,tx-checksum-limit = <1600>;
  				status = "disabled";
 
-				ethernet-port at 0 {
+				ethport: ethernet-port at 0 {
  					compatible = "marvell,orion-eth-port";
  					reg = <0>;
  					/* overwrite MAC address in bootloader */

@@ -145,14 +145,14 @@
  				/* add phy nodes in board file */
  			};
 
-			sata at 80000 {
+			sata: sata at 80000 {
  				compatible = "marvell,orion-sata";
  				reg = <0x80000 0x5000>;
  				interrupts = <29>;
  				status = "disabled";
  			};
 
-			ehci at a0000 {
+			ehci1: ehci at a0000 {
  				compatible = "marvell,orion-ehci";
  				reg = <0xa0000 0x1000>;
  				interrupts = <12>;

@@ -160,7 +160,7 @@
  			};
  		};
 
-		crypto at 90000 {
+		cesa: crypto at 90000 {
  			compatible = "marvell,orion-crypto";
  			reg = <MBUS_ID(0xf0, 0x01) 0x90000 0x10000>,
  			      <MBUS_ID(0x09, 0x00) 0x0 0x800>;

As noted by Sebastian Hesselbarth, the Device Tree nodes for GPIO keys and LEDs should be named gpio-keys and gpio-leds.

Signed-off-by Thomas Petazzoni <[email protected]>

---
  arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +2 -2

index d66d2fa..d85a206 100644
@@ -41,7 +41,7 @@
  		};
  	};
 
-	gpio_keys {
+	gpio-keys {
  		compatible = "gpio-keys";
  		#address-cells = <1>;
  		#size-cells = <0>;

@@ -52,7 +52,7 @@
  		};
  	};
 
-	gpio_leds {
+	gpio-leds {
  		compatible = "gpio-leds";
 
  		led at 1 {

This commit adds the new linux,stdout-path to the edmini_v2 platform, pointing to the serial device use for the console.

Signed-off-by Thomas Petazzoni <[email protected]>

---
  arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 1 +
  1 file changed, 1 insertion(+)

arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +1 -0

index d85a206..df53d256 100644
@@ -22,6 +22,7 @@
 
  	chosen {
  		bootargs = "console=ttyS0,115200n8 earlyprintk";
+		linux,stdout-path = &uart0;
  	};
 
  	soc {

This commit converts the existing devices described in the edmini_v2 Device Tree to use node labels: the UART and SATA device. Also, it reorders the eth and mdio node label references to be sorted alphabetically.

Signed-off-by Thomas Petazzoni <[email protected]>

---
  .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts    | 30 ++++++++++------------
  1 file changed, 14 insertions(+), 16 deletions(-)

arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +14 -16

index df53d256..83f45a7 100644
@@ -28,18 +28,6 @@
  	soc {
  		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
  			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>;
-
-		internal-regs {
-			serial at 12000 {
-				clock-frequency = <166666667>;
-				status = "okay";
-			};
-
-			sata at 80000 {
-				status = "okay";
-				nr-ports = <2>;
-			};
-		};
  	};
 
  	gpio-keys {

@@ -63,6 +51,14 @@
  	};
  };
 
+&eth {
+	status = "okay";
+
+	ethernet-port at 0 {
+		phy-handle = <&ethphy>;
+	};
+};
+
  &mdio {
  	status = "okay";
 

@@ -71,10 +67,12 @@
  	};
  };
 
-&eth {
+&sata {
  	status = "okay";
+	nr-ports = <2>;
+};
 
-	ethernet-port at 0 {
-		phy-handle = <&ethphy>;
-	};
+&uart0 {
+	clock-frequency = <166666667>;
+	status = "okay";
  };

Quoted 6 lines · Thomas Petazzoni

This commit converts the existing devices described in the edmini_v2 Device Tree to use node labels: the UART and SATA device. Also, it reorders the eth and mdio node label references to be sorted alphabetically.

Signed-off-by Thomas Petazzoni <[email protected]>

Does this also mean, we agree on the "using node label references" topic for Kirkwood?

I continue to have mixed feelings about the usage of node labels. To me, it breaks the "tree" nature of the Device Tree, by turning it into just a bunch of &bleh { ... } long list of statements. But this is purely subjective (just like your opinion, I believe), and I wanted to move forward with this, so I just did what was necessary :-)

Quoted 6 lines

I continue to have mixed feelings about the usage of node labels. To me, it breaks the "tree" nature of the Device Tree, by turning it into just a bunch of &bleh { ... } long list of statements. But this is purely subjective (just like your opinion, I believe), and I wanted to move forward with this, so I just did what was necessary :-)

Let me try to convince you a little :) Regressions like this would never appear with proper usage of phandles:

http://www.spinics.net/lists/arm-kernel/msg322999.html

This may be a matter of taste, but when I'm on the devicetree "user" side, I really don't care if the USB0 is part of some super complex tree, but just want to enable it in my board. Writing:

&usb0 {
	status = "okay";
};

seems to be just fine.

Until the previous commit, the Orion5x clocks were not described in the Device Tree. Now that they are described in the Device Tree, we can replace the manual 'clock-frequency' property in the UART nodes by a nicer 'clocks' reference in those UART nodes.

This commit consequently removes the 'clock-frequency' property from the LaCie edmini_v2 board, which is at this point the only Orion5x board converted to the Device Tree.

Signed-off-by Thomas Petazzoni <[email protected]>

---
  arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 1 -
  arch/arm/boot/dts/orion5x.dtsi                            | 4 ++--
  2 files changed, 2 insertions(+), 3 deletions(-)

arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +0 -1

index 83f45a7..ba43197 100644
@@ -73,6 +73,5 @@
  };
 
  &uart0 {
-	clock-frequency = <166666667>;
  	status = "okay";
  };

arch/arm/boot/dts/orion5x.dtsi +2 -2

index ad23ff4..88df8a8 100644
@@ -65,7 +65,7 @@
  				reg = <0x12000 0x100>;
  				reg-shift = <2>;
  				interrupts = <3>;
-				/* set clock-frequency in board dts */
+				clocks = <&core_clk 0>;
  				status = "disabled";
  			};
 

@@ -74,7 +74,7 @@
  				reg = <0x12100 0x100>;
  				reg-shift = <2>;
  				interrupts = <4>;
-				/* set clock-frequency in board dts */
+				clocks = <&core_clk 0>;
  				status = "disabled";
  			};
 

However, the common CONFIG_MULTI_IRQ_HANDLER handler for non-DT platforms in plat-orion/irq.c doesn't match the needs of Orion5x. Also, it doesn't make much sense for orion_irq_init() to register the multi-IRQ handler: orion_irq_init() is called once for each IRQ cause/mask tuple, while the multi-IRQ handler only needs to be registered once.