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Support qcom GDSC hardware

PATCH Superseded Stephen Boyd 3 participants 9 messages Apr 4, 2014 – Dec 19, 2014

Subsystems (4)

v1 of 8 Superseded Latest is v8 →

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#0 lore raw

cover Support qcom GDSC hardware

These patches add support for the multimedia GDSCs on the apq8074 dragonboard. The first two patches (and potentially the last) should go through Mike's tree and the DTS patch should go through the qcom tree. Patches are based on v3.14. The probe will conflict with patches I sent to consolidate things. I'll rework these patches on top of that if the gdsc.c file is acked/reviewed.

Stephen Boyd (4):
clk: qcom: Add support for GDSCs
clk: qcom: Add GDSCs within 8974 multimedia clock controller
ARM: dts: qcom: Add GDSC nodes underneath clock controller
devicetree: bindings: qcom,mmcc: Document GDSC binding

 .../devicetree/bindings/clock/qcom,mmcc.txt        |  42 +++
 arch/arm/boot/dts/qcom-apq8074-dragonboard.dts     |  18 +
 arch/arm/boot/dts/qcom-msm8974.dtsi                |  26 ++
 drivers/clk/qcom/Makefile                          |   1 +
 drivers/clk/qcom/gdsc.c                            | 361 +++++++++++++++++++++
 drivers/clk/qcom/gdsc.h                            |  32 ++
 drivers/clk/qcom/mmcc-msm8974.c                    |  86 ++++-
 7 files changed, 564 insertions(+), 2 deletions(-)
 create mode 100644 drivers/clk/qcom/gdsc.c
 create mode 100644 drivers/clk/qcom/gdsc.h
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#1 lore raw

PATCH 1/4 clk: qcom: Add support for GDSCs

GDSCs (Global Distributed Switch Controllers) are responsible for safely collapsing and restoring power to peripherals in the SoC. Add support for these controllers to the clock driver as the registers are scattered throughout the clock controller register space.

This is largely based on code originally written by Matt Wagantall[1].

[1] https://www.codeaurora.org/cgit/quic/la/kernel/msm/tree/arch/arm/mach-msm/gdsc.c?h=msm-3.4

Cc Matt Wagantall <[email protected]>
Cc Mark Brown <[email protected]>
---
 drivers/clk/qcom/Makefile |   1 +
 drivers/clk/qcom/gdsc.c   | 361 ++++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/qcom/gdsc.h   |  32 ++++
 3 files changed, 394 insertions(+)
 create mode 100644 drivers/clk/qcom/gdsc.c
 create mode 100644 drivers/clk/qcom/gdsc.h
drivers/clk/qcom/Makefile +1 -0
index f60db2ef1aee..2bc09576990a 100644
@@ -6,6 +6,7 @@ clk-qcom-y += clk-rcg.o
 clk-qcom-y += clk-rcg2.o
 clk-qcom-y += clk-branch.o
 clk-qcom-y += reset.o
+clk-qcom-y += gdsc.o
 
 obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
 obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
drivers/clk/qcom/gdsc.c new file +361 -0

361 lines not on this page · raw message

drivers/clk/qcom/gdsc.h new file +32 -0
new file mode 100644
index 000000000000..bd034c5071a9
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __QCOM_GDSC_H__
+#define __QCOM_GDSC_H__
+
+struct device;
+struct device_node;
+struct of_regulator_match;
+
+struct gdsc_desc {
+	unsigned int gdscr;
+	unsigned int *cxcs;
+	int cxc_count;
+	unsigned int *resets;
+	int reset_count;
+};
+
+extern int gdsc_register(struct device *pdev, struct of_regulator_match *match,
+			 struct reset_controller_dev *rcdev);
+
+#endif
Signature · 2 lines
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#2 lore raw

PATCH 2/4 clk: qcom: Add GDSCs within 8974 multimedia clock controller

In reply to Stephen Boyd

Add the necessary data and register the GDSCs that are present on the 8974 multimedia clock controller.

---
 drivers/clk/qcom/mmcc-msm8974.c | 86 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 84 insertions(+), 2 deletions(-)
drivers/clk/qcom/mmcc-msm8974.c +84 -2
index c95774514b81..1e7f69716d2f 100644
@@ -21,6 +21,7 @@
 #include <linux/clk-provider.h>
 #include <linux/regmap.h>
 #include <linux/reset-controller.h>
+#include <linux/regulator/of_regulator.h>
 
 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
 #include <dt-bindings/reset/qcom,mmcc-msm8974.h>
@@ -30,6 +31,7 @@
 #include "clk-rcg.h"
 #include "clk-branch.h"
 #include "reset.h"
+#include "gdsc.h"
 
 #define P_XO		0
 #define P_MMPLL0	1
@@ -2516,6 +2518,60 @@ static const struct qcom_reset_map mmcc_msm8974_resets[] = {
 	[OCMEMNOC_RESET] = { 0x50b0 },
 };
 
+static struct gdsc_desc gdsc_venus = {
+	.gdscr = 0x1024,
+	.cxcs = (unsigned int []){ 0x1028 },
+	.cxc_count = 1,
+	.resets = (unsigned int []){ VENUS0_RESET },
+	.reset_count = 1,
+};
+
+static struct gdsc_desc gdsc_mdss = {
+	.gdscr = 0x2304,
+	.cxcs = (unsigned int []){ 0x231c, 0x2320 },
+	.cxc_count = 2,
+	.resets = (unsigned int []){ MDSS_RESET },
+	.reset_count = 1,
+};
+
+static struct gdsc_desc gdsc_jpeg = {
+	.gdscr = 0x35a4,
+	.cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 },
+	.cxc_count = 3,
+	.resets = (unsigned int []){ CAMSS_JPEG_RESET },
+	.reset_count = 1,
+};
+
+static struct gdsc_desc gdsc_vfe = {
+	.gdscr = 0x36a4,
+	.cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 },
+	.cxc_count = 5,
+	.resets = (unsigned int []){ CAMSS_VFE_RESET, CAMSS_CSI_VFE0_RESET,
+				     CAMSS_CSI_VFE1_RESET },
+	.reset_count = 3,
+};
+
+static struct gdsc_desc gdsc_oxili_gx = {
+	.gdscr = 0x4024,
+	.cxcs = (unsigned int []){ 0x4028 },
+	.cxc_count = 1,
+	.resets = (unsigned int []){ OXILI_RESET },
+	.reset_count = 1,
+};
+
+static struct gdsc_desc gdsc_oxili_cx = {
+	.gdscr = 0x4034,
+};
+
+static struct of_regulator_match mmcc_msm8974_gdscs[] = {
+	{ .name = "gdsc_venus", .driver_data = &gdsc_venus },
+	{ .name = "gdsc_mdss", .driver_data = &gdsc_mdss },
+	{ .name = "gdsc_jpeg", .driver_data = &gdsc_jpeg },
+	{ .name = "gdsc_vfe", .driver_data = &gdsc_vfe },
+	{ .name = "gdsc_oxili_gx", .driver_data = &gdsc_oxili_gx },
+	{ .name = "gdsc_oxili_cx", .driver_data = &gdsc_oxili_cx },
+};
+
 static const struct regmap_config mmcc_msm8974_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,
@@ -2540,7 +2596,7 @@ static int mmcc_msm8974_probe(struct platform_device *pdev)
 {
 	void __iomem *base;
 	struct resource *res;
-	int i, ret;
+	int i, ret, num;
 	struct device *dev = &pdev->dev;
 	struct clk *clk;
 	struct clk_onecell_data *data;
@@ -2549,6 +2605,7 @@ static int mmcc_msm8974_probe(struct platform_device *pdev)
 	size_t num_clks;
 	struct qcom_reset_controller *reset;
 	struct qcom_cc *cc;
+	struct device_node *regs;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	base = devm_ioremap_resource(dev, res);
@@ -2597,8 +2654,33 @@ static int mmcc_msm8974_probe(struct platform_device *pdev)
 
 	ret = reset_controller_register(&reset->rcdev);
 	if (ret)
-		of_clk_del_provider(dev->of_node);
+		goto err_reset;
+
+	regs = of_get_child_by_name(dev->of_node, "regulators");
+	if (!regs)
+		return 0;
+
+	num = of_regulator_match(&pdev->dev, regs, mmcc_msm8974_gdscs,
+				 ARRAY_SIZE(mmcc_msm8974_gdscs));
+	of_node_put(regs);
+	if (num < 0) {
+		dev_err(&pdev->dev, "Regulator match failed\n");
+		ret = num;
+		goto err_regs;
+	}
+
+	for (i = 0; i < num; i++) {
+		ret = gdsc_register(&pdev->dev, &mmcc_msm8974_gdscs[i],
+				    &reset->rcdev);
+		if (ret)
+			goto err_regs;
+	}
 
+	return 0;
+err_regs:
+	reset_controller_unregister(&reset->rcdev);
+err_reset:
+	of_clk_del_provider(dev->of_node);
 	return ret;
 }
 
Signature · 2 lines
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hosted by The Linux Foundation
#3 lore raw

PATCH 3/4 ARM: dts: qcom: Add GDSC nodes underneath clock controller

In reply to Stephen Boyd

Add nodes for the GDSCs present on the multimedia clock controller in 8974.

---
 arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 18 ++++++++++++++++++
 arch/arm/boot/dts/qcom-msm8974.dtsi            | 26 ++++++++++++++++++++++++++
 2 files changed, 44 insertions(+)
arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +18 -0
index 13ac3e222495..478e89de0f38 100644
@@ -3,4 +3,22 @@
 / {
 	model = "Qualcomm APQ8074 Dragonboard";
 	compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";
+
+};
+
+&gdsc_venus {
+	qcom,skip-logic-collapse;
+	qcom,retain-periph;
+	qcom,retain-mem;
+};
+
+&gdsc_mdss {
+	qcom,skip-logic-collapse;
+	qcom,retain-periph;
+	qcom,retain-mem;
+};
+
+&gdsc_oxili_gx {
+	qcom,retain-mem;
+	qcom,retain-periph;
 };
arch/arm/boot/dts/qcom-msm8974.dtsi +26 -0
index 9e5dadb101eb..e38ae30930b2 100644
@@ -108,6 +108,32 @@
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			reg = <0xfd8c0000 0x6000>;
+
+			regulators {
+				gdsc_venus: gdsc_venus {
+					regulator-name = "gdsc_venus";
+				};
+
+				gdsc_mdss: gdsc_mdss {
+					regulator-name = "gdsc_mdss";
+				};
+
+				gdsc_jpeg: gdsc_jpeg {
+					regulator-name = "gdsc_jpeg";
+				};
+
+				gdsc_vfe: gdsc_vfe {
+					regulator-name = "gdsc_vfe";
+				};
+
+				gdsc_oxili_gx: gdsc_oxili_gx {
+					regulator-name = "gdsc_oxili_gx";
+				};
+
+				gdsc_oxili_cx: gdsc_oxili_cx {
+					regulator-name = "gdsc_oxili_cx";
+				};
+			};
 		};
 
 		serial at f991e000 {
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
#4 lore raw

PATCH 4/4 devicetree: bindings: qcom,mmcc: Document GDSC binding

In reply to Stephen Boyd

Document the GDSC nodes present within the multimedia clock controller.

---
 .../devicetree/bindings/clock/qcom,mmcc.txt        | 42 ++++++++++++++++++++++
 1 file changed, 42 insertions(+)
Documentation/devicetree/bindings/clock/qcom,mmcc.txt +42 -0
index d572e9964c54..695f86ad94ea 100644
@@ -19,3 +19,45 @@ Example:
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
+
+Qualcomm Global Distributed Switch Controller (GDSC) Binding
+------------------------------------------------------------
+
+The GDSC is responsible for safely collapsing and restoring power to
+peripheral cores on chipsets like msm8974 for power savings.
+
+Required properties:
+ - regulator-name:  A string used as a descriptive name for regulator outputs
+
+Optional properties:
+ - parent-supply:   phandle to the parent supply/regulator node
+ - qcom,retain-mem:  Presence denotes a hardware requirement to leave the
+		     forced core memory retention signals in the core's clock
+		     branch control registers asserted.
+ - qcom,retain-periph: Presence denotes a hardware requirement to leave the
+		     forced periph memory retention signal in the core's clock
+		     branch control registers asserted.
+ - qcom,skip-logic-collapse: Presence denotes a requirement to leave power to
+                             the core's logic enabled.
+ - qcom,support-hw-trigger: Presence denotes a hardware feature to switch
+			    on/off this regulator based on internal HW signals
+			    to save more power.
+
+Example:
+	clock-controller at 4000000 {
+		compatible = "qcom,mmcc-msm8974";
+		reg = <0x4000000 0x1000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+
+		regulators {
+			gdsc_oxili_gx: gdsc_oxili_gx {
+				regulator-name = "gdsc_oxili_gx";
+				parent-supply = <&pm8841_s4>;
+				qcom,retain-mem;
+				qcom,retain-periph;
+				qcom,skip-logic-collapse;
+				qcom,support-hw-trigger;
+			};
+		};
+	};
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#5 lore raw

PATCH 4/4 devicetree: bindings: qcom, mmcc: Document GDSC binding

Quoting Stephen Boyd (2014-04-04 11:45:36)

Documentation/devicetree/bindings/clock/qcom,mmcc.txt Example: · line 55

Quoted 10 lines
Documentation/devicetree/bindings/clock/qcom,mmcc.txt +10 -0
+Example:
+       clock-controller at 4000000 {
+               compatible = "qcom,mmcc-msm8974";
+               reg = <0x4000000 0x1000>;
+               #clock-cells = <1>;
+               #reset-cells = <1>;
+
+               regulators {
+                       gdsc_oxili_gx: gdsc_oxili_gx {
+                               regulator-name = "gdsc_oxili_gx";

Hi Stephen,

It makes sense to model the gdsc's as regulators. It also makes sense to nest them within the clock-controller node, assuming that matches the register manual for your part.

However, does it make sense to put this new code under drivers/clk/qcom? I don't see a compelling reason. How about breaking the registers out into a header for easier reuse?

Regards,
Mike

Quoted 12 lines
Documentation/devicetree/bindings/clock/qcom,mmcc.txt +8 -0
+                               parent-supply = <&pm8841_s4>;
+                               qcom,retain-mem;
+                               qcom,retain-periph;
+                               qcom,skip-logic-collapse;
+                               qcom,support-hw-trigger;
+                       };
+               };
+       };
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hosted by The Linux Foundation
#6 lore raw

Re: [PATCH 4/4] devicetree: bindings: qcom,mmcc: Document GDSC binding

Quoted 14 lines · Mike Turquette

Quoting Stephen Boyd (2014-04-04 11:45:36)

Documentation/devicetree/bindings/clock/qcom,mmcc.txt Example: · line 55

Quoted 10 lines
Documentation/devicetree/bindings/clock/qcom,mmcc.txt +10 -0
+Example:
+       clock-controller at 4000000 {
+               compatible = "qcom,mmcc-msm8974";
+               reg = <0x4000000 0x1000>;
+               #clock-cells = <1>;
+               #reset-cells = <1>;
+
+               regulators {
+                       gdsc_oxili_gx: gdsc_oxili_gx {
+                               regulator-name = "gdsc_oxili_gx";

Hi Stephen,

Quoted 7 lines

It makes sense to model the gdsc's as regulators. It also makes sense to nest them within the clock-controller node, assuming that matches the register manual for your part.

However, does it make sense to put this new code under drivers/clk/qcom? I don't see a compelling reason. How about breaking the registers out into a header for easier reuse?

What registers are we talking about? I put this under drivers/clk/qcom because it's one device that happens to have all these different driver subsystems in it (clocks, reset, gdsc).

Signature · 2 lines
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#7 lore raw
In reply to Stephen Boyd
Quoted 6 lines · Stephen Boyd

These patches add support for the multimedia GDSCs on the apq8074 dragonboard. The first two patches (and potentially the last) should go through Mike's tree and the DTS patch should go through the qcom tree. Patches are based on v3.14. The probe will conflict with patches I sent to consolidate things. I'll rework these patches on top of that if the gdsc.c file is acked/reviewed.

Any comments?

Signature · 2 lines
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#8 lore raw
Quoted 10 lines · Stephen Boyd
Quoted 6 lines · Stephen Boyd

These patches add support for the multimedia GDSCs on the apq8074 dragonboard. The first two patches (and potentially the last) should go through Mike's tree and the DTS patch should go through the qcom tree. Patches are based on v3.14. The probe will conflict with patches I sent to consolidate things. I'll rework these patches on top of that if the gdsc.c file is acked/reviewed.

Any comments?

Hi,

It will nice if we can progress on this. They are several drivers posted already which depends on these regulators, USB3.0 and PCIe, at least.

Thank you.
Ivan