RAPL driver updates

Adding support for Broadwell model 0x3d and HSW model (0x3c)

Signed-off-by Jacob Pan <[email protected]>

---
 drivers/powercap/intel_rapl.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

drivers/powercap/intel_rapl.c +3 -1

index 1c987d2..b1cda6f 100644
@@ -951,7 +951,9 @@ static const struct x86_cpu_id rapl_ids[] = {
 	{ X86_VENDOR_INTEL, 6, 0x2d},/* Sandy Bridge EP */
 	{ X86_VENDOR_INTEL, 6, 0x37},/* Valleyview */
 	{ X86_VENDOR_INTEL, 6, 0x3a},/* Ivy Bridge */
-	{ X86_VENDOR_INTEL, 6, 0x45},/* Haswell */
+	{ X86_VENDOR_INTEL, 6, 0x3c},/* Haswell */
+	{ X86_VENDOR_INTEL, 6, 0x3d},/* Broadwell */
+	{ X86_VENDOR_INTEL, 6, 0x45},/* Haswell ULT */
 	/* TODO: Add more CPU IDs after testing */
 	{}
 };

Signature · 1 line

1.8.1.2

Jacob Pan

author

2014-04-28 22:05 UTC #3 lore raw

PATCH 3/5 x86, iosf: Add dummy functions for loadable modules

From: "David E. Box" <[email protected]>

Some loadable modules only need IOSF access on the platforms where it exists. Provide dummy functions to allow these modules to compile and load on the platforms where it doesn't exist.

Link http://lkml.kernel.org/r/[email protected] open here

---
 arch/x86/include/asm/iosf_mbi.h | 33 +++++++++++++++++++++++++++++++++
 arch/x86/kernel/iosf_mbi.c      |  6 ++++++
 2 files changed, 39 insertions(+)

arch/x86/include/asm/iosf_mbi.h +33 -0

index 8e71c79..9fc5402 100644
@@ -5,6 +5,8 @@
 #ifndef IOSF_MBI_SYMS_H
 #define IOSF_MBI_SYMS_H
 
+#ifdef CONFIG_IOSF_MBI
+
 #define MBI_MCR_OFFSET		0xD0
 #define MBI_MDR_OFFSET		0xD4
 #define MBI_MCRX_OFFSET		0xD8

@@ -50,6 +52,8 @@
 #define BT_MBI_PCIE_READ	0x00
 #define BT_MBI_PCIE_WRITE	0x01
 
+bool iosf_mbi_available(void);
+
 /**
  * iosf_mbi_read() - MailBox Interface read command
  * @port:	port indicating subunit being accessed

@@ -87,4 +91,33 @@ int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr);
  */
 int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask);
 
+#else /* CONFIG_IOSF_MBI is not enabled */
+static inline
+bool iosf_mbi_available(void)
+{
+	return false;
+}
+
+static inline
+int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
+{
+	WARN();
+	return -EPERM;
+}
+
+static inline
+int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
+{
+	WARN();
+	return -EPERM;
+}
+
+static inline
+int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
+{
+	WARN();
+	return -EPERM;
+}
+#endif /* CONFIG_IOSF_MBI */
+
 #endif /* IOSF_MBI_SYMS_H */

arch/x86/kernel/iosf_mbi.c +6 -0

index c3aae66..d3803c6 100644
@@ -177,6 +177,12 @@ int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
 }
 EXPORT_SYMBOL(iosf_mbi_modify);
 
+bool iosf_mbi_available(void)
+{
+	return mbi_pdev;
+}
+EXPORT_SYMBOL(iosf_mbi_available);
+
 static int iosf_mbi_probe(struct pci_dev *pdev,
 			  const struct pci_device_id *unused)
 {

Signature · 1 line

1.8.1.2

Jacob Pan

author

2014-04-28 14:04 UTC #4 lore raw

PATCH 4/5 x86/iosf: kconfig and used by other drivers

Allow Kconfig selection for IOSF driver. Fix warning condition when MBI interface dummy functions are called at runtime.

Signed-off-by Jacob Pan <[email protected]>

---
 arch/x86/Kconfig                | 2 +-
 arch/x86/include/asm/iosf_mbi.h | 9 +++++----
 2 files changed, 6 insertions(+), 5 deletions(-)

arch/x86/Kconfig +1 -1

index 25d2c6f..cda587b 100644
@@ -2375,7 +2375,7 @@ config X86_DMA_REMAP
 	depends on STA2X11
 
 config IOSF_MBI
-	bool
+	bool "Intel OnChip System Fabric mailbox"
 	depends on PCI
 	---help---
 	  To be selected by modules requiring access to the Intel OnChip System

arch/x86/include/asm/iosf_mbi.h +5 -4

index 9fc5402..74336f0 100644
@@ -5,7 +5,6 @@
 #ifndef IOSF_MBI_SYMS_H
 #define IOSF_MBI_SYMS_H
 
-#ifdef CONFIG_IOSF_MBI
 
 #define MBI_MCR_OFFSET		0xD0
 #define MBI_MDR_OFFSET		0xD4

@@ -52,6 +51,8 @@
 #define BT_MBI_PCIE_READ	0x00
 #define BT_MBI_PCIE_WRITE	0x01
 
+#ifdef CONFIG_IOSF_MBI
+
 bool iosf_mbi_available(void);
 
 /**

@@ -101,21 +102,21 @@ bool iosf_mbi_available(void)
 static inline
 int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
 {
-	WARN();
+	WARN(1, "MBI driver not available");
 	return -EPERM;
 }
 
 static inline
 int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
 {
-	WARN();
+	WARN(1, "MBI driver not available");
 	return -EPERM;
 }
 
 static inline
 int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
 {
-	WARN();
+	WARN(1, "MBI driver not available");
 	return -EPERM;
 }
 #endif /* CONFIG_IOSF_MBI */

Signature · 1 line

1.8.1.2

Jacob Pan

author

2014-04-28 22:05 UTC #5 lore raw

PATCH 5/5 powercap/rapl: change floor frequency for vallewview

RAPL power limit reduce power by limiting CPU P-state and other techniques. On Valleyview, RAPL power limit cannot go to LFM (low frequency mode) if we don't set the floor frequency via IOSF mailbox.

This patch enables setting of floor frquency such that RAPL power limit is more effective.

Signed-off-by Jacob Pan <[email protected]>

---
 drivers/powercap/intel_rapl.c | 27 +++++++++++++++++++--------
 1 file changed, 19 insertions(+), 8 deletions(-)

drivers/powercap/intel_rapl.c +19 -8

index b1cda6f..13e4776 100644
@@ -32,6 +32,7 @@
 
 #include <asm/processor.h>
 #include <asm/cpu_device_id.h>
+#include <asm/iosf_mbi.h>
 
 /* bitmasks for RAPL MSRs, used by primitive access functions */
 #define ENERGY_STATUS_MASK      0xffffffff

@@ -336,11 +337,17 @@ static int find_nr_power_limit(struct rapl_domain *rd)
 	return i;
 }
 
+#define VLV_CPU_POWER_BUDGET_CTL (0x2)
+static const struct x86_cpu_id valleyview_id[] = {
+	{ X86_VENDOR_INTEL, 6, 0x37},
+	{}
+};
+
 static int set_domain_enable(struct powercap_zone *power_zone, bool mode)
 {
 	struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
 	int nr_powerlimit;
-
+	u32 mdata = 0;
 	if (rd->state & DOMAIN_STATE_BIOS_LOCKED)
 		return -EACCES;
 	get_online_cpus();

@@ -350,7 +357,16 @@ static int set_domain_enable(struct powercap_zone *power_zone, bool mode)
 	/* always enable clamp such that p-state can go below OS requested
 	 * range. power capping priority over guranteed frequency.
 	 */
-	rapl_write_data_raw(rd, PL1_CLAMP, mode);
+	if (x86_match_cpu(valleyview_id)) {
+		iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_PMC_READ,
+			VLV_CPU_POWER_BUDGET_CTL, &mdata);
+		mdata &= ~(0x7f << 8);
+		mdata |= 1 << 8;
+		iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_PMC_WRITE,
+			VLV_CPU_POWER_BUDGET_CTL, mdata);
+	} else
+		rapl_write_data_raw(rd, PL1_CLAMP, mode);
+
 	/* some domains have pl2 */
 	if (nr_powerlimit > 1) {
 		rapl_write_data_raw(rd, PL2_ENABLE, mode);

@@ -833,11 +849,6 @@ static int rapl_write_data_raw(struct rapl_domain *rd,
 	return 0;
 }
 
-static const struct x86_cpu_id energy_unit_quirk_ids[] = {
-	{ X86_VENDOR_INTEL, 6, 0x37},/* Valleyview */
-	{}
-};
-
 static int rapl_check_unit(struct rapl_package *rp, int cpu)
 {
 	u64 msr_val;

@@ -859,7 +870,7 @@ static int rapl_check_unit(struct rapl_package *rp, int cpu)
 	 */
 	value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
 	/* some CPUs have different way to calculate energy unit */
-	if (x86_match_cpu(energy_unit_quirk_ids))
+	if (x86_match_cpu(valleyview_id))
 		rp->energy_unit_divisor = 1000000 / (1 << value);
 	else
 		rp->energy_unit_divisor = 1 << value;

Signature · 1 line

1.8.1.2

R, Durgadoss

2014-04-29 02:45 UTC #6 lore raw

RE: [PATCH 5/5] powercap/rapl: change floor frequency for vallewview

Hi Jacob,

Quoted 33 lines

-----Original Message-----
From: Jacob Pan [mailto:[email protected]]
Sent: Monday, April 28, 2014 7:35 PM
To: Linux PM; Wysocki, Rafael J; LKML
Cc: David E. Box; Alan Cox; R, Durgadoss; Accardi, Kristen C; Jacob Pan
Subject: [PATCH 5/5] powercap/rapl: change floor frequency for vallewview
RAPL power limit reduce power by limiting CPU P-state and other techniques. On Valleyview, RAPL power limit cannot go to LFM (low frequency mode) if we don't set the floor frequency via IOSF mailbox.
This patch enables setting of floor frquency such that RAPL power limit is more effective.
Signed-off-by Jacob Pan <[email protected]>
---
 drivers/powercap/intel_rapl.c | 27 +++++++++++++++++++--------
 1 file changed, 19 insertions(+), 8 deletions(-)
drivers/powercap/intel_rapl.c +1 -0
index b1cda6f..13e4776 100644
@@ -32,6 +32,7 @@
 
 #include <asm/processor.h>
 #include <asm/cpu_device_id.h>
+#include <asm/iosf_mbi.h>
 
 /* bitmasks for RAPL MSRs, used by primitive access functions */
 #define ENERGY_STATUS_MASK      0xffffffff

drivers/powercap/intel_rapl.c static int find_nr_power_limit(struct rapl_domain *rd) · line 344

Quoted 8 lines

drivers/powercap/intel_rapl.c +5 -0

@@ -336,11 +337,17 @@ static int find_nr_power_limit(struct rapl_domain *rd)
 	return i;
 }
 
+#define VLV_CPU_POWER_BUDGET_CTL (0x2)
+static const struct x86_cpu_id valleyview_id[] = {
+	{ X86_VENDOR_INTEL, 6, 0x37},
+	{}
+};

There are other platforms that have this FloorFreq register as well. And those addresses are not '0x02'. So, we need to have a cpu_id based table to define the address of the floor freq register as well. [This is not specific to valleyview.]

Also, is there a plan to expose this floor freq ratio through Sysfs for runtime configuration. ? May be through a standard thermal cooling device interface ?

Quoted 30 lines

drivers/powercap/intel_rapl.c +12 -2

+
 static int set_domain_enable(struct powercap_zone *power_zone, bool mode)
 {
 	struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
 	int nr_powerlimit;
-
+	u32 mdata = 0;
 	if (rd->state & DOMAIN_STATE_BIOS_LOCKED)
 		return -EACCES;
 	get_online_cpus();

@@ -350,7 +357,16 @@ static int set_domain_enable(struct powercap_zone
 *power_zone, bool mode)
 	/* always enable clamp such that p-state can go below OS requested
 	 * range. power capping priority over guranteed frequency.
 	 */
-	rapl_write_data_raw(rd, PL1_CLAMP, mode);
+	if (x86_match_cpu(valleyview_id)) {
+		iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_PMC_READ,
+			VLV_CPU_POWER_BUDGET_CTL, &mdata);
+		mdata &= ~(0x7f << 8);
+		mdata |= 1 << 8;
+		iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_PMC_WRITE,
+			VLV_CPU_POWER_BUDGET_CTL, mdata);
+	} else
+		rapl_write_data_raw(rd, PL1_CLAMP, mode);
+
 	/* some domains have pl2 */
 	if (nr_powerlimit > 1) {

drivers/powercap/intel_rapl.c +0 -0

 		rapl_write_data_raw(rd, PL2_ENABLE, mode);

drivers/powercap/intel_rapl.c static int rapl_write_data_raw(struct rapl_domain *rd, · line 839

Quoted 7 lines

drivers/powercap/intel_rapl.c +0 -4

@@ -833,11 +849,6 @@ static int rapl_write_data_raw(struct rapl_domain *rd,
 	return 0;
 }
 
-static const struct x86_cpu_id energy_unit_quirk_ids[] = {
-	{ X86_VENDOR_INTEL, 6, 0x37},/* Valleyview */
-	{}
-};

Same thing here. There are other Atom platforms that need this conversion quirk. So, please keep the table as is.

Thanks,
Durga

Quoted 15 lines

drivers/powercap/intel_rapl.c +1 -3

-
 static int rapl_check_unit(struct rapl_package *rp, int cpu)
 {
 	u64 msr_val;

@@ -859,7 +870,7 @@ static int rapl_check_unit(struct rapl_package *rp, int cpu)
 	 */
 	value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
 	/* some CPUs have different way to calculate energy unit */
-	if (x86_match_cpu(energy_unit_quirk_ids))
+	if (x86_match_cpu(valleyview_id))
 		rp->energy_unit_divisor = 1000000 / (1 << value);
 	else
 		rp->energy_unit_divisor = 1 << value;
--

1.8.1.2

Jacob Pan

author

2014-04-29 13:02 UTC #7 lore raw

Re: [PATCH 5/5] powercap/rapl: change floor frequency for vallewview

Quoted 39 lines · Durgadoss

Hi Jacob,
Quoted 37 lines
-----Original Message-----
From: Jacob Pan [mailto:[email protected]]
Sent: Monday, April 28, 2014 7:35 PM
To: Linux PM; Wysocki, Rafael J; LKML
Cc: David E. Box; Alan Cox; R, Durgadoss; Accardi, Kristen C; Jacob Pan Subject: [PATCH 5/5] powercap/rapl: change floor frequency for vallewview
RAPL power limit reduce power by limiting CPU P-state and other techniques. On Valleyview, RAPL power limit cannot go to LFM (low frequency mode) if we don't set the floor frequency via IOSF mailbox.
This patch enables setting of floor frquency such that RAPL power limit is more effective.
Signed-off-by Jacob Pan <[email protected]>
---
 drivers/powercap/intel_rapl.c | 27 +++++++++++++++++++--------
 1 file changed, 19 insertions(+), 8 deletions(-)
(quoted diff) +0 -0
b/drivers/powercap/intel_rapl.c index b1cda6f..13e4776 100644
drivers/powercap/intel_rapl.c +1 -0
@@ -32,6 +32,7 @@
 
 #include <asm/processor.h>
 #include <asm/cpu_device_id.h>
+#include <asm/iosf_mbi.h>
 
 /* bitmasks for RAPL MSRs, used by primitive access functions */
 #define ENERGY_STATUS_MASK      0xffffffff
@@ -336,11 +337,17 @@ static int find_nr_power_limit(struct
 rapl_domain *rd) return i;
 }
 

Quoted 11 lines

drivers/powercap/intel_rapl.c static int find_nr_power_limit(struct rapl_domain *rd) · line 344
Quoted 5 lines
drivers/powercap/intel_rapl.c +5 -0
+#define VLV_CPU_POWER_BUDGET_CTL (0x2)
+static const struct x86_cpu_id valleyview_id[] = {
+	{ X86_VENDOR_INTEL, 6, 0x37},
+	{}
+};
There are other platforms that have this FloorFreq register as well. And those addresses are not '0x02'. So, we need to have a cpu_id based table to define the address of the floor freq register as well. [This is not specific to valleyview.]

Sounds like I need to add an abstraction to capture this. So far, there are only two exceptions so i was hesitate to do so. Thanks for the input.

Quoted 4 lines

Also, is there a plan to expose this floor freq ratio through Sysfs for runtime configuration. ? May be through a standard thermal cooling device interface ?

why would that be necessary? who will use it? floor freq only affects RAPL, AFAIK. In Linux there is no guaranteed freq anyway. My original patch to enable RAPL as cooling device was abandoned in favor of powercap framework, I am not sure if we should go back.

Quoted 45 lines

Quoted 31 lines

drivers/powercap/intel_rapl.c +2 -1

+
 static int set_domain_enable(struct powercap_zone *power_zone,
 bool mode) {
 	struct rapl_domain *rd =
 power_zone_to_rapl_domain(power_zone); int nr_powerlimit;
-
+	u32 mdata = 0;
 	if (rd->state & DOMAIN_STATE_BIOS_LOCKED)
 		return -EACCES;
 	get_online_cpus();

@@ -350,7 +357,16 @@ static int set_domain_enable(struct
 powercap_zone *power_zone, bool mode)
 	/* always enable clamp such that p-state can go below OS

requested

drivers/powercap/intel_rapl.c +10 -1

 	 * range. power capping priority over guranteed frequency.
 	 */
-	rapl_write_data_raw(rd, PL1_CLAMP, mode);
+	if (x86_match_cpu(valleyview_id)) {
+		iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_PMC_READ,
+			VLV_CPU_POWER_BUDGET_CTL, &mdata);
+		mdata &= ~(0x7f << 8);
+		mdata |= 1 << 8;
+		iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_PMC_WRITE,
+			VLV_CPU_POWER_BUDGET_CTL, mdata);
+	} else
+		rapl_write_data_raw(rd, PL1_CLAMP, mode);
+
 	/* some domains have pl2 */
 	if (nr_powerlimit > 1) {
 		rapl_write_data_raw(rd, PL2_ENABLE, mode);

drivers/powercap/intel_rapl.c static int rapl_write_data_raw(struct · line 839

Quoted 7 lines

drivers/powercap/intel_rapl.c +0 -4

@@ -833,11 +849,6 @@ static int rapl_write_data_raw(struct
 rapl_domain *rd, return 0;
 }
 
-static const struct x86_cpu_id energy_unit_quirk_ids[] = {
-	{ X86_VENDOR_INTEL, 6, 0x37},/* Valleyview */
-	{}
-};

Same thing here. There are other Atom platforms that need this conversion quirk. So, please keep the table as is.

Thanks,
Durga

Quoted 16 lines

Quoted 14 lines

drivers/powercap/intel_rapl.c +1 -3

-
 static int rapl_check_unit(struct rapl_package *rp, int cpu)
 {
 	u64 msr_val;

@@ -859,7 +870,7 @@ static int rapl_check_unit(struct rapl_package
 *rp, int cpu) */
 	value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
 	/* some CPUs have different way to calculate energy unit */
-	if (x86_match_cpu(energy_unit_quirk_ids))
+	if (x86_match_cpu(valleyview_id))
 		rp->energy_unit_divisor = 1000000 / (1 << value);
 	else
 		rp->energy_unit_divisor = 1 << value;
--

Quoted 1 line

1.8.1.2

[Jacob Pan]

R, Durgadoss

2014-04-29 14:40 UTC #8 lore raw

RE: [PATCH 5/5] powercap/rapl: change floor frequency for vallewview

Quoted 60 lines

-----Original Message-----
From: Jacob Pan [mailto:[email protected]]
Sent: Tuesday, April 29, 2014 6:33 PM
To: R, Durgadoss
Cc: Linux PM; Wysocki, Rafael J; LKML; David E. Box; Alan Cox; Accardi, Kristen C
Subject: Re: [PATCH 5/5] powercap/rapl: change floor frequency for vallewview
Quoted 39 lines · Durgadoss
Hi Jacob,
Quoted 37 lines
-----Original Message-----
From: Jacob Pan [mailto:[email protected]]
Sent: Monday, April 28, 2014 7:35 PM
To: Linux PM; Wysocki, Rafael J; LKML
Cc: David E. Box; Alan Cox; R, Durgadoss; Accardi, Kristen C; Jacob Pan Subject: [PATCH 5/5] powercap/rapl: change floor frequency for vallewview
RAPL power limit reduce power by limiting CPU P-state and other techniques. On Valleyview, RAPL power limit cannot go to LFM (low frequency mode) if we don't set the floor frequency via IOSF mailbox.
This patch enables setting of floor frquency such that RAPL power limit is more effective.
Signed-off-by Jacob Pan <[email protected]>
---
 drivers/powercap/intel_rapl.c | 27 +++++++++++++++++++--------
 1 file changed, 19 insertions(+), 8 deletions(-)
(quoted diff) +0 -0
b/drivers/powercap/intel_rapl.c index b1cda6f..13e4776 100644
drivers/powercap/intel_rapl.c +1 -0
@@ -32,6 +32,7 @@
 
 #include <asm/processor.h>
 #include <asm/cpu_device_id.h>
+#include <asm/iosf_mbi.h>
 
 /* bitmasks for RAPL MSRs, used by primitive access functions */
 #define ENERGY_STATUS_MASK      0xffffffff
@@ -336,11 +337,17 @@ static int find_nr_power_limit(struct
 rapl_domain *rd) return i;
 }
 
Quoted 11 lines
drivers/powercap/intel_rapl.c static int find_nr_power_limit(struct rapl_domain *rd) · line 344
Quoted 5 lines
drivers/powercap/intel_rapl.c +5 -0
+#define VLV_CPU_POWER_BUDGET_CTL (0x2)
+static const struct x86_cpu_id valleyview_id[] = {
+	{ X86_VENDOR_INTEL, 6, 0x37},
+	{}
+};
There are other platforms that have this FloorFreq register as well. And those addresses are not '0x02'. So, we need to have a cpu_id based table to define the address of the floor freq register as well. [This is not specific to valleyview.]

Quoted 3 lines

Sounds like I need to add an abstraction to capture this. So far, there are only two exceptions so i was hesitate to do so. Thanks for the input.

Yes, We at least have few platforms that need this.

Quoted 8 lines

Quoted 4 lines
Also, is there a plan to expose this floor freq ratio through Sysfs for runtime configuration. ? May be through a standard thermal cooling device interface ?
why would that be necessary? who will use it? floor freq only affects RAPL, AFAIK. In Linux there is no guaranteed freq anyway. My original patch to enable RAPL as cooling device was abandoned in favor of powercap framework, I am not sure if we should go back.

There are user space thermal controls which change RAPL Power limits according to platform's thermal condition as you might be aware.

The floor frequency is not used only to transition to LFM ratio. We can transition to any frequency ratio by adjusting this floor frequency (at least on VLV and couple more platforms)

Hence while changing RAPL Power Limits, there is a need to adjust this also, to specify which ratio is our Floor (basically we will not go below that). That's why we need an interface for modifying this at run time (along with Power Limits).

Thanks,
Durga

Quoted 63 lines

Quoted 45 lines

Quoted 31 lines

drivers/powercap/intel_rapl.c +2 -1

+
 static int set_domain_enable(struct powercap_zone *power_zone,
 bool mode) {
 	struct rapl_domain *rd =
 power_zone_to_rapl_domain(power_zone); int nr_powerlimit;
-
+	u32 mdata = 0;
 	if (rd->state & DOMAIN_STATE_BIOS_LOCKED)
 		return -EACCES;
 	get_online_cpus();

@@ -350,7 +357,16 @@ static int set_domain_enable(struct
 powercap_zone *power_zone, bool mode)
 	/* always enable clamp such that p-state can go below OS

requested

drivers/powercap/intel_rapl.c +10 -1

 	 * range. power capping priority over guranteed frequency.
 	 */
-	rapl_write_data_raw(rd, PL1_CLAMP, mode);
+	if (x86_match_cpu(valleyview_id)) {
+		iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_PMC_READ,
+			VLV_CPU_POWER_BUDGET_CTL, &mdata);
+		mdata &= ~(0x7f << 8);
+		mdata |= 1 << 8;
+		iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_PMC_WRITE,
+			VLV_CPU_POWER_BUDGET_CTL, mdata);
+	} else
+		rapl_write_data_raw(rd, PL1_CLAMP, mode);
+
 	/* some domains have pl2 */
 	if (nr_powerlimit > 1) {
 		rapl_write_data_raw(rd, PL2_ENABLE, mode);

drivers/powercap/intel_rapl.c static int rapl_write_data_raw(struct · line 839

Quoted 7 lines

drivers/powercap/intel_rapl.c +0 -4

@@ -833,11 +849,6 @@ static int rapl_write_data_raw(struct
 rapl_domain *rd, return 0;
 }
 
-static const struct x86_cpu_id energy_unit_quirk_ids[] = {
-	{ X86_VENDOR_INTEL, 6, 0x37},/* Valleyview */
-	{}
-};

Same thing here. There are other Atom platforms that need this conversion quirk. So, please keep the table as is.

Thanks,
Durga

Quoted 16 lines

Quoted 14 lines

drivers/powercap/intel_rapl.c +1 -3

-
 static int rapl_check_unit(struct rapl_package *rp, int cpu)
 {
 	u64 msr_val;

@@ -859,7 +870,7 @@ static int rapl_check_unit(struct rapl_package
 *rp, int cpu) */
 	value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
 	/* some CPUs have different way to calculate energy unit */
-	if (x86_match_cpu(energy_unit_quirk_ids))
+	if (x86_match_cpu(valleyview_id))
 		rp->energy_unit_divisor = 1000000 / (1 << value);
 	else
 		rp->energy_unit_divisor = 1 << value;
--

Quoted 1 line

1.8.1.2

[Jacob Pan]

Jacob Pan

author

2014-04-29 16:25 UTC #9 lore raw

Re: [PATCH 5/5] powercap/rapl: change floor frequency for vallewview

Quoted 79 lines · Durgadoss

Quoted 61 lines
-----Original Message-----
From: Jacob Pan [mailto:[email protected]]
Sent: Tuesday, April 29, 2014 6:33 PM
To: R, Durgadoss
Cc: Linux PM; Wysocki, Rafael J; LKML; David E. Box; Alan Cox; Accardi, Kristen C Subject: Re: [PATCH 5/5] powercap/rapl: change floor frequency for vallewview
Quoted 39 lines · Durgadoss
Hi Jacob,
Quoted 37 lines
-----Original Message-----
From: Jacob Pan [mailto:[email protected]]
Sent: Monday, April 28, 2014 7:35 PM
To: Linux PM; Wysocki, Rafael J; LKML
Cc: David E. Box; Alan Cox; R, Durgadoss; Accardi, Kristen C; Jacob Pan Subject: [PATCH 5/5] powercap/rapl: change floor frequency for vallewview
RAPL power limit reduce power by limiting CPU P-state and other techniques. On Valleyview, RAPL power limit cannot go to LFM (low frequency mode) if we don't set the floor frequency via IOSF mailbox.
This patch enables setting of floor frquency such that RAPL power limit is more effective.
Signed-off-by Jacob Pan <[email protected]>
---
 drivers/powercap/intel_rapl.c | 27 +++++++++++++++++++--------
 1 file changed, 19 insertions(+), 8 deletions(-)
(quoted diff) +0 -0
b/drivers/powercap/intel_rapl.c index b1cda6f..13e4776 100644
drivers/powercap/intel_rapl.c +1 -0
@@ -32,6 +32,7 @@
 
 #include <asm/processor.h>
 #include <asm/cpu_device_id.h>
+#include <asm/iosf_mbi.h>
 
 /* bitmasks for RAPL MSRs, used by primitive access functions
 */ #define ENERGY_STATUS_MASK      0xffffffff
@@ -336,11 +337,17 @@ static int find_nr_power_limit(struct
 rapl_domain *rd) return i;
 }
 
Quoted 11 lines
drivers/powercap/intel_rapl.c static int find_nr_power_limit(struct rapl_domain *rd) · line 344
Quoted 5 lines
drivers/powercap/intel_rapl.c +5 -0
+#define VLV_CPU_POWER_BUDGET_CTL (0x2)
+static const struct x86_cpu_id valleyview_id[] = {
+	{ X86_VENDOR_INTEL, 6, 0x37},
+	{}
+};
There are other platforms that have this FloorFreq register as well. And those addresses are not '0x02'. So, we need to have a cpu_id based table to define the address of the floor freq register as well. [This is not specific to valleyview.]
Quoted 3 lines
Sounds like I need to add an abstraction to capture this. So far, there are only two exceptions so i was hesitate to do so. Thanks for the input.
Yes, We at least have few platforms that need this.
Quoted 8 lines
Quoted 4 lines
Also, is there a plan to expose this floor freq ratio through Sysfs for runtime configuration. ? May be through a standard thermal cooling device interface ?
why would that be necessary? who will use it? floor freq only affects RAPL, AFAIK. In Linux there is no guaranteed freq anyway. My original patch to enable RAPL as cooling device was abandoned in favor of powercap framework, I am not sure if we should go back.
There are user space thermal controls which change RAPL Power limits according to platform's thermal condition as you might be aware.

Quoted 9 lines

The floor frequency is not used only to transition to LFM ratio. We can transition to any frequency ratio by adjusting this floor frequency (at least on VLV and couple more platforms)
Hence while changing RAPL Power Limits, there is a need to adjust this also, to specify which ratio is our Floor (basically we will not go below that). That's why we need an interface for modifying this at run time (along with Power Limits).

I understand. What I am proposing here is to have a single knob for user control power, instead of two knobs (power limit and floor freq) which may have conflicts. When thermal throttling is needed, user only cares about power limit, that is why I think it is better to set floor to LFM and let power limit be the only knob. It is simpler. In case freq is a constraint, user should use cpufreq interface.

Quoted 68 lines

Thanks,
Durga
Quoted 65 lines
Quoted 46 lines
Quoted 32 lines
drivers/powercap/intel_rapl.c +2 -1
+
 static int set_domain_enable(struct powercap_zone *power_zone,
 bool mode) {
 	struct rapl_domain *rd =
 power_zone_to_rapl_domain(power_zone); int nr_powerlimit;
-
+	u32 mdata = 0;
 	if (rd->state & DOMAIN_STATE_BIOS_LOCKED)
 		return -EACCES;
 	get_online_cpus();
@@ -350,7 +357,16 @@ static int set_domain_enable(struct
 powercap_zone *power_zone, bool mode)
 	/* always enable clamp such that p-state can go below
OS requested
* range. power capping priority over guranteed
frequency. */
drivers/powercap/intel_rapl.c +6 -1
-	rapl_write_data_raw(rd, PL1_CLAMP, mode);
+	if (x86_match_cpu(valleyview_id)) {
+		iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_PMC_READ,
+			VLV_CPU_POWER_BUDGET_CTL, &mdata);
+		mdata &= ~(0x7f << 8);
+		mdata |= 1 << 8;
+		iosf_mbi_write(BT_MBI_UNIT_PMC,
BT_MBI_PMC_WRITE,
drivers/powercap/intel_rapl.c +4 -0
+			VLV_CPU_POWER_BUDGET_CTL, mdata);
+	} else
+		rapl_write_data_raw(rd, PL1_CLAMP, mode);
+
 	/* some domains have pl2 */
 	if (nr_powerlimit > 1) {
 		rapl_write_data_raw(rd, PL2_ENABLE, mode);
drivers/powercap/intel_rapl.c static int rapl_write_data_raw(struct · line 839
Quoted 7 lines
drivers/powercap/intel_rapl.c +0 -4
@@ -833,11 +849,6 @@ static int rapl_write_data_raw(struct
 rapl_domain *rd, return 0;
 }
 
-static const struct x86_cpu_id energy_unit_quirk_ids[] = {
-	{ X86_VENDOR_INTEL, 6, 0x37},/* Valleyview */
-	{}
-};
Same thing here. There are other Atom platforms that need this conversion quirk. So, please keep the table as is.
Thanks,
Durga
Quoted 17 lines
Quoted 12 lines
drivers/powercap/intel_rapl.c +0 -1
-
 static int rapl_check_unit(struct rapl_package *rp, int cpu)
 {
 	u64 msr_val;
@@ -859,7 +870,7 @@ static int rapl_check_unit(struct
rapl_package *rp, int cpu) */
value = (msr_val & ENERGY_UNIT_MASK) >>
ENERGY_UNIT_OFFSET; /* some CPUs have different way to calculate energy unit */
drivers/powercap/intel_rapl.c +1 -1
-	if (x86_match_cpu(energy_unit_quirk_ids))
+	if (x86_match_cpu(valleyview_id))
 		rp->energy_unit_divisor = 1000000 / (1 <<
Quoted 4 lines
value); else
rp->energy_unit_divisor = 1 << value;
--
1.8.1.2
[Jacob Pan]

[Jacob Pan]

David E. Box

2014-04-29 22:35 UTC #10 lore raw

v2 cover RAPL driver updates

From: "David E. Box" <[email protected]>

v2: iosf: Remove Kconfig exposure. Make mailbox driver a module.

David E. Box (1):
x86/iosf: Make IOSF driver modular and usable by more drivers

Jacob Pan (3):
powercap/rapl: further relax energy counter checks powercap/rapl: add new cpu ids powercap/rapl: change floor frequency for vallewview

 arch/x86/Kconfig                |    7 ++---
 arch/x86/include/asm/iosf_mbi.h |   33 +++++++++++++++++++++
 arch/x86/kernel/iosf_mbi.c      |    6 ++++
 drivers/powercap/intel_rapl.c   |   60 ++++++++++++++++++++-------------------
 4 files changed, 72 insertions(+), 34 deletions(-)

Signature · 1 line

1.7.10.4

David E. Box

2014-04-29 22:35 UTC #11 lore raw

PATCH v2 1/4 powercap/rapl: further relax energy counter checks

From: Jacob Pan <[email protected]>

Signed-off-by Jacob Pan <[email protected]>

---
 drivers/powercap/intel_rapl.c |   29 +++++++++--------------------
 1 file changed, 9 insertions(+), 20 deletions(-)

drivers/powercap/intel_rapl.c +9 ~~-20~~

index d9a0770..1c987d2 100644
@@ -1124,8 +1124,7 @@ err_cleanup_package:
 static int rapl_check_domain(int cpu, int domain)
 {
 	unsigned msr;
-	u64 val1, val2 = 0;
-	int retry = 0;
+	u64 val = 0;
 
 	switch (domain) {
 	case RAPL_DOMAIN_PACKAGE:

@@ -1144,26 +1143,13 @@ static int rapl_check_domain(int cpu, int domain)
 		pr_err("invalid domain id %d\n", domain);
 		return -EINVAL;
 	}
-	if (rdmsrl_safe_on_cpu(cpu, msr, &val1))
-		return -ENODEV;
-
-	/* PP1/uncore/graphics domain may not be active at the time of
-	 * driver loading. So skip further checks.
+	/* make sure domain counters are available and contains non-zero
+	 * values, otherwise skip it.
 	 */
-	if (domain == RAPL_DOMAIN_PP1)
-		return 0;
-	/* energy counters roll slowly on some domains */
-	while (++retry < 10) {
-		usleep_range(10000, 15000);
-		rdmsrl_safe_on_cpu(cpu, msr, &val2);
-		if ((val1 & ENERGY_STATUS_MASK) != (val2 & ENERGY_STATUS_MASK))
-			return 0;
-	}
-	/* if energy counter does not change, report as bad domain */
-	pr_info("domain %s energy ctr %llu:%llu not working, skip\n",
-		rapl_domain_names[domain], val1, val2);
+	if (rdmsrl_safe_on_cpu(cpu, msr, &val) || !val)
+		return -ENODEV;
 
-	return -ENODEV;
+	return 0;
 }
 
 /* Detect active and valid domains for the given CPU, caller must

@@ -1180,6 +1166,9 @@ static int rapl_detect_domains(struct rapl_package *rp, int cpu)
 		/* use physical package id to read counters */
 		if (!rapl_check_domain(cpu, i))
 			rp->domain_map |= 1 << i;
+		else
+			pr_warn("RAPL domain %s detection failed\n",
+				rapl_domain_names[i]);
 	}
 	rp->nr_domains = bitmap_weight(&rp->domain_map,	RAPL_DOMAIN_MAX);
 	if (!rp->nr_domains) {

Signature · 1 line

1.7.10.4

R, Durgadoss

Acked-by on v2 1/4

2014-04-30 05:29 UTC #12 lore raw

RE: [PATCH v2 1/4] powercap/rapl: further relax energy counter checks

Quoted 11 lines

-----Original Message-----
From: David E. Box [mailto:[email protected]]
Sent: Wednesday, April 30, 2014 4:03 AM
To: [email protected]; [email protected]; linux- [email protected]; Wysocki, Rafael J; [email protected]; [email protected]
Cc: [email protected]; R, Durgadoss; Accardi, Kristen C
Subject: [PATCH v2 1/4] powercap/rapl: further relax energy counter checks

Quoted 8 lines

From: Jacob Pan <[email protected]>
Energy counters may roll slowly for some RAPL domains, checking all of them can be time consuming and takes unpredictable amount of time. Therefore, we relax the sanity check by only checking availability of the MSRs and non-zero value of the energy status counters. It has been shown sufficient for all the platforms tested to filter out inactive domains.

Acked-by Durgadoss R <[email protected]>

Thanks,
Durga

Quoted 66 lines

Signed-off-by Jacob Pan <[email protected]>

---
 drivers/powercap/intel_rapl.c |   29 +++++++++--------------------
 1 file changed, 9 insertions(+), 20 deletions(-)

drivers/powercap/intel_rapl.c +6 ~~-20~~

index d9a0770..1c987d2 100644
@@ -1124,8 +1124,7 @@ err_cleanup_package:
 static int rapl_check_domain(int cpu, int domain)
 {
 	unsigned msr;
-	u64 val1, val2 = 0;
-	int retry = 0;
+	u64 val = 0;
 
 	switch (domain) {
 	case RAPL_DOMAIN_PACKAGE:

@@ -1144,26 +1143,13 @@ static int rapl_check_domain(int cpu, int domain)
 		pr_err("invalid domain id %d\n", domain);
 		return -EINVAL;
 	}
-	if (rdmsrl_safe_on_cpu(cpu, msr, &val1))
-		return -ENODEV;
-
-	/* PP1/uncore/graphics domain may not be active at the time of
-	 * driver loading. So skip further checks.
+	/* make sure domain counters are available and contains non-zero
+	 * values, otherwise skip it.
 	 */
-	if (domain == RAPL_DOMAIN_PP1)
-		return 0;
-	/* energy counters roll slowly on some domains */
-	while (++retry < 10) {
-		usleep_range(10000, 15000);
-		rdmsrl_safe_on_cpu(cpu, msr, &val2);
-		if ((val1 & ENERGY_STATUS_MASK) != (val2 &
 ENERGY_STATUS_MASK))
-			return 0;
-	}
-	/* if energy counter does not change, report as bad domain */
-	pr_info("domain %s energy ctr %llu:%llu not working, skip\n",
-		rapl_domain_names[domain], val1, val2);
+	if (rdmsrl_safe_on_cpu(cpu, msr, &val) || !val)
+		return -ENODEV;
 
-	return -ENODEV;
+	return 0;
 }

/* Detect active and valid domains for the given CPU, caller must

drivers/powercap/intel_rapl.c +3 -0

@@ -1180,6 +1166,9 @@ static int rapl_detect_domains(struct rapl_package *rp,
 int cpu)
 		/* use physical package id to read counters */
 		if (!rapl_check_domain(cpu, i))
 			rp->domain_map |= 1 << i;
+		else
+			pr_warn("RAPL domain %s detection failed\n",
+				rapl_domain_names[i]);
 	}
 	rp->nr_domains = bitmap_weight(&rp->domain_map,

	RAPL_DOMAIN_MAX);

if (!rp->nr_domains) {
--
1.7.10.4

David E. Box

2014-04-29 22:33 UTC #13 lore raw

PATCH v2 2/4 powercap/rapl: add new cpu ids

From: Jacob Pan <[email protected]>

Adding support for Broadwell model 0x3d and HSW model (0x3c)

Signed-off-by Jacob Pan <[email protected]>

---
 drivers/powercap/intel_rapl.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

drivers/powercap/intel_rapl.c +3 -1

index 1c987d2..b1cda6f 100644
@@ -951,7 +951,9 @@ static const struct x86_cpu_id rapl_ids[] = {
 	{ X86_VENDOR_INTEL, 6, 0x2d},/* Sandy Bridge EP */
 	{ X86_VENDOR_INTEL, 6, 0x37},/* Valleyview */
 	{ X86_VENDOR_INTEL, 6, 0x3a},/* Ivy Bridge */
-	{ X86_VENDOR_INTEL, 6, 0x45},/* Haswell */
+	{ X86_VENDOR_INTEL, 6, 0x3c},/* Haswell */
+	{ X86_VENDOR_INTEL, 6, 0x3d},/* Broadwell */
+	{ X86_VENDOR_INTEL, 6, 0x45},/* Haswell ULT */
 	/* TODO: Add more CPU IDs after testing */
 	{}
 };

Signature · 1 line

1.7.10.4

David E. Box

2014-04-29 22:33 UTC #14 lore raw

PATCH v2 3/4 x86/iosf: Make IOSF driver modular and usable by more drivers

From: "David E. Box" <[email protected]>

Currently drivers that work on big core can't use the mailbox driver without selecting it which forces an unneeded dependency. Provides dummy fucntions to allow these modules to conditionally use the mailbox on soc's without limiting their ability to compile and load on big core systems. Make mailbox driver build default m to ensure availability on x86 SOC's.

---
 arch/x86/Kconfig                |    7 ++-----
 arch/x86/include/asm/iosf_mbi.h |   33 +++++++++++++++++++++++++++++++++
 arch/x86/kernel/iosf_mbi.c      |    6 ++++++
 3 files changed, 41 insertions(+), 5 deletions(-)

arch/x86/Kconfig +2 -5

index 25d2c6f..f1304d3 100644
@@ -2375,12 +2375,9 @@ config X86_DMA_REMAP
 	depends on STA2X11
 
 config IOSF_MBI
-	bool
+	tristate
+	default m
 	depends on PCI
-	---help---
-	  To be selected by modules requiring access to the Intel OnChip System
-	  Fabric (IOSF) Sideband MailBox Interface (MBI). For MBI platforms
-	  enumerable by PCI.
 
 source "net/Kconfig"

arch/x86/include/asm/iosf_mbi.h +33 -0

index 8e71c79..9e92d65 100644
@@ -50,6 +50,10 @@
 #define BT_MBI_PCIE_READ	0x00
 #define BT_MBI_PCIE_WRITE	0x01
 
+#if defined(CONFIG_IOSF_MBI) || defined(CONFIG_IOSF_MBI_MODULE)
+
+bool iosf_mbi_available(void);
+
 /**
  * iosf_mbi_read() - MailBox Interface read command
  * @port:	port indicating subunit being accessed

@@ -87,4 +91,33 @@ int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr);
  */
 int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask);
 
+#else /* CONFIG_IOSF_MBI is not enabled */
+static inline
+bool iosf_mbi_available(void)
+{
+	return false;
+}
+
+static inline
+int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
+{
+	WARN(1, "MBI driver not available");
+	return -EPERM;
+}
+
+static inline
+int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
+{
+	WARN(1, "MBI driver not available");
+	return -EPERM;
+}
+
+static inline
+int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
+{
+	WARN(1, "MBI driver not available");
+	return -EPERM;
+}
+#endif /* CONFIG_IOSF_MBI */
+
 #endif /* IOSF_MBI_SYMS_H */

arch/x86/kernel/iosf_mbi.c +6 -0

index c3aae66..d3803c6 100644
@@ -177,6 +177,12 @@ int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
 }
 EXPORT_SYMBOL(iosf_mbi_modify);
 
+bool iosf_mbi_available(void)
+{
+	return mbi_pdev;
+}
+EXPORT_SYMBOL(iosf_mbi_available);
+
 static int iosf_mbi_probe(struct pci_dev *pdev,
 			  const struct pci_device_id *unused)
 {

Signature · 1 line

1.7.10.4

David E. Box

2014-04-29 22:33 UTC #15 lore raw

PATCH v2 4/4 powercap/rapl: change floor frequency for vallewview

From: Jacob Pan <[email protected]>

RAPL power limit reduce power by limiting CPU P-state and other techniques. On Valleyview, RAPL power limit cannot go to LFM (low frequency mode) if we don't set the floor frequency via IOSF mailbox.

This patch enables setting of floor frquency such that RAPL power limit is more effective.

Signed-off-by Jacob Pan <[email protected]>

---
 drivers/powercap/intel_rapl.c |   27 +++++++++++++++++++--------
 1 file changed, 19 insertions(+), 8 deletions(-)

drivers/powercap/intel_rapl.c +19 -8

index b1cda6f..13e4776 100644
@@ -32,6 +32,7 @@
 
 #include <asm/processor.h>
 #include <asm/cpu_device_id.h>
+#include <asm/iosf_mbi.h>
 
 /* bitmasks for RAPL MSRs, used by primitive access functions */
 #define ENERGY_STATUS_MASK      0xffffffff

@@ -336,11 +337,17 @@ static int find_nr_power_limit(struct rapl_domain *rd)
 	return i;
 }
 
+#define VLV_CPU_POWER_BUDGET_CTL (0x2)
+static const struct x86_cpu_id valleyview_id[] = {
+	{ X86_VENDOR_INTEL, 6, 0x37},
+	{}
+};
+
 static int set_domain_enable(struct powercap_zone *power_zone, bool mode)
 {
 	struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
 	int nr_powerlimit;
-
+	u32 mdata = 0;
 	if (rd->state & DOMAIN_STATE_BIOS_LOCKED)
 		return -EACCES;
 	get_online_cpus();

@@ -350,7 +357,16 @@ static int set_domain_enable(struct powercap_zone *power_zone, bool mode)
 	/* always enable clamp such that p-state can go below OS requested
 	 * range. power capping priority over guranteed frequency.
 	 */
-	rapl_write_data_raw(rd, PL1_CLAMP, mode);
+	if (x86_match_cpu(valleyview_id)) {
+		iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_PMC_READ,
+			VLV_CPU_POWER_BUDGET_CTL, &mdata);
+		mdata &= ~(0x7f << 8);
+		mdata |= 1 << 8;
+		iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_PMC_WRITE,
+			VLV_CPU_POWER_BUDGET_CTL, mdata);
+	} else
+		rapl_write_data_raw(rd, PL1_CLAMP, mode);
+
 	/* some domains have pl2 */
 	if (nr_powerlimit > 1) {
 		rapl_write_data_raw(rd, PL2_ENABLE, mode);

@@ -833,11 +849,6 @@ static int rapl_write_data_raw(struct rapl_domain *rd,
 	return 0;
 }
 
-static const struct x86_cpu_id energy_unit_quirk_ids[] = {
-	{ X86_VENDOR_INTEL, 6, 0x37},/* Valleyview */
-	{}
-};
-
 static int rapl_check_unit(struct rapl_package *rp, int cpu)
 {
 	u64 msr_val;

@@ -859,7 +870,7 @@ static int rapl_check_unit(struct rapl_package *rp, int cpu)
 	 */
 	value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
 	/* some CPUs have different way to calculate energy unit */
-	if (x86_match_cpu(energy_unit_quirk_ids))
+	if (x86_match_cpu(valleyview_id))
 		rp->energy_unit_divisor = 1000000 / (1 << value);
 	else
 		rp->energy_unit_divisor = 1 << value;

Signature · 1 line

1.7.10.4

Rafael J. Wysocki

2014-04-29 22:46 UTC #16 lore raw

Quoted 11 lines · David E. Box

From: "David E. Box" <[email protected]>
v2: iosf: Remove Kconfig exposure. Make mailbox driver a module.
David E. Box (1):
x86/iosf: Make IOSF driver modular and usable by more drivers
Jacob Pan (3):
powercap/rapl: further relax energy counter checks powercap/rapl: add new cpu ids powercap/rapl: change floor frequency for vallewview

I'm fine with [1-2/4].

[3/4] has to go via the x86 tree and [4/4] probably too, because it depends on [3/4].

So would you like me to queue up [1-2/4] without the remaining two for 3.16?

Signature · 2 lines

I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.

Jacob Pan

author

2014-04-29 23:38 UTC #17 lore raw

Quoted 13 lines · On Wed, 30 Apr 2014 01:02:36 +0200 "Rafael J. Wysocki" <[email protected]>…

Quoted 11 lines · David E. Box
From: "David E. Box" <[email protected]>
v2: iosf: Remove Kconfig exposure. Make mailbox driver a module.
David E. Box (1):
x86/iosf: Make IOSF driver modular and usable by more drivers
Jacob Pan (3):
powercap/rapl: further relax energy counter checks powercap/rapl: add new cpu ids powercap/rapl: change floor frequency for vallewview

Quoted 5 lines

I'm fine with [1-2/4].
[3/4] has to go via the x86 tree and [4/4] probably too, because it depends on [3/4].

OK. I will update [4/4] to be submitted to x86 tree with [3/4].

Quoted 3 lines

So would you like me to queue up [1-2/4] without the remaining two for 3.16?

Sure. thanks.

Quoted 1 line

[Jacob Pan]

David E. Box

2014-05-02 17:39 UTC #18 lore raw

PATCH v3 1/1 x86/iosf: Make IOSF driver modular and usable by more drivers

From: "David E. Box" <[email protected]>

Currently drivers that run on non-IOSF systems (Core/Xeon) can't use the IOSF driver on SOC's without selecting it which forces an unnecessary and limiting dependency. Provides dummy functions to allow these modules to conditionally use the driver on IOSF equipped platforms without impacting their ability to compile and load on non-IOSF platforms. Build default m to ensure availability on x86 SOC's.

In reply to One Thousand Gnomes

---

v2: Remove Kconfig exposure. Make mailbox driver a module.

v3: Use IS_ENABLED macro and clarify commit message. Submit to x86.

 arch/x86/Kconfig                |  7 ++-----
 arch/x86/include/asm/iosf_mbi.h | 33 +++++++++++++++++++++++++++++++++
 arch/x86/kernel/iosf_mbi.c      |  6 ++++++
 3 files changed, 41 insertions(+), 5 deletions(-)

arch/x86/Kconfig +2 -5

index 0af5250..921d10a 100644
@@ -2413,12 +2413,9 @@ config X86_DMA_REMAP
 	depends on STA2X11
 
 config IOSF_MBI
-	bool
+	tristate
+	default m
 	depends on PCI
-	---help---
-	  To be selected by modules requiring access to the Intel OnChip System
-	  Fabric (IOSF) Sideband MailBox Interface (MBI). For MBI platforms
-	  enumerable by PCI.
 
 source "net/Kconfig"

arch/x86/include/asm/iosf_mbi.h +33 -0

index 8e71c79..1a91a36 100644
@@ -50,6 +50,10 @@
 #define BT_MBI_PCIE_READ	0x00
 #define BT_MBI_PCIE_WRITE	0x01
 
+#if IS_ENABLED(CONFIG_IOSF_MBI)
+
+bool iosf_mbi_available(void);
+
 /**
  * iosf_mbi_read() - MailBox Interface read command
  * @port:	port indicating subunit being accessed

@@ -87,4 +91,33 @@ int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr);
  */
 int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask);
 
+#else /* CONFIG_IOSF_MBI is not enabled */
+static inline
+bool iosf_mbi_available(void)
+{
+	return false;
+}
+
+static inline
+int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
+{
+	WARN(1, "IOSF_MBI driver not available");
+	return -EPERM;
+}
+
+static inline
+int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
+{
+	WARN(1, "IOSF_MBI driver not available");
+	return -EPERM;
+}
+
+static inline
+int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
+{
+	WARN(1, "IOSF_MBI driver not available");
+	return -EPERM;
+}
+#endif /* CONFIG_IOSF_MBI */
+
 #endif /* IOSF_MBI_SYMS_H */

arch/x86/kernel/iosf_mbi.c +6 -0

index c3aae66..d3803c6 100644
@@ -177,6 +177,12 @@ int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
 }
 EXPORT_SYMBOL(iosf_mbi_modify);
 
+bool iosf_mbi_available(void)
+{
+	return mbi_pdev;
+}
+EXPORT_SYMBOL(iosf_mbi_available);
+
 static int iosf_mbi_probe(struct pci_dev *pdev,
 			  const struct pci_device_id *unused)
 {

Signature · 1 line

1.8.5.4

One Thousand Gnomes

2014-05-07 16:48 UTC #19 lore raw

Re: [PATCH v3] x86/iosf: Make IOSF driver modular and usable by more drivers

On Fri, 2 May 2014 10:36:39 -0700

arch/x86/kernel/iosf_mbi.c int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask) · line 184

Quoted 5 lines

arch/x86/kernel/iosf_mbi.c +5 -0

+bool iosf_mbi_available(void)
+{
+	return mbi_pdev;
+}
+EXPORT_SYMBOL(iosf_mbi_available);

Probably worth a follow up patch that comments this so the assumption that iosf can never be unloaded or hot-unplugged is clear.

Alan

H. Peter Anvin

reviewer

2014-05-07 17:05 UTC #20 lore raw

Re: [PATCH v3] x86/iosf: Make IOSF driver modular and usable by more drivers

Quoted 10 lines · One Thousand Gnomes

On Fri, 2 May 2014 10:36:39 -0700
arch/x86/kernel/iosf_mbi.c int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask) · line 184
Quoted 5 lines
arch/x86/kernel/iosf_mbi.c +5 -0
+bool iosf_mbi_available(void)
+{
+	return mbi_pdev;
+}
+EXPORT_SYMBOL(iosf_mbi_available);
Probably worth a follow up patch that comments this so the assumption that iosf can never be unloaded or hot-unplugged is clear.

When you say unloaded you mean the module or the hardware?

-hpa

One Thousand Gnomes

2014-05-07 17:11 UTC #21 lore raw

Re: [PATCH v3] x86/iosf: Make IOSF driver modular and usable by more drivers

Quoted 12 lines · On Wed, 07 May 2014 10:04:56 -0700 "H. Peter Anvin" <[email protected]> wrote:

Quoted 10 lines · One Thousand Gnomes
On Fri, 2 May 2014 10:36:39 -0700
arch/x86/kernel/iosf_mbi.c int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask) · line 184
Quoted 5 lines
arch/x86/kernel/iosf_mbi.c +5 -0
+bool iosf_mbi_available(void)
+{
+	return mbi_pdev;
+}
+EXPORT_SYMBOL(iosf_mbi_available);
Probably worth a follow up patch that comments this so the assumption that iosf can never be unloaded or hot-unplugged is clear.

Quoted 1 line

When you say unloaded you mean the module or the hardware?

Both. Currently the hardware isn't removable (but could be virtually removed by playing with unplugging) and the module can't be unloaded so the assumption is fine.

Alan

H. Peter Anvin

reviewer

2014-05-07 17:14 UTC #22 lore raw

Re: [PATCH v3] x86/iosf: Make IOSF driver modular and usable by more drivers

Quoted 15 lines · One Thousand Gnomes

Quoted 12 lines · On Wed, 07 May 2014 10:04:56 -0700 "H. Peter Anvin" <[email protected]> wrote:
Quoted 10 lines · One Thousand Gnomes
On Fri, 2 May 2014 10:36:39 -0700
arch/x86/kernel/iosf_mbi.c int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask) · line 184
Quoted 5 lines
arch/x86/kernel/iosf_mbi.c +5 -0
+bool iosf_mbi_available(void)
+{
+	return mbi_pdev;
+}
+EXPORT_SYMBOL(iosf_mbi_available);
Probably worth a follow up patch that comments this so the assumption that iosf can never be unloaded or hot-unplugged is clear.

Quoted 6 lines

Quoted 1 line
When you say unloaded you mean the module or the hardware?
Both. Currently the hardware isn't removable (but could be virtually removed by playing with unplugging) and the module can't be unloaded so the assumption is fine.

I guess I don't see why the module isn't removable. Of course, any driver which calls iosf_mbi_available() will depend on it, preventing removal until *those* modules have been removed...

-hpa

One Thousand Gnomes

2014-05-07 18:58 UTC #23 lore raw

Re: [PATCH v3] x86/iosf: Make IOSF driver modular and usable by more drivers

Quoted 3 lines

I guess I don't see why the module isn't removable. Of course, any driver which calls iosf_mbi_available() will depend on it, preventing removal until *those* modules have been removed...

Going back over the current version you could unload it but you rely upon the iosf_mbi_available caller locking the module in memory (which I think is fair) and someone not forcing a hot unplug of any kind from userspace, in which case life gets a bit odd as we clear mbi_pdev in the exit method not when the device is unplugged. Probably for the best as with a remove method you'd need to check the mbi_pdev pointer inside iosf_mbi_lock and also clear it under the lock.

Alan

David E. Box

2014-05-07 18:03 UTC #24 lore raw

Re: [PATCH v3] x86/iosf: Make IOSF driver modular and usable by more drivers

Quoted 15 lines · One Thousand Gnomes

Quoted 12 lines · On Wed, 07 May 2014 10:04:56 -0700 "H. Peter Anvin" <[email protected]> wrote:
Quoted 10 lines · One Thousand Gnomes
On Fri, 2 May 2014 10:36:39 -0700
arch/x86/kernel/iosf_mbi.c int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask) · line 184
Quoted 5 lines
arch/x86/kernel/iosf_mbi.c +5 -0
+bool iosf_mbi_available(void)
+{
+	return mbi_pdev;
+}
+EXPORT_SYMBOL(iosf_mbi_available);
Probably worth a follow up patch that comments this so the assumption that iosf can never be unloaded or hot-unplugged is clear.

Quoted 6 lines

Quoted 1 line
When you say unloaded you mean the module or the hardware?
Both. Currently the hardware isn't removable (but could be virtually removed by playing with unplugging) and the module can't be unloaded so the assumption is fine.

Actually it can be explictly unloaded with rmmod, something I left in while testing use of the driver on non-iosf systems.

Speaking of non-iosf systems (Core/Xeon), having the iosf driver configured as default m will cause it to be loaded on non-iosf systems by drivers that work on both. Not a huge problem. I already tested that attempts to use the driver result in proper warnings with ill affect to those systems. But it is a waste of memory. I looked at doing a probe and unload in module_init but that would cause these drivers, like RAPL for example, to fail due to the missing iosf symbols, which the driver would still be looking for because default m means that CONFIG_IOSF is always true so they aren't compiled out out in exchange for the dummy ones.

Imo, this stems from not exposing the iosf in Kconfig. I understand the reasoning but maybe there should be a separate Kconfig option that is exposed indicating that the hardware is an x86 SOC. The iosf could have just depended on that, avoiding this situation.

Dave Box

David E. Box

2014-05-09 20:46 UTC #25 lore raw

v4 cover x86/iosf: IOSF additional driver/device support

From: "David E. Box" <[email protected]>

v2: Remove Kconfig exposure. Make mailbox driver a module.

v3: Use IS_ENABLED macro and clarify commit message. Submit to x86.

v4: Add comment making clear mbi iosf device isn't hot-pluggable.
Add patch set for Quark support from Ong Boon Leong.

David E. Box (1):
x86/iosf: Make IOSF driver modular and usable by more drivers

Ong Boon Leong (3):
arch: x86: added Quark MBI support
arch: x86: iosf_mbi: add Quark X1000 pci id
arch: x86: iosf_mbi: add pci id macros for better readability

 arch/x86/Kconfig                |    7 ++---
 arch/x86/include/asm/iosf_mbi.h |   55 +++++++++++++++++++++++++++++++++++++++
 arch/x86/kernel/iosf_mbi.c      |   13 ++++++++-
 3 files changed, 69 insertions(+), 6 deletions(-)

Signature · 1 line

1.7.10.4

David E. Box

2014-05-09 20:46 UTC #26 lore raw

PATCH v4 1/4 x86/iosf: Make IOSF driver modular and usable by more drivers

From: "David E. Box" <[email protected]>

---
 arch/x86/Kconfig                |    7 ++-----
 arch/x86/include/asm/iosf_mbi.h |   33 +++++++++++++++++++++++++++++++++
 arch/x86/kernel/iosf_mbi.c      |    7 +++++++
 3 files changed, 42 insertions(+), 5 deletions(-)

arch/x86/Kconfig +2 -5

index 25d2c6f..f1304d3 100644
@@ -2375,12 +2375,9 @@ config X86_DMA_REMAP
 	depends on STA2X11
 
 config IOSF_MBI
-	bool
+	tristate
+	default m
 	depends on PCI
-	---help---
-	  To be selected by modules requiring access to the Intel OnChip System
-	  Fabric (IOSF) Sideband MailBox Interface (MBI). For MBI platforms
-	  enumerable by PCI.
 
 source "net/Kconfig"

arch/x86/include/asm/iosf_mbi.h +33 -0

index 8e71c79..1a91a36 100644
@@ -50,6 +50,10 @@
 #define BT_MBI_PCIE_READ	0x00
 #define BT_MBI_PCIE_WRITE	0x01
 
+#if IS_ENABLED(CONFIG_IOSF_MBI)
+
+bool iosf_mbi_available(void);
+
 /**
  * iosf_mbi_read() - MailBox Interface read command
  * @port:	port indicating subunit being accessed

@@ -87,4 +91,33 @@ int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr);
  */
 int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask);
 
+#else /* CONFIG_IOSF_MBI is not enabled */
+static inline
+bool iosf_mbi_available(void)
+{
+	return false;
+}
+
+static inline
+int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
+{
+	WARN(1, "IOSF_MBI driver not available");
+	return -EPERM;
+}
+
+static inline
+int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
+{
+	WARN(1, "IOSF_MBI driver not available");
+	return -EPERM;
+}
+
+static inline
+int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
+{
+	WARN(1, "IOSF_MBI driver not available");
+	return -EPERM;
+}
+#endif /* CONFIG_IOSF_MBI */
+
 #endif /* IOSF_MBI_SYMS_H */

arch/x86/kernel/iosf_mbi.c +7 -0

index c3aae66..f4ff978 100644
@@ -177,6 +177,13 @@ int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
 }
 EXPORT_SYMBOL(iosf_mbi_modify);
 
+bool iosf_mbi_available(void)
+{
+	/* Mbi isn't hot-pluggable. No remove routine is provided */
+	return mbi_pdev;
+}
+EXPORT_SYMBOL(iosf_mbi_available);
+
 static int iosf_mbi_probe(struct pci_dev *pdev,
 			  const struct pci_device_id *unused)
 {

Signature · 1 line

1.7.10.4

tip-bot for David E. Box

merge bot

2014-05-28 21:24 UTC #27 lore raw

[tip:x86/platform] x86, iosf: Make IOSF driver modular and usable by more drivers

x86, iosf: Make IOSF driver modular and usable by more drivers

Commit-ID:  6b8f0c8780c71d78624f736d7849645b64cc88b7
Gitweb:     http://git.kernel.org/tip/6b8f0c8780c71d78624f736d7849645b64cc88b7
Author:     David E. Box <[email protected]>
AuthorDate: Fri, 9 May 2014 13:44:05 -0700
Committer:  H. Peter Anvin <[email protected]>
CommitDate: Fri, 9 May 2014 14:56:15 -0700

x86, iosf: Make IOSF driver modular and usable by more drivers

Link http://lkml.kernel.org/r/[email protected] open here

---
 arch/x86/Kconfig                |  7 ++-----
 arch/x86/include/asm/iosf_mbi.h | 33 +++++++++++++++++++++++++++++++++
 arch/x86/kernel/iosf_mbi.c      |  7 +++++++
 3 files changed, 42 insertions(+), 5 deletions(-)

arch/x86/Kconfig +2 -5

index 25d2c6f..f1304d3 100644
@@ -2375,12 +2375,9 @@ config X86_DMA_REMAP
 	depends on STA2X11
 
 config IOSF_MBI
-	bool
+	tristate
+	default m
 	depends on PCI
-	---help---
-	  To be selected by modules requiring access to the Intel OnChip System
-	  Fabric (IOSF) Sideband MailBox Interface (MBI). For MBI platforms
-	  enumerable by PCI.
 
 source "net/Kconfig"

arch/x86/include/asm/iosf_mbi.h +33 -0

index 8e71c79..1a91a36 100644
@@ -50,6 +50,10 @@
 #define BT_MBI_PCIE_READ	0x00
 #define BT_MBI_PCIE_WRITE	0x01
 
+#if IS_ENABLED(CONFIG_IOSF_MBI)
+
+bool iosf_mbi_available(void);
+
 /**
  * iosf_mbi_read() - MailBox Interface read command
  * @port:	port indicating subunit being accessed

@@ -87,4 +91,33 @@ int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr);
  */
 int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask);
 
+#else /* CONFIG_IOSF_MBI is not enabled */
+static inline
+bool iosf_mbi_available(void)
+{
+	return false;
+}
+
+static inline
+int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
+{
+	WARN(1, "IOSF_MBI driver not available");
+	return -EPERM;
+}
+
+static inline
+int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
+{
+	WARN(1, "IOSF_MBI driver not available");
+	return -EPERM;
+}
+
+static inline
+int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
+{
+	WARN(1, "IOSF_MBI driver not available");
+	return -EPERM;
+}
+#endif /* CONFIG_IOSF_MBI */
+
 #endif /* IOSF_MBI_SYMS_H */

arch/x86/kernel/iosf_mbi.c +7 -0

index c3aae66..f4ff978 100644
@@ -177,6 +177,13 @@ int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
 }
 EXPORT_SYMBOL(iosf_mbi_modify);
 
+bool iosf_mbi_available(void)
+{
+	/* Mbi isn't hot-pluggable. No remove routine is provided */
+	return mbi_pdev;
+}
+EXPORT_SYMBOL(iosf_mbi_available);
+
 static int iosf_mbi_probe(struct pci_dev *pdev,
 			  const struct pci_device_id *unused)
 {

David E. Box

2014-05-09 20:46 UTC #28 lore raw

PATCH v4 2/4 arch: x86: added Quark MBI support

From: Ong Boon Leong <[email protected]>

Added all the MBI units below and their associated read/write opcodes:
- Host Bridge Arbiter
- Host Bridge
- Remote Management Unit
- Memory Manager & eSRAM
- SoC Unit

---
 arch/x86/include/asm/iosf_mbi.h |   22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

arch/x86/include/asm/iosf_mbi.h +22 -0

index 1a91a36..57995f0 100644
@@ -50,6 +50,28 @@
 #define BT_MBI_PCIE_READ	0x00
 #define BT_MBI_PCIE_WRITE	0x01
 
+/* Quark available units */
+#define QRK_MBI_UNIT_HBA	0x00
+#define QRK_MBI_UNIT_HB	0x03
+#define QRK_MBI_UNIT_RMU	0x04
+#define QRK_MBI_UNIT_MM	0x05
+#define QRK_MBI_UNIT_MMESRAM	0x05
+#define QRK_MBI_UNIT_SOC	0x31
+
+/* Quark read/write opcodes */
+#define QRK_MBI_HBA_READ	0x10
+#define QRK_MBI_HBA_WRITE	0x11
+#define QRK_MBI_HB_READ	0x10
+#define QRK_MBI_HB_WRITE	0x11
+#define QRK_MBI_RMU_READ	0x10
+#define QRK_MBI_RMU_WRITE	0x11
+#define QRK_MBI_MM_READ	0x10
+#define QRK_MBI_MM_WRITE	0x11
+#define QRK_MBI_MMESRAM_READ	0x12
+#define QRK_MBI_MMESRAM_WRITE	0x13
+#define QRK_MBI_SOC_READ	0x06
+#define QRK_MBI_SOC_WRITE	0x07
+
 #if IS_ENABLED(CONFIG_IOSF_MBI)
 
 bool iosf_mbi_available(void);

Signature · 1 line

1.7.10.4

tip-bot for Ong Boon Leong

merge bot

2014-05-28 21:25 UTC #29 lore raw

[tip:x86/platform] x86, iosf: Added Quark MBI identifiers

x86, iosf: Added Quark MBI identifiers

Commit-ID:  7ef1def800e907edd28ddb1a5c64bae6b8749cdd
Gitweb:     http://git.kernel.org/tip/7ef1def800e907edd28ddb1a5c64bae6b8749cdd
Author:     Ong Boon Leong <[email protected]>
AuthorDate: Fri, 9 May 2014 13:44:06 -0700
Committer:  H. Peter Anvin <[email protected]>
CommitDate: Fri, 9 May 2014 14:57:08 -0700

x86, iosf: Added Quark MBI identifiers

Added all the MBI units below and their associated read/write opcodes:
- Host Bridge Arbiter
- Host Bridge
- Remote Management Unit
- Memory Manager & eSRAM
- SoC Unit

Link http://lkml.kernel.org/r/[email protected] open here

---
 arch/x86/include/asm/iosf_mbi.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

arch/x86/include/asm/iosf_mbi.h +22 -0

index 1a91a36..57995f0 100644
@@ -50,6 +50,28 @@
 #define BT_MBI_PCIE_READ	0x00
 #define BT_MBI_PCIE_WRITE	0x01
 
+/* Quark available units */
+#define QRK_MBI_UNIT_HBA	0x00
+#define QRK_MBI_UNIT_HB	0x03
+#define QRK_MBI_UNIT_RMU	0x04
+#define QRK_MBI_UNIT_MM	0x05
+#define QRK_MBI_UNIT_MMESRAM	0x05
+#define QRK_MBI_UNIT_SOC	0x31
+
+/* Quark read/write opcodes */
+#define QRK_MBI_HBA_READ	0x10
+#define QRK_MBI_HBA_WRITE	0x11
+#define QRK_MBI_HB_READ	0x10
+#define QRK_MBI_HB_WRITE	0x11
+#define QRK_MBI_RMU_READ	0x10
+#define QRK_MBI_RMU_WRITE	0x11
+#define QRK_MBI_MM_READ	0x10
+#define QRK_MBI_MM_WRITE	0x11
+#define QRK_MBI_MMESRAM_READ	0x12
+#define QRK_MBI_MMESRAM_WRITE	0x13
+#define QRK_MBI_SOC_READ	0x06
+#define QRK_MBI_SOC_WRITE	0x07
+
 #if IS_ENABLED(CONFIG_IOSF_MBI)
 
 bool iosf_mbi_available(void);

David E. Box

2014-05-09 20:47 UTC #30 lore raw

PATCH v4 3/4 arch: x86: iosf_mbi: add Quark X1000 pci id

From: Ong Boon Leong <[email protected]>

Add PCI device ID, i.e. that of the Host Bridge,
for IOSF MBI driver.

---
 arch/x86/kernel/iosf_mbi.c |    1 +
 1 file changed, 1 insertion(+)

arch/x86/kernel/iosf_mbi.c +1 -0

index f4ff978..201a7ab 100644
@@ -201,6 +201,7 @@ static int iosf_mbi_probe(struct pci_dev *pdev,
 
 static DEFINE_PCI_DEVICE_TABLE(iosf_mbi_pci_ids) = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0F00) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0958) },
 	{ 0, },
 };
 MODULE_DEVICE_TABLE(pci, iosf_mbi_pci_ids);

Signature · 1 line

1.7.10.4

tip-bot for Ong Boon Leong

merge bot

2014-05-28 21:25 UTC #31 lore raw

[tip:x86/platform] x86, iosf: Add Quark X1000 PCI ID

x86, iosf: Add Quark X1000 PCI ID

Commit-ID:  90916e048c1e0c1d379577e43ab9b8e331490cfb
Gitweb:     http://git.kernel.org/tip/90916e048c1e0c1d379577e43ab9b8e331490cfb
Author:     Ong Boon Leong <[email protected]>
AuthorDate: Fri, 9 May 2014 13:44:07 -0700
Committer:  H. Peter Anvin <[email protected]>
CommitDate: Fri, 9 May 2014 14:57:23 -0700

x86, iosf: Add Quark X1000 PCI ID

Add PCI device ID, i.e. that of the Host Bridge, for IOSF MBI driver.

Link http://lkml.kernel.org/r/[email protected] open here

---
 arch/x86/kernel/iosf_mbi.c | 1 +
 1 file changed, 1 insertion(+)

arch/x86/kernel/iosf_mbi.c +1 -0

index f4ff978..201a7ab 100644
@@ -201,6 +201,7 @@ static int iosf_mbi_probe(struct pci_dev *pdev,
 
 static DEFINE_PCI_DEVICE_TABLE(iosf_mbi_pci_ids) = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0F00) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0958) },
 	{ 0, },
 };
 MODULE_DEVICE_TABLE(pci, iosf_mbi_pci_ids);

David E. Box

2014-05-09 20:47 UTC #32 lore raw

PATCH v4 4/4 arch: x86: iosf_mbi: add pci id macros for better readability

From: Ong Boon Leong <[email protected]>

Introduce PCI IDs macro for the list of supported product:
BayTrail & Quark X1000.

---
 arch/x86/kernel/iosf_mbi.c |    7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

arch/x86/kernel/iosf_mbi.c +5 -2

index 201a7ab..d30acdc 100644
@@ -25,6 +25,9 @@
 
 #include <asm/iosf_mbi.h>
 
+#define PCI_DEVICE_ID_BAYTRAIL		0x0F00
+#define PCI_DEVICE_ID_QUARK_X1000	0x0958
+
 static DEFINE_SPINLOCK(iosf_mbi_lock);
 
 static inline u32 iosf_mbi_form_mcr(u8 op, u8 port, u8 offset)

@@ -200,8 +203,8 @@ static int iosf_mbi_probe(struct pci_dev *pdev,
 }
 
 static DEFINE_PCI_DEVICE_TABLE(iosf_mbi_pci_ids) = {
-	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0F00) },
-	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0958) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BAYTRAIL) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_QUARK_X1000) },
 	{ 0, },
 };
 MODULE_DEVICE_TABLE(pci, iosf_mbi_pci_ids);

Signature · 1 line

1.7.10.4

tip-bot for Ong Boon Leong

merge bot

2014-05-28 21:25 UTC #33 lore raw

[tip:x86/platform] x86, iosf: Add PCI ID macros for better readability

x86, iosf: Add PCI ID macros for better readability

Commit-ID:  04725ad59474d24553d526fa774179ecd2922342
Gitweb:     http://git.kernel.org/tip/04725ad59474d24553d526fa774179ecd2922342
Author:     Ong Boon Leong <[email protected]>
AuthorDate: Fri, 9 May 2014 13:44:08 -0700
Committer:  H. Peter Anvin <[email protected]>
CommitDate: Fri, 9 May 2014 14:57:35 -0700

x86, iosf: Add PCI ID macros for better readability

Introduce PCI IDs macro for the list of supported product:
BayTrail & Quark X1000.

Link http://lkml.kernel.org/r/[email protected] open here