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ARM: dts: imx6: edmqmx6: add pinctrl for pfuze irq gpio

PATCH New Lucas Stach 2 participants 3 messages May 7, 2014 – May 8, 2014

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Device tree bindings Arm i.MX and Layerscape
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Lucas Stach

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#0 lore raw

PATCH 1/2 ARM: dts: imx6: edmqmx6: add pinctrl for pfuze irq gpio

Signed-off-by Lucas Stach <[email protected]>
---
 arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)
arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +8 -1
index e4ae38fd0269..be5de70fe86a 100644
@@ -105,7 +105,8 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_i2c2
 		     &pinctrl_stmpe1
-		     &pinctrl_stmpe2>;
+		     &pinctrl_stmpe2
+		     &pinctrl_pfuze>;
 	status = "okay";
 
 	pmic: pfuze100 at 08 {

@@ -291,6 +292,12 @@
 			>;
 		};
 
+		pinctrl_pfuze: pfuze100grp1 {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D20__GPIO3_IO20		0x80000000
+			>;
+		};
+
 		pinctrl_stmpe1: stmpe1grp {
 			fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>;
 		};
Signature · 1 line
2.0.0.rc0
author
#1 lore raw

PATCH 2/2 ARM: dts: imx6: edmqmx6: add SPI bus and flash

Signed-off-by Lucas Stach <[email protected]>
---
 arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +23 -0
index be5de70fe86a..58791d0eaaf8 100644
@@ -91,6 +91,20 @@
 	};
 };
 
+&ecspi5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi5>;
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio1 12 0>;
+	status = "okay";
+
+	flash: m25p80 at 0 {
+		compatible = "m25p80";
+		spi-max-frequency = <40000000>;
+		reg = <0>;
+	};
+};
+
 &fec {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet>;

@@ -264,6 +278,15 @@
 			>;
 		};
 
+		pinctrl_ecspi5: ecspi5rp-1 {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO	0x80000000
+				MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI		0x80000000
+				MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK		0x80000000
+				MX6QDL_PAD_SD2_DAT3__GPIO1_IO12		0x80000000
+			>;
+		};
+
 		pinctrl_enet: enetgrp {
 			fsl,pins = <
 				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
Signature · 1 line
2.0.0.rc0