arm: Add basic support for Mediatek Cortex-A7 SoCs

This patch adds a clock source and clock event for the timer found on the Mediatek SoCs.

The Mediatek General Porpose Timer block provides five 32 bit timers and one 64 bit timer.

Two 32 bit timers are used:
TIMER1: clock events supporting periodic and oneshot events
TIMER2: clock source configured as a free running counter

The General Porpose Timer block can be run with two clocks. A 13 MHz system clock and the RTC clock running at 32 KHz. This implementation uses the system clock.

Signed-off-by Matthias Brugger <[email protected]>

---
 drivers/clocksource/Kconfig     |   4 +
 drivers/clocksource/Makefile    |   1 +
 drivers/clocksource/mtk_timer.c | 263 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 268 insertions(+)
 create mode 100644 drivers/clocksource/mtk_timer.c

drivers/clocksource/Kconfig +4 -0

index 96918e1..1f73740 100644
@@ -144,6 +144,10 @@ config VF_PIT_TIMER
 config SYS_SUPPORTS_SH_CMT
         bool
 
+config MTK_TIMER
+	select CLKSRC_MMIO
+	bool
+
 config SYS_SUPPORTS_SH_MTU2
         bool
 

drivers/clocksource/Makefile +1 -0

index 98cb6c5..619d302 100644
@@ -33,6 +33,7 @@ obj-$(CONFIG_CLKSRC_EXYNOS_MCT)	+= exynos_mct.o
 obj-$(CONFIG_CLKSRC_SAMSUNG_PWM)	+= samsung_pwm_timer.o
 obj-$(CONFIG_VF_PIT_TIMER)	+= vf_pit_timer.o
 obj-$(CONFIG_CLKSRC_QCOM)	+= qcom-timer.o
+obj-$(CONFIG_MTK_TIMER)		+= mtk_timer.o
 
 obj-$(CONFIG_ARM_ARCH_TIMER)		+= arm_arch_timer.o
 obj-$(CONFIG_ARM_GLOBAL_TIMER)		+= arm_global_timer.o

drivers/clocksource/mtk_timer.c new file +190 -0

new file mode 100644
index 0000000..4b88065
@@ -0,0 +1,263 @@
+/*
+ * Mediatek SoCs General-Purpose Timer handling.
+ *
+ * Copyright (C) 2014 Matthias Brugger
+ *
+ * Matthias Brugger <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqreturn.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+
+#define GPT_IRQ_EN_REG		0x00
+#define GPT_IRQ_ENABLE(val)	BIT(val-1)
+#define GPT_IRQ_ST_REG		0x04
+#define GPT_IRQ_ACK_REG		0x08
+#define GPT_IRQ_ACK(val)	BIT(val-1)
+
+#define TIMER_CTRL_REG(val)	(0x10 * val)
+#define TIMER_CTRL_OP(val)	(((val) & 0x3) << 4)
+#define TIMER_CTRL_OP_ONESHOT	(0)
+#define TIMER_CTRL_OP_REPEAT	(1)
+#define TIMER_CTRL_OP_KEEPGO	(2)
+#define TIMER_CTRL_OP_FREERUN	(3)
+#define TIMER_CTRL_CLEAR	(2)
+#define TIMER_CTRL_ENABLE	(1)
+#define TIMER_CTRL_DISABLE	(0)
+
+#define TIMER_CLK_REG(val)	(0x04 + (0x10 * val))
+#define TIMER_CLK_SRC(val)	(((val) & 0x1) << 4)
+#define TIMER_CLK_SRC_SYS13M	(0)
+#define TIMER_CLK_SRC_RTC32K	(1)
+#define TIMER_CLK_DIV1		(0x0)
+#define TIMER_CLK_DIV2		(0x1)
+#define TIMER_CLK_DIV3		(0x2)
+#define TIMER_CLK_DIV4		(0x3)
+#define TIMER_CLK_DIV5		(0x4)
+#define TIMER_CLK_DIV6		(0x5)
+#define TIMER_CLK_DIV7		(0x6)
+#define TIMER_CLK_DIV8		(0x7)
+#define TIMER_CLK_DIV9		(0x8)
+#define TIMER_CLK_DIV10		(0x9)
+#define TIMER_CLK_DIV11		(0xA)
+#define TIMER_CLK_DIV12		(0xB)
+#define TIMER_CLK_DIV13		(0xC)
+#define TIMER_CLK_DIV16		(0xD)
+#define TIMER_CLK_DIV32		(0xE)
+#define TIMER_CLK_DIV64		(0xF)
+
+#define TIMER_CNT_REG(val)	(0x08 + (0x10 * val))
+#define TIMER_CMP_REG(val)	(0x0C + (0x10 * val))
+
+#define GPT_CLK_EVT	1
+#define GPT_CLK_SRC	2
+
+
+
+struct mtk_clock_event_device {
+	void __iomem *gpt_base;
+	u32 ticks_per_jiffy;
+	struct clock_event_device dev;
+};
+
+static inline struct mtk_clock_event_device *to_mtk_clk(
+				struct clock_event_device *c)
+{
+	return container_of(c, struct mtk_clock_event_device, dev);
+}
+
+static void mtk_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer)
+{
+	u32 val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
+	writel(val & ~TIMER_CTRL_ENABLE, evt->gpt_base +
+			TIMER_CTRL_REG(timer));
+}
+
+static void mtk_clkevt_time_setup(struct mtk_clock_event_device *evt,
+				unsigned long delay, u8 timer)
+{
+	writel(delay, evt->gpt_base + TIMER_CMP_REG(timer));
+}
+
+static void mtk_clkevt_time_start(struct mtk_clock_event_device *evt,
+		bool periodic, u8 timer)
+{
+	u32 val;
+
+	/* Acknowledge interrupt */
+	writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG);
+
+	val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
+
+	/* Clear 2 bit timer operation mode field */
+	val &= ~TIMER_CTRL_OP(0x3);
+
+	if (periodic)
+		val |= TIMER_CTRL_OP(TIMER_CTRL_OP_REPEAT);
+	else
+		val |= TIMER_CTRL_OP(TIMER_CTRL_OP_ONESHOT);
+
+	writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR,
+	       evt->gpt_base + TIMER_CTRL_REG(timer));
+}
+
+static void mtk_clkevt_mode(enum clock_event_mode mode,
+				struct clock_event_device *clk)
+{
+	struct mtk_clock_event_device *evt = to_mtk_clk(clk);
+
+	mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
+
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+		mtk_clkevt_time_setup(evt, evt->ticks_per_jiffy, GPT_CLK_EVT);
+		mtk_clkevt_time_start(evt, true, GPT_CLK_EVT);
+		break;
+	case CLOCK_EVT_MODE_ONESHOT:
+		mtk_clkevt_time_start(evt, false, GPT_CLK_EVT);
+		break;
+	case CLOCK_EVT_MODE_UNUSED:
+	case CLOCK_EVT_MODE_SHUTDOWN:
+	default:
+		/* No more interrupts will occur as source is disabled */
+		break;
+	}
+}
+
+static int mtk_clkevt_next_event(unsigned long event,
+				   struct clock_event_device *clk)
+{
+	struct mtk_clock_event_device *evt = to_mtk_clk(clk);
+
+	mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
+	mtk_clkevt_time_setup(evt, event, GPT_CLK_EVT);
+	mtk_clkevt_time_start(evt, false, GPT_CLK_EVT);
+
+	return 0;
+}
+
+static irqreturn_t mtk_timer_interrupt(int irq, void *dev_id)
+{
+	struct mtk_clock_event_device *evt = dev_id;
+
+	/* Acknowledge timer0 irq */
+	writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG);
+	evt->dev.event_handler(&evt->dev);
+
+	return IRQ_HANDLED;
+}
+
+static void mtk_timer_global_reset(struct mtk_clock_event_device *evt)
+{
+	/* Disable all interrupts */
+	writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG);
+	/* Acknowledge all interrupts */
+	writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG);
+}
+
+static void mtk_timer_reset(struct mtk_clock_event_device *evt, u8 timer)
+{
+	writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE,
+		evt->gpt_base + TIMER_CTRL_REG(timer));
+	writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer));
+}
+
+static void __init mtk_timer_init(struct device_node *node)
+{
+	struct mtk_clock_event_device *evt;
+	struct resource res;
+	unsigned long rate = 0;
+	struct clk *clk;
+	int ret;
+	u32 val;
+

Quoted 250 lines

This patch adds a clock source and clock event for the timer found on the Mediatek SoCs.

The Mediatek General Porpose Timer block provides five 32 bit timers and one 64 bit timer.

Two 32 bit timers are used:
TIMER1: clock events supporting periodic and oneshot events
TIMER2: clock source configured as a free running counter

The General Porpose Timer block can be run with two clocks. A 13 MHz system clock and the RTC clock running at 32 KHz. This implementation uses the system clock.

Signed-off-by Matthias Brugger <[email protected]>

---
 drivers/clocksource/Kconfig     |   4 +
 drivers/clocksource/Makefile    |   1 +
 drivers/clocksource/mtk_timer.c | 263 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 268 insertions(+)
 create mode 100644 drivers/clocksource/mtk_timer.c

drivers/clocksource/Kconfig +4 -0

index 96918e1..1f73740 100644
@@ -144,6 +144,10 @@ config VF_PIT_TIMER
 config SYS_SUPPORTS_SH_CMT
         bool
 
+config MTK_TIMER
+     select CLKSRC_MMIO
+     bool
+
 config SYS_SUPPORTS_SH_MTU2
         bool
 

drivers/clocksource/Makefile +1 -0

index 98cb6c5..619d302 100644
@@ -33,6 +33,7 @@ obj-$(CONFIG_CLKSRC_EXYNOS_MCT)     += exynos_mct.o
 obj-$(CONFIG_CLKSRC_SAMSUNG_PWM)     += samsung_pwm_timer.o
 obj-$(CONFIG_VF_PIT_TIMER)   += vf_pit_timer.o
 obj-$(CONFIG_CLKSRC_QCOM)    += qcom-timer.o
+obj-$(CONFIG_MTK_TIMER)              += mtk_timer.o
 
 obj-$(CONFIG_ARM_ARCH_TIMER)         += arm_arch_timer.o
 obj-$(CONFIG_ARM_GLOBAL_TIMER)               += arm_global_timer.o

drivers/clocksource/mtk_timer.c new file +195 -0

new file mode 100644
index 0000000..4b88065
@@ -0,0 +1,263 @@
+/*
+ * Mediatek SoCs General-Purpose Timer handling.
+ *
+ * Copyright (C) 2014 Matthias Brugger
+ *
+ * Matthias Brugger <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqreturn.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+
+#define GPT_IRQ_EN_REG               0x00
+#define GPT_IRQ_ENABLE(val)  BIT(val-1)
+#define GPT_IRQ_ST_REG               0x04
+#define GPT_IRQ_ACK_REG              0x08
+#define GPT_IRQ_ACK(val)     BIT(val-1)
+
+#define TIMER_CTRL_REG(val)  (0x10 * val)
+#define TIMER_CTRL_OP(val)   (((val) & 0x3) << 4)
+#define TIMER_CTRL_OP_ONESHOT        (0)
+#define TIMER_CTRL_OP_REPEAT (1)
+#define TIMER_CTRL_OP_KEEPGO (2)
+#define TIMER_CTRL_OP_FREERUN        (3)
+#define TIMER_CTRL_CLEAR     (2)
+#define TIMER_CTRL_ENABLE    (1)
+#define TIMER_CTRL_DISABLE   (0)
+
+#define TIMER_CLK_REG(val)   (0x04 + (0x10 * val))
+#define TIMER_CLK_SRC(val)   (((val) & 0x1) << 4)
+#define TIMER_CLK_SRC_SYS13M (0)
+#define TIMER_CLK_SRC_RTC32K (1)
+#define TIMER_CLK_DIV1               (0x0)
+#define TIMER_CLK_DIV2               (0x1)
+#define TIMER_CLK_DIV3               (0x2)
+#define TIMER_CLK_DIV4               (0x3)
+#define TIMER_CLK_DIV5               (0x4)
+#define TIMER_CLK_DIV6               (0x5)
+#define TIMER_CLK_DIV7               (0x6)
+#define TIMER_CLK_DIV8               (0x7)
+#define TIMER_CLK_DIV9               (0x8)
+#define TIMER_CLK_DIV10              (0x9)
+#define TIMER_CLK_DIV11              (0xA)
+#define TIMER_CLK_DIV12              (0xB)
+#define TIMER_CLK_DIV13              (0xC)
+#define TIMER_CLK_DIV16              (0xD)
+#define TIMER_CLK_DIV32              (0xE)
+#define TIMER_CLK_DIV64              (0xF)
+
+#define TIMER_CNT_REG(val)   (0x08 + (0x10 * val))
+#define TIMER_CMP_REG(val)   (0x0C + (0x10 * val))
+
+#define GPT_CLK_EVT  1
+#define GPT_CLK_SRC  2
+
+
+
+struct mtk_clock_event_device {
+     void __iomem *gpt_base;
+     u32 ticks_per_jiffy;
+     struct clock_event_device dev;
+};
+
+static inline struct mtk_clock_event_device *to_mtk_clk(
+                             struct clock_event_device *c)
+{
+     return container_of(c, struct mtk_clock_event_device, dev);
+}
+
+static void mtk_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer)
+{
+     u32 val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
+     writel(val & ~TIMER_CTRL_ENABLE, evt->gpt_base +
+                     TIMER_CTRL_REG(timer));
+}
+
+static void mtk_clkevt_time_setup(struct mtk_clock_event_device *evt,
+                             unsigned long delay, u8 timer)
+{
+     writel(delay, evt->gpt_base + TIMER_CMP_REG(timer));
+}
+
+static void mtk_clkevt_time_start(struct mtk_clock_event_device *evt,
+             bool periodic, u8 timer)
+{
+     u32 val;
+
+     /* Acknowledge interrupt */
+     writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG);
+
+     val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
+
+     /* Clear 2 bit timer operation mode field */
+     val &= ~TIMER_CTRL_OP(0x3);
+
+     if (periodic)
+             val |= TIMER_CTRL_OP(TIMER_CTRL_OP_REPEAT);
+     else
+             val |= TIMER_CTRL_OP(TIMER_CTRL_OP_ONESHOT);
+
+     writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR,
+            evt->gpt_base + TIMER_CTRL_REG(timer));
+}
+
+static void mtk_clkevt_mode(enum clock_event_mode mode,
+                             struct clock_event_device *clk)
+{
+     struct mtk_clock_event_device *evt = to_mtk_clk(clk);
+
+     mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
+
+     switch (mode) {
+     case CLOCK_EVT_MODE_PERIODIC:
+             mtk_clkevt_time_setup(evt, evt->ticks_per_jiffy, GPT_CLK_EVT);
+             mtk_clkevt_time_start(evt, true, GPT_CLK_EVT);
+             break;
+     case CLOCK_EVT_MODE_ONESHOT:
+             mtk_clkevt_time_start(evt, false, GPT_CLK_EVT);
+             break;
+     case CLOCK_EVT_MODE_UNUSED:
+     case CLOCK_EVT_MODE_SHUTDOWN:
+     default:
+             /* No more interrupts will occur as source is disabled */
+             break;
+     }
+}
+
+static int mtk_clkevt_next_event(unsigned long event,
+                                struct clock_event_device *clk)
+{
+     struct mtk_clock_event_device *evt = to_mtk_clk(clk);
+
+     mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
+     mtk_clkevt_time_setup(evt, event, GPT_CLK_EVT);
+     mtk_clkevt_time_start(evt, false, GPT_CLK_EVT);
+
+     return 0;
+}
+
+static irqreturn_t mtk_timer_interrupt(int irq, void *dev_id)
+{
+     struct mtk_clock_event_device *evt = dev_id;
+
+     /* Acknowledge timer0 irq */
+     writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG);
+     evt->dev.event_handler(&evt->dev);
+
+     return IRQ_HANDLED;
+}
+
+static void mtk_timer_global_reset(struct mtk_clock_event_device *evt)
+{
+     /* Disable all interrupts */
+     writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG);
+     /* Acknowledge all interrupts */
+     writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG);
+}
+
+static void mtk_timer_reset(struct mtk_clock_event_device *evt, u8 timer)
+{
+     writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE,
+             evt->gpt_base + TIMER_CTRL_REG(timer));
+     writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer));
+}
+
+static void __init mtk_timer_init(struct device_node *node)
+{
+     struct mtk_clock_event_device *evt;
+     struct resource res;
+     unsigned long rate = 0;
+     struct clk *clk;
+     int ret;
+     u32 val;
+
+     evt = kzalloc(sizeof(*evt), GFP_KERNEL);
+     if (!evt)
+             panic("Can't allocate mtk clock event driver struct");
+
+     evt->dev.name = "mtk_tick";

drivers/clocksource/mtk_timer.c line 200

Quoted 5 lines

drivers/clocksource/mtk_timer.c new file +5 -0

+     evt->dev.rating = 300;
+     evt->dev.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
+     evt->dev.set_mode = mtk_clkevt_mode;
+     evt->dev.set_next_event = mtk_clkevt_next_event;
+     evt->dev.cpumask = cpu_all_mask;

cpu_possible_mask would probably be a better fit. And you still forgot to set the irq field of this struct.

Maxime

--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

2014-05-13 7:54 GMT+02:00 Maxime Ripard <[email protected]>:

Quoted 251 lines · Matthias Brugger

Quoted 250 lines

This patch adds a clock source and clock event for the timer found on the Mediatek SoCs.

The Mediatek General Porpose Timer block provides five 32 bit timers and one 64 bit timer.

Two 32 bit timers are used:
TIMER1: clock events supporting periodic and oneshot events
TIMER2: clock source configured as a free running counter

The General Porpose Timer block can be run with two clocks. A 13 MHz system clock and the RTC clock running at 32 KHz. This implementation uses the system clock.

Signed-off-by Matthias Brugger <[email protected]>

---
 drivers/clocksource/Kconfig     |   4 +
 drivers/clocksource/Makefile    |   1 +
 drivers/clocksource/mtk_timer.c | 263 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 268 insertions(+)
 create mode 100644 drivers/clocksource/mtk_timer.c

drivers/clocksource/Kconfig +4 -0

index 96918e1..1f73740 100644
@@ -144,6 +144,10 @@ config VF_PIT_TIMER
 config SYS_SUPPORTS_SH_CMT
         bool
 
+config MTK_TIMER
+     select CLKSRC_MMIO
+     bool
+
 config SYS_SUPPORTS_SH_MTU2
         bool
 

drivers/clocksource/Makefile +1 -0

index 98cb6c5..619d302 100644
@@ -33,6 +33,7 @@ obj-$(CONFIG_CLKSRC_EXYNOS_MCT)     += exynos_mct.o
 obj-$(CONFIG_CLKSRC_SAMSUNG_PWM)     += samsung_pwm_timer.o
 obj-$(CONFIG_VF_PIT_TIMER)   += vf_pit_timer.o
 obj-$(CONFIG_CLKSRC_QCOM)    += qcom-timer.o
+obj-$(CONFIG_MTK_TIMER)              += mtk_timer.o
 
 obj-$(CONFIG_ARM_ARCH_TIMER)         += arm_arch_timer.o
 obj-$(CONFIG_ARM_GLOBAL_TIMER)               += arm_global_timer.o

drivers/clocksource/mtk_timer.c new file +195 -0

new file mode 100644
index 0000000..4b88065
@@ -0,0 +1,263 @@
+/*
+ * Mediatek SoCs General-Purpose Timer handling.
+ *
+ * Copyright (C) 2014 Matthias Brugger
+ *
+ * Matthias Brugger <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqreturn.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+
+#define GPT_IRQ_EN_REG               0x00
+#define GPT_IRQ_ENABLE(val)  BIT(val-1)
+#define GPT_IRQ_ST_REG               0x04
+#define GPT_IRQ_ACK_REG              0x08
+#define GPT_IRQ_ACK(val)     BIT(val-1)
+
+#define TIMER_CTRL_REG(val)  (0x10 * val)
+#define TIMER_CTRL_OP(val)   (((val) & 0x3) << 4)
+#define TIMER_CTRL_OP_ONESHOT        (0)
+#define TIMER_CTRL_OP_REPEAT (1)
+#define TIMER_CTRL_OP_KEEPGO (2)
+#define TIMER_CTRL_OP_FREERUN        (3)
+#define TIMER_CTRL_CLEAR     (2)
+#define TIMER_CTRL_ENABLE    (1)
+#define TIMER_CTRL_DISABLE   (0)
+
+#define TIMER_CLK_REG(val)   (0x04 + (0x10 * val))
+#define TIMER_CLK_SRC(val)   (((val) & 0x1) << 4)
+#define TIMER_CLK_SRC_SYS13M (0)
+#define TIMER_CLK_SRC_RTC32K (1)
+#define TIMER_CLK_DIV1               (0x0)
+#define TIMER_CLK_DIV2               (0x1)
+#define TIMER_CLK_DIV3               (0x2)
+#define TIMER_CLK_DIV4               (0x3)
+#define TIMER_CLK_DIV5               (0x4)
+#define TIMER_CLK_DIV6               (0x5)
+#define TIMER_CLK_DIV7               (0x6)
+#define TIMER_CLK_DIV8               (0x7)
+#define TIMER_CLK_DIV9               (0x8)
+#define TIMER_CLK_DIV10              (0x9)
+#define TIMER_CLK_DIV11              (0xA)
+#define TIMER_CLK_DIV12              (0xB)
+#define TIMER_CLK_DIV13              (0xC)
+#define TIMER_CLK_DIV16              (0xD)
+#define TIMER_CLK_DIV32              (0xE)
+#define TIMER_CLK_DIV64              (0xF)
+
+#define TIMER_CNT_REG(val)   (0x08 + (0x10 * val))
+#define TIMER_CMP_REG(val)   (0x0C + (0x10 * val))
+
+#define GPT_CLK_EVT  1
+#define GPT_CLK_SRC  2
+
+
+
+struct mtk_clock_event_device {
+     void __iomem *gpt_base;
+     u32 ticks_per_jiffy;
+     struct clock_event_device dev;
+};
+
+static inline struct mtk_clock_event_device *to_mtk_clk(
+                             struct clock_event_device *c)
+{
+     return container_of(c, struct mtk_clock_event_device, dev);
+}
+
+static void mtk_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer)
+{
+     u32 val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
+     writel(val & ~TIMER_CTRL_ENABLE, evt->gpt_base +
+                     TIMER_CTRL_REG(timer));
+}
+
+static void mtk_clkevt_time_setup(struct mtk_clock_event_device *evt,
+                             unsigned long delay, u8 timer)
+{
+     writel(delay, evt->gpt_base + TIMER_CMP_REG(timer));
+}
+
+static void mtk_clkevt_time_start(struct mtk_clock_event_device *evt,
+             bool periodic, u8 timer)
+{
+     u32 val;
+
+     /* Acknowledge interrupt */
+     writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG);
+
+     val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
+
+     /* Clear 2 bit timer operation mode field */
+     val &= ~TIMER_CTRL_OP(0x3);
+
+     if (periodic)
+             val |= TIMER_CTRL_OP(TIMER_CTRL_OP_REPEAT);
+     else
+             val |= TIMER_CTRL_OP(TIMER_CTRL_OP_ONESHOT);
+
+     writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR,
+            evt->gpt_base + TIMER_CTRL_REG(timer));
+}
+
+static void mtk_clkevt_mode(enum clock_event_mode mode,
+                             struct clock_event_device *clk)
+{
+     struct mtk_clock_event_device *evt = to_mtk_clk(clk);
+
+     mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
+
+     switch (mode) {
+     case CLOCK_EVT_MODE_PERIODIC:
+             mtk_clkevt_time_setup(evt, evt->ticks_per_jiffy, GPT_CLK_EVT);
+             mtk_clkevt_time_start(evt, true, GPT_CLK_EVT);
+             break;
+     case CLOCK_EVT_MODE_ONESHOT:
+             mtk_clkevt_time_start(evt, false, GPT_CLK_EVT);
+             break;
+     case CLOCK_EVT_MODE_UNUSED:
+     case CLOCK_EVT_MODE_SHUTDOWN:
+     default:
+             /* No more interrupts will occur as source is disabled */
+             break;
+     }
+}
+
+static int mtk_clkevt_next_event(unsigned long event,
+                                struct clock_event_device *clk)
+{
+     struct mtk_clock_event_device *evt = to_mtk_clk(clk);
+
+     mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
+     mtk_clkevt_time_setup(evt, event, GPT_CLK_EVT);
+     mtk_clkevt_time_start(evt, false, GPT_CLK_EVT);
+
+     return 0;
+}
+
+static irqreturn_t mtk_timer_interrupt(int irq, void *dev_id)
+{
+     struct mtk_clock_event_device *evt = dev_id;
+
+     /* Acknowledge timer0 irq */
+     writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG);
+     evt->dev.event_handler(&evt->dev);
+
+     return IRQ_HANDLED;
+}
+
+static void mtk_timer_global_reset(struct mtk_clock_event_device *evt)
+{
+     /* Disable all interrupts */
+     writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG);
+     /* Acknowledge all interrupts */
+     writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG);
+}
+
+static void mtk_timer_reset(struct mtk_clock_event_device *evt, u8 timer)
+{
+     writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE,
+             evt->gpt_base + TIMER_CTRL_REG(timer));
+     writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer));
+}
+
+static void __init mtk_timer_init(struct device_node *node)
+{
+     struct mtk_clock_event_device *evt;
+     struct resource res;
+     unsigned long rate = 0;
+     struct clk *clk;
+     int ret;
+     u32 val;
+
+     evt = kzalloc(sizeof(*evt), GFP_KERNEL);
+     if (!evt)
+             panic("Can't allocate mtk clock event driver struct");
+
+     evt->dev.name = "mtk_tick";

Quoted 8 lines

drivers/clocksource/mtk_timer.c line 200

Quoted 5 lines

drivers/clocksource/mtk_timer.c new file +5 -0

+     evt->dev.rating = 300;
+     evt->dev.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
+     evt->dev.set_mode = mtk_clkevt_mode;
+     evt->dev.set_next_event = mtk_clkevt_next_event;
+     evt->dev.cpumask = cpu_all_mask;

cpu_possible_mask would probably be a better fit. And you still forgot to set the irq field of this struct.

I set the irq field when parsing the irq from the dts. Or do you refer to a different field I'm not aware of?

Add binding documentation for the General Porpose Timer driver of the Mediatek SoCs.

Signed-off-by Matthias Brugger <[email protected]>

---
 .../devicetree/bindings/timer/mediatek,mtk-timer.txt   | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt

Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt new file +0 -0

new file mode 100644
index 0000000..d0f2df3

Hi Matthias,

Quoted 22 lines · Matthias Brugger

Add binding documentation for the General Porpose Timer driver of the Mediatek SoCs.

Signed-off-by Matthias Brugger <[email protected]>

---
 .../devicetree/bindings/timer/mediatek,mtk-timer.txt   | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt

Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt new file +7 -0

new file mode 100644
index 0000000..d0f2df3
@@ -0,0 +1,18 @@
+Mediatek MT6589, MT6577 and MT6572 Timers
+---------------------------------------
+
+Required properties:
+- compatible: Should be "mediatek,mtk6589-timer"
+- reg: Should contain location and length for timers register.
+- clocks: phandle to the clock source; the first refers to a 13 MHz fixed

Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt line 9

Quoted 2 lines

Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt new file +2 -0

+             system clock and the second handle to a 32 KHz fixed RTC
+             clock.

Are these frequencies mandatory to the timer or an implementation detail of the SOC you're working with? I suspect, it might be possible to see the same timer in a different SOC implementation with different frequencies? In that case - or probably in general - the frequencies should not be part of the binding, IMHO.

Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt line 17

Quoted 9 lines

Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt new file +8 -0

+
+Examples:
+
+     timer {
+             compatible = "mediatek,mtk6589-timer";
+             reg = <0x10008000 0x80>;
+             interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
+             clocks = <&system_clk>, <&rtc_clk>;

Might be just my personal preference, but you could also add the clock-names property which would relax the ordering requirement a bit and would clearly identify the IP's clocks.

S?ren

2014-05-13 15:08 GMT+02:00 S?ren Brinkmann <[email protected]>:

Quoted 25 lines

Hi Matthias,

Quoted 22 lines · Matthias Brugger

Add binding documentation for the General Porpose Timer driver of the Mediatek SoCs.

Signed-off-by Matthias Brugger <[email protected]>

---
 .../devicetree/bindings/timer/mediatek,mtk-timer.txt   | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt

Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt new file +7 -0

new file mode 100644
index 0000000..d0f2df3
@@ -0,0 +1,18 @@
+Mediatek MT6589, MT6577 and MT6572 Timers
+---------------------------------------
+
+Required properties:
+- compatible: Should be "mediatek,mtk6589-timer"
+- reg: Should contain location and length for timers register.
+- clocks: phandle to the clock source; the first refers to a 13 MHz fixed

Quoted 8 lines

Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt line 9

Quoted 2 lines

Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt new file +2 -0

+             system clock and the second handle to a 32 KHz fixed RTC
+             clock.

Are these frequencies mandatory to the timer or an implementation detail of the SOC you're working with? I suspect, it might be possible to see the same timer in a different SOC implementation with different frequencies? In that case - or probably in general - the frequencies should not be part of the binding, IMHO.

I had a look at the implementation of several Mediatek SoCs and all of them have the timer with the same clock connections.
I don't know if the IP can be or is actually used with other clocksources. I can try to reformulate the description to make the clock constraints sound less mandatory.
Although I would prefer to leave a mention about the clock frequencies (like e.g. in the allwinner,sun4i-timer).

Quoted 14 lines

Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt line 17

Quoted 10 lines

Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt new file +8 -0

+
+Examples:
+
+     timer {
+             compatible = "mediatek,mtk6589-timer";
+             reg = <0x10008000 0x80>;
+             interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
+             clocks = <&system_clk>, <&rtc_clk>;

Might be just my personal preference, but you could also add the clock-names property which would relax the ordering requirement a bit and would clearly identify the IP's clocks.

In the v1 of the patch series I had the clock names included [1] but because of comments of others I removed them [1]. Actually the driver just use the first clock, but from my understanding the DT reflects as well the HW configuration and for this reason I put the two clocks in the DT.

[1] http://thread.gmane.org/gmane.linux.drivers.devicetree/69155/

arch/arm/mach-mediatek/mediatek.c new file +15 -0

new file mode 100644
index 0000000..73dfb05
@@ -0,0 +1,32 @@
+/*
+ * Device Tree support for Mediatek SoCs
+ *
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.

Quoted 21 lines · Matthias Brugger

arch/arm/mach-mediatek/mediatek.c new file +15 -0

new file mode 100644
index 0000000..73dfb05
@@ -0,0 +1,32 @@
+/*
+ * Device Tree support for Mediatek SoCs
+ *
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.

arch/arm/mach-mediatek/mediatek.c line 25

Quoted 10 lines

arch/arm/mach-mediatek/mediatek.c new file +10 -0

+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_platform.h>
+#include <linux/irqchip.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+static const char * const mediatek_board_dt_compat[] = {

__initconst?

arch/arm/mach-mediatek/mediatek.c line 32

Quoted 7 lines

arch/arm/mach-mediatek/mediatek.c new file +7 -0

+	"mediatek,mt6589",
+	NULL,
+};
+
+DT_MACHINE_START(MEDIATEK_DT, "Mediatek Cortex-A7 (Device Tree)")
+	.dt_compat	= mediatek_board_dt_compat,
+MACHINE_END

You shouldn't need this file at all if the platform is part of the multi-platform kernel.

From a technical point of view, you don't. But it's interesting to

Quoted 11 lines · Stephen Boyd

arch/arm/mach-mediatek/mediatek.c line 32

Quoted 7 lines · Matthias Brugger

arch/arm/mach-mediatek/mediatek.c new file +7 -0

+	"mediatek,mt6589",
+	NULL,
+};
+
+DT_MACHINE_START(MEDIATEK_DT, "Mediatek Cortex-A7 (Device Tree)")
+	.dt_compat	= mediatek_board_dt_compat,
+MACHINE_END

You shouldn't need this file at all if the platform is part of the multi-platform kernel.

From a technical point of view, you don't. But it's interesting to keep it mostly for two things:
- You get to see the platform name in /proc/cpuinfo
- If you ever need to add platform quirks, it's already there

We had a similar discussion two weeks ago for mach-sunxi with Olof and Arnd, and ended up keeping this minimal machine.

Quoted 18 lines · Maxime Ripard

Quoted 11 lines · Stephen Boyd

arch/arm/mach-mediatek/mediatek.c line 32

Quoted 7 lines · Matthias Brugger

arch/arm/mach-mediatek/mediatek.c new file +7 -0

+	"mediatek,mt6589",
+	NULL,
+};
+
+DT_MACHINE_START(MEDIATEK_DT, "Mediatek Cortex-A7 (Device Tree)")
+	.dt_compat	= mediatek_board_dt_compat,
+MACHINE_END

You shouldn't need this file at all if the platform is part of the multi-platform kernel.

From a technical point of view, you don't. But it's interesting to keep it mostly for two things:
- You get to see the platform name in /proc/cpuinfo
- If you ever need to add platform quirks, it's already there

Quoted 3 lines

We had a similar discussion two weeks ago for mach-sunxi with Olof and Arnd, and ended up keeping this minimal machine.

It looks like it's only useful to make /proc/cpuinfo have the platform name because it really isn't that hard to add this file if we need to add platform quirks. The downside is we have to keep adding compatibles when we support new SoCs.

Quoted 19 lines · On Wednesday 14 May 2014 14:26:12 Stephen Boyd wrote:

Quoted 18 lines · Maxime Ripard

Quoted 11 lines · Stephen Boyd

arch/arm/mach-mediatek/mediatek.c line 32

Quoted 7 lines · Matthias Brugger

arch/arm/mach-mediatek/mediatek.c new file +7 -0

+       "mediatek,mt6589",
+       NULL,
+};
+
+DT_MACHINE_START(MEDIATEK_DT, "Mediatek Cortex-A7 (Device Tree)")
+       .dt_compat      = mediatek_board_dt_compat,
+MACHINE_END

You shouldn't need this file at all if the platform is part of the multi-platform kernel.

From a technical point of view, you don't. But it's interesting to keep it mostly for two things:
- You get to see the platform name in /proc/cpuinfo
- If you ever need to add platform quirks, it's already there

Quoted 8 lines

Quoted 3 lines

We had a similar discussion two weeks ago for mach-sunxi with Olof and Arnd, and ended up keeping this minimal machine.

It looks like it's only useful to make /proc/cpuinfo have the platform name because it really isn't that hard to add this file if we need to add platform quirks. The downside is we have to keep adding compatibles when we support new SoCs.

We also still add Kconfig entries for each new platform, and I'd like to leave it at that for the time being. In a lot of cases we end up adding stuff to the machine descriptor later, e.g. for SMP support (hopefully no more thanks to your work though).

Once we have a significant number of machines that are actually usable rather than stubs and that we are confident about never needing any additional pointers, we can revisit this discussion.

At that point, we should also discuss how to avoid adding a Kconfig entry for each new platform, which e.g. involves making the clocksource drivers user selectable. That part has been surprisingly controversial in the past.

Hi Stephen,

Quoted 35 lines · Stephen Boyd

Quoted 21 lines · Matthias Brugger

arch/arm/mach-mediatek/mediatek.c new file +15 -0

new file mode 100644
index 0000000..73dfb05
@@ -0,0 +1,32 @@
+/*
+ * Device Tree support for Mediatek SoCs
+ *
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.

arch/arm/mach-mediatek/mediatek.c line 25

Quoted 10 lines

arch/arm/mach-mediatek/mediatek.c new file +10 -0

+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_platform.h>
+#include <linux/irqchip.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+static const char * const mediatek_board_dt_compat[] = {

__initconst?

Quoted 10 lines

arch/arm/mach-mediatek/mediatek.c line 32

Quoted 7 lines

arch/arm/mach-mediatek/mediatek.c new file +7 -0

+   "mediatek,mt6589",
+   NULL,
+};
+
+DT_MACHINE_START(MEDIATEK_DT, "Mediatek Cortex-A7 (Device Tree)")
+   .dt_compat      = mediatek_board_dt_compat,
+MACHINE_END

You shouldn't need this file at all if the platform is part of the multi-platform kernel.

From a technical point of view, you don't. But it's interesting to keep it mostly for two things:
- You get to see the platform name in /proc/cpuinfo

- If you ever need to add platform quirks, it's already there