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Implement flush_kern_tlb_page

PATCH New ritesh.harjani at gmail.com 2 participants 6 messages May 19, 2014 arm64

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ritesh.harjani at gmail.com

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#0 lore raw

cover Implement flush_kern_tlb_page

From: Ritesh Harjani <[email protected]>

This patch adds the function definition to flush_kern_tlb_page, defined in comments header in arch/arm64/include/asm/tlbflush.h

Quoted 1 line

From ARMv8_arm:

TLBI VAE1IS: Global TLB entries that match the VA value will be affected by this operation, regardless of the value of the ASID field.

So, since kernel region has nG(non-Global) == 0, means region is available for all processes. So, we can use TLBI VAE1IS for kernel region as well.

Ritesh Harjani (1):
arm64: TLB maintainance: Implement flush_kern_tlb_page

 arch/arm64/include/asm/tlbflush.h | 10 ++++++++++
 1 file changed, 10 insertions(+)
Signature · 1 line
1.8.1.3
author
#1 lore raw

PATCH 1/1 arm64: TLB maintainance: Implement flush_kern_tlb_page

From: Ritesh Harjani <[email protected]>

Implement flush_kern_tlb_page mentioned in the header comment of arch/arm64/include/asm/tlbflush.h

Signed-off-by Ritesh Harjani <[email protected]>
---
 arch/arm64/include/asm/tlbflush.h | 10 ++++++++++
 1 file changed, 10 insertions(+)
arch/arm64/include/asm/tlbflush.h +10 -0
index 8b48203..92d0588 100644
@@ -98,6 +98,16 @@ static inline void flush_tlb_page(struct vm_area_struct *vma,
 	dsb();
 }
 
+static inline void flush_kern_tlb_page(unsigned long kaddr)
+{
+	unsigned long addr = kaddr >> 12;
+
+	dsb();
+	asm("tlbi	vae1is, %0" : : "r" (addr));
+	dsb();
+	isb();
+}
+
 /*
  * Convert calls to our calling convention.
  */
Signature · 1 line
1.8.1.3
maintainer
#2 lore raw

PATCH 1/1 arm64: TLB maintainance: Implement flush_kern_tlb_page

Quoted 4 lines · ritesh.harjani at gmail.com

From: Ritesh Harjani <[email protected]>

Implement flush_kern_tlb_page mentioned in the header comment of arch/arm64/include/asm/tlbflush.h

Alternatively, clean-up the comment.

Signature · 1 line
Catalin
author
#3 lore raw

PATCH 1/1 arm64: TLB maintainance: Implement flush_kern_tlb_page

Hi Catalin,

Quoted 7 lines · Catalin Marinas
Quoted 4 lines · ritesh.harjani at gmail.com

From: Ritesh Harjani <[email protected]>

Implement flush_kern_tlb_page mentioned in the header comment of arch/arm64/include/asm/tlbflush.h

Alternatively, clean-up the comment.

You mean this function is of no use ? Or there are other plans which might require clean up of this file ?

Also, could you please confirm whether the implementation of the function is correct ?

Quoted 1 line
Quoted 1 line

+ asm("tlbi vae1is, %0" : : "r" (addr));

Should following instruction be more appropriate instead of above:
asm("tlbi vaae1is, %0" : : "r" (addr));

Quoted 3 lines

--
Catalin

Thanks
Ritesh

maintainer
#4 lore raw

PATCH 1/1 arm64: TLB maintainance: Implement flush_kern_tlb_page

Quoted 5 lines · Ritesh Harjani
Quoted 3 lines · Catalin Marinas
Quoted 2 lines · ritesh.harjani at gmail.com

From: Ritesh Harjani <[email protected]>

Quoted 7 lines
Quoted 4 lines
Quoted 2 lines

Implement flush_kern_tlb_page mentioned in the header comment of arch/arm64/include/asm/tlbflush.h

Alternatively, clean-up the comment.

You mean this function is of no use ? Or there are other plans which might require clean up of this file ?

Since we don't have it and the kernel builds fine, I guess we don't need it.

Quoted 7 lines

Also, could you please confirm whether the implementation of the function is correct ?

Quoted 1 line
Quoted 1 line

+ asm("tlbi vae1is, %0" : : "r" (addr));

Should following instruction be more appropriate instead of above:
asm("tlbi vaae1is, %0" : : "r" (addr));

You should use the vaae1is variant for all ASIDs since it's a global mapping (see flush_tlb_kernel_range()).

Signature · 1 line
Catalin
author
#5 lore raw

PATCH 1/1 arm64: TLB maintainance: Implement flush_kern_tlb_page

Quoted 9 lines · Catalin Marinas
Quoted 8 lines · Ritesh Harjani
Quoted 6 lines · Catalin Marinas
Quoted 4 lines · ritesh.harjani at gmail.com

From: Ritesh Harjani <[email protected]>

Implement flush_kern_tlb_page mentioned in the header comment of arch/arm64/include/asm/tlbflush.h

Quoted 7 lines
Quoted 4 lines
Quoted 1 line

Alternatively, clean-up the comment.

You mean this function is of no use ? Or there are other plans which might require clean up of this file ?

Since we don't have it and the kernel builds fine, I guess we don't need it.

Ok.

Quoted 11 lines
Quoted 8 lines

Also, could you please confirm whether the implementation of the function is correct ?

Quoted 1 line
Quoted 1 line

+ asm("tlbi vae1is, %0" : : "r" (addr));

Should following instruction be more appropriate instead of above:
asm("tlbi vaae1is, %0" : : "r" (addr));

You should use the vaae1is variant for all ASIDs since it's a global mapping (see flush_tlb_kernel_range()).

Yes!!, ok thanks!!.

Quoted 3 lines

--
Catalin

Thanks
Ritesh