Skip to contentSkip to conversation

ARM: omap3-lilly-a83x: update board support

PATCH New Christoph Fritz 4 participants 18 messages May 22, 2014 – Jul 16, 2014

Subsystems (8)
Device tree bindings Arm (32-bit) Arm sub-architectures Pin control +4 more subsystems
lore
Share & tools
lore

Christoph Fritz

author
#0 lore raw

cover ARM: omap3-lilly-a83x: update board support

This set of patches updates board support for omap3-lilly-a83x.

Christoph Fritz (5):
[RFC-HACK] pinctrl-single: init by postcore_initcall() [RFC-HACK] ARM: dts: OMAP3: reorder pinmux_gpio1_pins
ARM: dts: omap3: set mcbsp2 status
[RFC] ARM: OMAP2+: gpmc: fix gpmc_hwecc_bch_capable
ARM: dts: OMAP3 a83x: fix duplicate usb pin config

 arch/arm/boot/dts/omap3-lilly-a83x.dtsi |    7 +++---
 arch/arm/boot/dts/omap34xx.dtsi         |   28 ++++++++++++----------
 arch/arm/boot/dts/omap36xx.dtsi         |   40 ++++++++++++++++---------------
 arch/arm/mach-omap2/gpmc-nand.c         |   16 +++++--------
 drivers/pinctrl/pinctrl-single.c        |   15 ++++++++++++
 5 files changed, 61 insertions(+), 45 deletions(-)
Signature · 1 line
1.7.10.4
author
#1 lore raw

PATCH 1/5 pinctrl-single: init by postcore_initcall()

Init pinctrl-single as postcore, because without this patch omap_gpio is deferring probe which results in more deferring and finally NFS-Boot doesn't work.

Diff of bootlog with (good) and without (fail) this patch:

fail renamed from good +95 -84
@@ -60,15 +60,22 @@
 cpuidle: using governor ladder
 cpuidle: using governor menu
 Reprogramming SDRC clock to 400000000 Hz
-pinctrl-single 480025a0.pinmux: 46 pins at pa fa0025a0 size 92
-pinctrl-single 48002030.pinmux: 282 pins at pa fa002030 size 564
-pinctrl-single 48002a00.pinmux: 46 pins at pa fa002a00 size 92
+omap_gpio 48310000.gpio: could not find pctldev for node /ocp/pinmux at 480025a0/pinmux_gpio1_pins, deferring probe
+platform 48310000.gpio: Driver omap_gpio requests probe deferral
 OMAP GPIO hardware version 2.5
+omap_gpio 49054000.gpio: could not find pctldev for node /ocp/pinmux at 48002030/pinmux_gpio4_pins, deferring probe
+platform 49054000.gpio: Driver omap_gpio requests probe deferral
+omap_gpio 49056000.gpio: could not find pctldev for node /ocp/pinmux at 48002030/pinmux_gpio5_pins, deferring probe
+platform 49056000.gpio: Driver omap_gpio requests probe deferral
+omap_gpio 49058000.gpio: could not find pctldev for node /ocp/pinmux at 48002030/pinmux_hsusb1_pins, deferring probe
+platform 49058000.gpio: Driver omap_gpio requests probe deferral
 platform 49022000.mcbsp: alias fck already exists
 omap-gpmc 6e000000.gpmc: GPMC revision 5.0
 gpmc_probe_nand_child: ti,elm-id property not found
 gpmc_read_settings_dt: page/burst-length set but not used!
 gpmc_read_settings_dt: read/write wait monitoring not enabled!
+irq: no irq domain found for /ocp/gpio at 49056000 !
+irq: no irq domain found for /ocp/gpio at 49054000 !
 omap3_dbb056_legacy_init: Late Reparent clkout2 to 96M_FCK
 omap3_dbb056_legacy_init: Set clkout2 to 24MHz for internal usb hub
 No ATAGs?

@@ -82,9 +89,14 @@
 usbcore: registered new interface driver usbfs
 usbcore: registered new interface driver hub
 usbcore: registered new device driver usb
-omap_i2c 48070000.i2c: bus 0 rev4.4 at 2600 kHz
-omap_i2c 48072000.i2c: bus 1 rev4.4 at 2600 kHz
-omap_i2c 48060000.i2c: bus 2 rev4.4 at 2600 kHz
+musb-omap2430 480ab000.usb_otg_hs: could not find pctldev for node /ocp/pinmux at 48002030/pinmux_hsusb_otg_pins, deferring probe
+platform 480ab000.usb_otg_hs: Driver musb-omap2430 requests probe deferral
+omap_i2c 48070000.i2c: could not find pctldev for node /ocp/pinmux at 48002030/pinmux_i2c1_pins, deferring probe
+platform 48070000.i2c: Driver omap_i2c requests probe deferral
+omap_i2c 48072000.i2c: could not find pctldev for node /ocp/pinmux at 48002030/pinmux_i2c2_pins, deferring probe
+platform 48072000.i2c: Driver omap_i2c requests probe deferral
+omap_i2c 48060000.i2c: could not find pctldev for node /ocp/pinmux at 48002030/pinmux_i2c3_pins, deferring probe
+platform 48060000.i2c: Driver omap_i2c requests probe deferral
 pps_core: LinuxPPS API ver. 1 registered
 pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <[email protected]>
 PTP clock support registered

@@ -103,6 +115,8 @@
 RPC: Registered udp transport module.
 RPC: Registered tcp transport module.
 RPC: Registered tcp NFSv4.1 backchannel transport module.
+usbhs_omap 48064000.usbhshost: could not find pctldev for node /ocp/pinmux at 480025a0/pinmux_hsusb1_2_pins, deferring probe
+platform 48064000.usbhshost: Driver usbhs_omap requests probe deferral
 hw perfevents: enabled with ARMv7 Cortex-A8 PMU driver, 5 counters available
 futex hash table entries: 16 (order: -3, 704 bytes)
 VFS: Disk quotas dquot_6.5.2

@@ -116,10 +130,14 @@
 io scheduler noop registered
 io scheduler deadline registered
 io scheduler cfq registered (default)
+pinctrl-single 480025a0.pinmux: 46 pins at pa fa0025a0 size 92
+pinctrl-single 48002030.pinmux: 282 pins at pa fa002030 size 564
+pinctrl-single 48002a00.pinmux: 46 pins at pa fa002a00 size 92
 OMAP DSS rev 2.0
-omapdss_dpi.0 supply vdds_dsi not found, using dummy regulator
-Console: switching to colour frame buffer device 80x30
-omapfb omapfb: using display 'lcd' mode 640x480
+platform panel-dpi.0: Driver panel-dpi requests probe deferral
+omapfb omapfb: no displays
+omapfb omapfb: failed to setup omapfb
+platform omapfb: Driver omapfb requests probe deferral
 Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
 omap_uart 4806a000.serial: no wakeirq for uart0
 4806a000.serial: ttyO0 at MMIO 0x4806a000 (irq = 88, base_baud = 3000000) is a OMAP UART0

@@ -130,28 +148,6 @@
 49020000.serial: ttyO2 at MMIO 0x49020000 (irq = 90, base_baud = 3000000) is a OMAP UART2
 brd: module loaded
 loop: module loaded
-twl 0-0048: PIH (irq 23) chaining IRQs 338..346
-twl 0-0048: power (irq 343) chaining IRQs 346..353
-VAUX1: at 3000 mV
-VAUX2_4030: 2800 mV
-VAUX3: at 2800 mV
-VAUX4: at 2800 mV
-VDD1: 600 <--> 1450 mV at 1200 mV
-VDAC: 1800 mV
-VIO: at 1800 mV
-VINTANA1: 1500 mV
-VINTANA2: at 2750 mV
-VINTDIG: 1500 mV
-VMMC1: 1850 <--> 3150 mV at 3000 mV
-VMMC2: 1850 <--> 3150 mV at 2600 mV
-VUSB1V5: 1500 mV
-VUSB1V8: 1800 mV
-VUSB3V1: 3100 mV
-VPLL1: at 1800 mV
-VPLL2: 1800 mV
-VSIM: 1800 <--> 3000 mV at 1800 mV
-twl4030_gpio twl4030-gpio: gpio (irq 338) chaining IRQs 354..371
-twl4030_usb twl4030-usb.29: Initialized TWL4030 USB module
 mtdoops: mtd device (mtddev=name/number) must be supplied
 nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xba
 nand: Micron MT29F2G16ABBEAHC

@@ -164,67 +160,28 @@
 0x000000260000-0x000000280000 : "u-boot-environment"
 0x000000280000-0x000000780000 : "kernel"
 0x000000780000-0x000010000000 : "filesystem"
+irq: no irq domain found for /ocp/gpio at 48310000 !
 CAN device driver interface
 sja1000 CAN netdevice driver
-libphy: smsc911x-mdio: probed
-smsc911x 15000000.ethernet eth0: attached PHY driver [Generic PHY] (mii_bus:phy_addr=15000000.etherne:01, irq=-1)
-smsc911x 15000000.ethernet eth0: MAC Address: e2:cc:98:d3:c6:56
-libphy: smsc911x-mdio: probed
-smsc911x 20000000.ethernet eth1: attached PHY driver [Generic PHY] (mii_bus:phy_addr=20000000.etherne:01, irq=-1)
-smsc911x 20000000.ethernet eth1: MAC Address: 00:50:c2:0d:6a:63
+smsc911x: Could not allocate irq resource
+smsc911x: Could not allocate irq resource
 ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
 ehci-omap: OMAP-EHCI Host Controller driver
-ehci-omap 48064800.ehci: EHCI Host Controller
-ehci-omap 48064800.ehci: new USB bus registered, assigned bus number 1
-ehci-omap 48064800.ehci: irq 93, io mem 0x48064800
-ehci-omap 48064800.ehci: USB 2.0 started, EHCI 1.00
-usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
-usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
-usb usb1: Product: EHCI Host Controller
-usb usb1: Manufacturer: Linux 3.15.0-rc6+ ehci_hcd
-usb usb1: SerialNumber: 48064800.ehci
-hub 1-0:1.0: USB hub found
-hub 1-0:1.0: 3 ports detected
 ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
 ohci-omap3: OHCI OMAP3 driver
-ohci-omap3 48064400.ohci: OHCI Host Controller
-ohci-omap3 48064400.ohci: new USB bus registered, assigned bus number 2
-ohci-omap3 48064400.ohci: irq 92, io mem 0x48064400
-usb usb2: New USB device found, idVendor=1d6b, idProduct=0001
-usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
-usb usb2: Product: OHCI Host Controller
-usb usb2: Manufacturer: Linux 3.15.0-rc6+ ohci_hcd
-usb usb2: SerialNumber: 48064400.ohci
-hub 2-0:1.0: USB hub found
-hub 2-0:1.0: 3 ports detected
 usbcore: registered new interface driver usb-storage
-musb-hdrc musb-hdrc.0.auto: MUSB HDRC host driver
-musb-hdrc musb-hdrc.0.auto: new USB bus registered, assigned bus number 3
-usb usb3: New USB device found, idVendor=1d6b, idProduct=0002
-usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
-usb usb3: Product: MUSB HDRC host driver
-usb usb3: Manufacturer: Linux 3.15.0-rc6+ musb-hcd
-usb usb3: SerialNumber: musb-hdrc.0.auto
-hub 3-0:1.0: USB hub found
-hub 3-0:1.0: 1 port detected
 mousedev: PS/2 mouse device common for all mice
-ads7846 spi2.0: touchscreen, irq 120
-input: ADS7846 Touchscreen as /devices/68000000.ocp/4809a000.spi/spi_master/spi2/spi2.0/input/input0
-twl_rtc rtc.8: Power up reset detected.
-twl_rtc rtc.8: Enabling TWL-RTC
-twl_rtc rtc.8: rtc core: registered rtc.8 as rtc0
+ads7846: probe of spi2.0 failed with error -22
 i2c /dev entries driver
-usb 1-1: new high-speed USB device number 2 using ehci-omap
 omap_wdt: OMAP Watchdog Timer Rev 0x31: initial timeout 60 sec
-VMMC1: Restricting voltage, 3100000-1950000uV
-omap_hsmmc 480b4000.mmc: could not set regulator OCR (-22)
+platform 4809c000.mmc: Driver omap_hsmmc requests probe deferral
+platform 480b4000.mmc: Driver omap_hsmmc requests probe deferral
+platform leds.3: Driver leds-gpio requests probe deferral
 usbcore: registered new interface driver usbhid
 usbhid: USB HID core driver
-usb 1-1: New USB device found, idVendor=0424, idProduct=2512
-usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
-hub 1-1:1.0: USB hub found
-hub 1-1:1.0: 2 ports detected
-omap-twl4030 sound.4: twl4030-hifi <-> 49022000.mcbsp mapping ok
+omap-twl4030 sound.4: ASoC: CODEC twl4030-codec not registered
+omap-twl4030 sound.4: devm_snd_soc_register_card() failed: -517
+platform sound.4: Driver omap-twl4030 requests probe deferral
 TCP: cubic registered
 Initializing XFRM netlink socket
 NET: Registered protocol family 17

@@ -238,7 +195,61 @@
 ThumbEE CPU extension supported.
 Registering SWP/SWPB emulation handler
 registered taskstats version 1
-twl_rtc rtc.8: setting system clock to 2000-01-01 00:00:00 UTC (946684800)
-smsc911x 15000000.ethernet eth0: SMSC911x/921x identified at 0xc8856000, IRQ: 241
-smsc911x 20000000.ethernet eth1: SMSC911x/921x identified at 0xc8858000, IRQ: 210
-Sending DHCP requests ...
+HS USB OTG: no transceiver configured
+musb-hdrc musb-hdrc.0.auto: musb_init_controller failed with status -517
+platform musb-hdrc.0.auto: Driver musb-hdrc requests probe deferral
+twl 0-0048: PIH (irq 23) chaining IRQs 338..346
+twl 0-0048: power (irq 343) chaining IRQs 346..353
+twl_rtc rtc.8: Enabling TWL-RTC
+twl_rtc rtc.8: rtc core: registered rtc.8 as rtc0
+VAUX1: at 3000 mV
+VAUX2_4030: 2800 mV
+VAUX3: at 2800 mV
+VAUX4: at 2800 mV
+VDD1: 600 <--> 1450 mV at 1200 mV
+VDAC: 1800 mV
+VIO: at 1800 mV
+VINTANA1: 1500 mV
+VINTANA2: at 2750 mV
+VINTDIG: 1500 mV
+VMMC1: 1850 <--> 3150 mV at 3150 mV
+VMMC2: 1850 <--> 3150 mV at 2600 mV
+VUSB1V5: 1500 mV
+VUSB1V8: 1800 mV
+VUSB3V1: 3100 mV
+VPLL1: at 1800 mV
+VPLL2: 1800 mV
+VSIM: 1800 <--> 3000 mV at 1800 mV
+twl4030_gpio twl4030-gpio: gpio (irq 338) chaining IRQs 354..371
+twl4030_usb twl4030-usb.29: Initialized TWL4030 USB module
+omap_i2c 48070000.i2c: bus 0 rev4.4 at 2600 kHz
+omap_i2c 48072000.i2c: bus 1 rev4.4 at 2600 kHz
+omap_i2c 48060000.i2c: bus 2 rev4.4 at 2600 kHz
+omapdss_dpi.0 supply vdds_dsi not found, using dummy regulator
+Console: switching to colour frame buffer device 80x30
+omapfb omapfb: using display 'lcd' mode 640x480
+VMMC1: Restricting voltage, 3100000-1950000uV
+omap_hsmmc 480b4000.mmc: could not set regulator OCR (-22)
+omap-twl4030 sound.4: twl4030-hifi <-> 49022000.mcbsp mapping ok
+musb-hdrc musb-hdrc.0.auto: MUSB HDRC host driver
+musb-hdrc musb-hdrc.0.auto: new USB bus registered, assigned bus number 1
+usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
+usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
+usb usb1: Product: MUSB HDRC host driver
+usb usb1: Manufacturer: Linux 3.15.0-rc6+ musb-hcd
+usb usb1: SerialNumber: musb-hdrc.0.auto
+hub 1-0:1.0: USB hub found
+hub 1-0:1.0: 1 port detected
+twl_rtc rtc.8: setting system clock to 2000-01-01 00:18:06 UTC (946685886)
+ALSA device list:
+  #0: lilly-a83x
+Root-NFS: no NFS server address
+VFS: Unable to mount root fs via NFS, trying floppy.
+VFS: Cannot open root device "nfs" or unknown-block(2,0): error -6
+Please append a correct "root=" boot option; here are the available partitions:
+1f00             512 mtdblock0  (driver?)
+1f01            1920 mtdblock1  (driver?)
+1f02             128 mtdblock2  (driver?)
+1f03            5120 mtdblock3  (driver?)
+1f04          254464 mtdblock4  (driver?)
+Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(2,0)

See Bootlog:

---
 drivers/pinctrl/pinctrl-single.c |   15 +++++++++++++++
 1 file changed, 15 insertions(+)
drivers/pinctrl/pinctrl-single.c +15 -0
index 2960557..8582f29 100644
@@ -2069,7 +2069,22 @@ static struct platform_driver pcs_driver = {
 #endif
 };
 
+#ifdef CONFIG_USE_OF
+static int __init pcs_driver_drv_init(void)
+{
+       return platform_driver_register(&pcs_driver);
+}
+postcore_initcall(pcs_driver_drv_init);
+
+static void __exit pcs_driver_drv_exit(void)
+{
+       platform_driver_unregister(&pcs_driver);
+}
+module_exit(pcs_driver_drv_exit);
+#else
 module_platform_driver(pcs_driver);
+#endif
+
 
 MODULE_AUTHOR("Tony Lindgren <[email protected]>");
 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
Signature · 1 line
1.7.10.4
maintainer
#2 lore raw

PATCH 1/5 pinctrl-single: init by postcore_initcall()

Quoted 12 lines · Christoph Fritz
drivers/pinctrl/pinctrl-single.c +6 -0
@@ -2069,7 +2069,22 @@ static struct platform_driver pcs_driver = {
 #endif
 };
 
+#ifdef CONFIG_USE_OF
+static int __init pcs_driver_drv_init(void)
+{
+       return platform_driver_register(&pcs_driver);
+}
+postcore_initcall(pcs_driver_drv_init);

drivers/pinctrl/pinctrl-single.c static struct platform_driver pcs_driver = { · line 2087

Quoted 10 lines
drivers/pinctrl/pinctrl-single.c +9 -0
+
+static void __exit pcs_driver_drv_exit(void)
+{
+       platform_driver_unregister(&pcs_driver);
+}
+module_exit(pcs_driver_drv_exit);
+#else
 module_platform_driver(pcs_driver);
+#endif
+

I would prefer to initialize all the drivers with module_init and and if necessary, selected frameworks with subsys_initcall.

In drivers/Makefile we do have painctrl before gpio, so this too could be just module_init once the other drivers are fixed.

Regards,

Tony

#3 lore raw

PATCH 1/5 pinctrl-single: init by postcore_initcall()

Quoted 27 lines · Tony Lindgren
Quoted 12 lines · Christoph Fritz
drivers/pinctrl/pinctrl-single.c +6 -0
@@ -2069,7 +2069,22 @@ static struct platform_driver pcs_driver = {
 #endif
 };
 
+#ifdef CONFIG_USE_OF
+static int __init pcs_driver_drv_init(void)
+{
+       return platform_driver_register(&pcs_driver);
+}
+postcore_initcall(pcs_driver_drv_init);

drivers/pinctrl/pinctrl-single.c static struct platform_driver pcs_driver = { · line 2087

Quoted 10 lines
drivers/pinctrl/pinctrl-single.c +9 -0
+
+static void __exit pcs_driver_drv_exit(void)
+{
+       platform_driver_unregister(&pcs_driver);
+}
+module_exit(pcs_driver_drv_exit);
+#else
 module_platform_driver(pcs_driver);
+#endif
+

I would prefer to initialize all the drivers with module_init and and if necessary, selected frameworks with subsys_initcall.

Quoted 3 lines

In drivers/Makefile we do have painctrl before gpio, so this too could be just module_init once the other drivers are fixed.

I've been using patches that change gpio and i2c initialization to module_init for some time now. However, I still see some non-DT boards using the GPIO API in early functions such as .init_machine.

Only when these boards get converted and the legacy support is dropped, we'll be able to move all the drivers to module_init.

Signature · 2 lines
Ezequiel Garcia, VanguardiaSur
www.vanguardiasur.com.ar
maintainer
#4 lore raw

PATCH 1/5 pinctrl-single: init by postcore_initcall()

Quoted 32 lines · Ezequiel Garcia
Quoted 27 lines · Tony Lindgren
Quoted 12 lines · Christoph Fritz
drivers/pinctrl/pinctrl-single.c +6 -0
@@ -2069,7 +2069,22 @@ static struct platform_driver pcs_driver = {
 #endif
 };
 
+#ifdef CONFIG_USE_OF
+static int __init pcs_driver_drv_init(void)
+{
+       return platform_driver_register(&pcs_driver);
+}
+postcore_initcall(pcs_driver_drv_init);

drivers/pinctrl/pinctrl-single.c static struct platform_driver pcs_driver = { · line 2087

Quoted 10 lines
drivers/pinctrl/pinctrl-single.c +9 -0
+
+static void __exit pcs_driver_drv_exit(void)
+{
+       platform_driver_unregister(&pcs_driver);
+}
+module_exit(pcs_driver_drv_exit);
+#else
 module_platform_driver(pcs_driver);
+#endif
+

I would prefer to initialize all the drivers with module_init and and if necessary, selected frameworks with subsys_initcall.

Quoted 3 lines

In drivers/Makefile we do have painctrl before gpio, so this too could be just module_init once the other drivers are fixed.

Quoted 6 lines

I've been using patches that change gpio and i2c initialization to module_init for some time now. However, I still see some non-DT boards using the GPIO API in early functions such as .init_machine.

Only when these boards get converted and the legacy support is dropped, we'll be able to move all the drivers to module_init.

Hmm yeah tons of dependencies to dropping the legacy booting.. But to not have that dependency maybe we can convert those .init_machine functions easily to late_initcall.

Regards,

Tony

#5 lore raw

PATCH 1/5 pinctrl-single: init by postcore_initcall()

Quoted 37 lines · Tony Lindgren
Quoted 36 lines · Ezequiel Garcia
Quoted 27 lines · Tony Lindgren
Quoted 12 lines · Christoph Fritz
drivers/pinctrl/pinctrl-single.c +6 -0
@@ -2069,7 +2069,22 @@ static struct platform_driver pcs_driver = {
 #endif
 };
 
+#ifdef CONFIG_USE_OF
+static int __init pcs_driver_drv_init(void)
+{
+       return platform_driver_register(&pcs_driver);
+}
+postcore_initcall(pcs_driver_drv_init);

drivers/pinctrl/pinctrl-single.c static struct platform_driver pcs_driver = { · line 2087

Quoted 10 lines
drivers/pinctrl/pinctrl-single.c +9 -0
+
+static void __exit pcs_driver_drv_exit(void)
+{
+       platform_driver_unregister(&pcs_driver);
+}
+module_exit(pcs_driver_drv_exit);
+#else
 module_platform_driver(pcs_driver);
+#endif
+

I would prefer to initialize all the drivers with module_init and and if necessary, selected frameworks with subsys_initcall.

Quoted 3 lines

In drivers/Makefile we do have painctrl before gpio, so this too could be just module_init once the other drivers are fixed.

I've been using patches that change gpio and i2c initialization to module_init for some time now. However, I still see some non-DT boards using the GPIO API in early functions such as .init_machine.

Quoted 7 lines
Quoted 2 lines

Only when these boards get converted and the legacy support is dropped, we'll be able to move all the drivers to module_init.

Hmm yeah tons of dependencies to dropping the legacy booting.. But to not have that dependency maybe we can convert those .init_machine functions easily to late_initcall.

Could be. I can drop a few patches and then wait for Acks from the maintainers. Although I'm not really sure this is worth the pain.

Signature · 2 lines
Ezequiel Garcia, VanguardiaSur
www.vanguardiasur.com.ar
author
#6 lore raw

PATCH 2/5 ARM: dts: OMAP3: reorder pinmux_gpio1_pins

In reply to Christoph Fritz

pinctrl-single for omap3_pmx_core2 gets deferred which results in some corrupt IRQs so that mmc, spi and dss stop working.

Diff of bootlog with (good) and without (fail) this patch:

--- good
+++ fail
cpuidle: using governor ladder
cpuidle: using governor menu
Reprogramming SDRC clock to 400000000 Hz
-pinctrl-single 480025a0.pinmux: 46 pins at pa fa0025a0 size 92
pinctrl-single 48002030.pinmux: 282 pins at pa fa002030 size 564
pinctrl-single 48002a00.pinmux: 46 pins at pa fa002a00 size 92
+omap_gpio 48310000.gpio: could not find pctldev for node /ocp/pinmux at 480025a0/pinmux_gpio1_pins, deferring probe +platform 48310000.gpio: Driver omap_gpio requests probe deferral
OMAP GPIO hardware version 2.5
platform 49022000.mcbsp: alias fck already exists
omap-gpmc 6e000000.gpmc: GPMC revision 5.0
gpmc_probe_nand_child: ti,elm-id property not found
gpmc_read_settings_dt: page/burst-length set but not used!
gpmc_read_settings_dt: read/write wait monitoring not enabled!
+pinctrl-single 480025a0.pinmux: 46 pins at pa fa0025a0 size 92
omap3_dbb056_legacy_init: Late Reparent clkout2 to 96M_FCK
omap3_dbb056_legacy_init: Set clkout2 to 24MHz for internal usb hub
No ATAGs?
@@ -130,8 +132,8 @@
49020000.serial: ttyO2 at MMIO 0x49020000 (irq = 90, base_baud = 3000000) is a OMAP UART2
brd: module loaded
loop: module loaded
-twl 0-0048: PIH (irq 23) chaining IRQs 338..346
-twl 0-0048: power (irq 343) chaining IRQs 346..353
+twl 0-0048: PIH (irq 23) chaining IRQs 306..314
+twl 0-0048: power (irq 311) chaining IRQs 314..321
VAUX1: at 3000 mV
VAUX2_4030: 2800 mV
VAUX3: at 2800 mV
@@ -150,7 +152,7 @@
VPLL1: at 1800 mV
VPLL2: 1800 mV
VSIM: 1800 <--> 3000 mV at 1800 mV
-twl4030_gpio twl4030-gpio: gpio (irq 338) chaining IRQs 354..371
+twl4030_gpio twl4030-gpio: gpio (irq 306) chaining IRQs 322..339
twl4030_usb twl4030-usb.29: Initialized TWL4030 USB module
mtdoops: mtd device (mtddev=name/number) must be supplied
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xba
@@ -164,11 +166,12 @@
0x000000260000-0x000000280000 : "u-boot-environment"
0x000000280000-0x000000780000 : "kernel"
0x000000780000-0x000010000000 : "filesystem"
+irq: no irq domain found for /ocp/gpio at 48310000 !
CAN device driver interface
sja1000 CAN netdevice driver
libphy: smsc911x-mdio: probed
smsc911x 15000000.ethernet eth0: attached PHY driver [Generic PHY] (mii_bus:phy_addr=15000000.etherne:01, irq=-1)
@@ -208,16 +211,16 @@
hub 3-0:1.0: USB hub found
hub 3-0:1.0: 1 port detected
mousedev: PS/2 mouse device common for all mice
-ads7846 spi2.0: touchscreen, irq 120
-input: ADS7846 Touchscreen as /devices/68000000.ocp/4809a000.spi/spi_master/spi2/spi2.0/input/input0 +ads7846: probe of spi2.0 failed with error -22
twl_rtc rtc.8: Power up reset detected.
twl_rtc rtc.8: Enabling TWL-RTC
twl_rtc rtc.8: rtc core: registered rtc.8 as rtc0
i2c /dev entries driver
-usb 1-1: new high-speed USB device number 2 using ehci-omap
omap_wdt: OMAP Watchdog Timer Rev 0x31: initial timeout 60 sec
+usb 1-1: new high-speed USB device number 2 using ehci-omap
VMMC1: Restricting voltage, 3100000-1950000uV
omap_hsmmc 480b4000.mmc: could not set regulator OCR (-22)
+platform leds.3: Driver leds-gpio requests probe deferral
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
usb 1-1: New USB device found, idVendor=0424, idProduct=2512
@@ -239,6 +242,6 @@
Registering SWP/SWPB emulation handler
registered taskstats version 1
twl_rtc rtc.8: setting system clock to 2000-01-01 00:00:00 UTC (946684800)
-smsc911x 15000000.ethernet eth0: SMSC911x/921x identified at 0xc8856000, IRQ: 241
-smsc911x 20000000.ethernet eth1: SMSC911x/921x identified at 0xc8858000, IRQ: 210
-Sending DHCP requests ...
+smsc911x 15000000.ethernet eth0: SMSC911x/921x identified at 0xc8856000, IRQ: 209
+smsc911x 20000000.ethernet eth1: SMSC911x/921x identified at 0xc8858000, IRQ: 178
+Sending DHCP requests ..., OK

---
 arch/arm/boot/dts/omap34xx.dtsi |   28 ++++++++++++++-------------
 arch/arm/boot/dts/omap36xx.dtsi |   40 ++++++++++++++++++++-------------------
 2 files changed, 36 insertions(+), 32 deletions(-)
arch/arm/boot/dts/omap34xx.dtsi +15 -13
index 2e92360..4994cb0 100644
@@ -8,6 +8,21 @@
  * kind, whether express or implied.
  */
 
+/ {
+	ocp {
+		omap3_pmx_core2: pinmux at 480025d8 {
+			compatible = "ti,omap3-padconf", "pinctrl-single";
+			reg = <0x480025d8 0x24>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			pinctrl-single,register-width = <16>;
+			pinctrl-single,function-mask = <0xff1f>;
+		};
+	};
+};
+
 #include "omap3.dtsi"
 
 / {

@@ -25,19 +40,6 @@
 			clock-latency = <300000>; /* From legacy driver */
 		};
 	};
-
-	ocp {
-		omap3_pmx_core2: pinmux at 480025d8 {
-			compatible = "ti,omap3-padconf", "pinctrl-single";
-			reg = <0x480025d8 0x24>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			#interrupt-cells = <1>;
-			interrupt-controller;
-			pinctrl-single,register-width = <16>;
-			pinctrl-single,function-mask = <0xff1f>;
-		};
-	};
 };
 
 /include/ "omap34xx-omap36xx-clocks.dtsi"
arch/arm/boot/dts/omap36xx.dtsi +21 -19
index 22cf464..fad05f3 100644
@@ -8,26 +8,7 @@
  * kind, whether express or implied.
  */
 
-#include "omap3.dtsi"
-
 / {
-	aliases {
-		serial3 = &uart4;
-	};
-
-	cpus {
-		/* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */
-		cpu at 0 {
-			operating-points = <
-				/* kHz    uV */
-				300000  1012500
-				600000  1200000
-				800000  1325000
-			>;
-			clock-latency = <300000>; /* From legacy driver */
-		};
-	};
-
 	ocp {
 		uart4: serial at 49042000 {
 			compatible = "ti,omap3-uart";

@@ -72,6 +53,27 @@
 	};
 };
 
+#include "omap3.dtsi"
+
+/ {
+	aliases {
+		serial3 = &uart4;
+	};
+
+	cpus {
+		/* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */
+		cpu at 0 {
+			operating-points = <
+				/* kHz    uV */
+				300000  1012500
+				600000  1200000
+				800000  1325000
+			>;
+			clock-latency = <300000>; /* From legacy driver */
+		};
+	};
+};
+
 /* OMAP3630 needs dss_96m_fck for VENC */
 &venc {
 	clocks = <&dss_tv_fck>, <&dss_96m_fck>;
Signature · 1 line
1.7.10.4
maintainer
#7 lore raw

PATCH 2/5 ARM: dts: OMAP3: reorder pinmux_gpio1_pins

Quoted 7 lines · Christoph Fritz

pinctrl-single for omap3_pmx_core2 gets deferred which results in some corrupt IRQs so that mmc, spi and dss stop working.

Diff of bootlog with (good) and without (fail) this patch:

fail

Quoted 8 lines
fail renamed from good +2 -1
 cpuidle: using governor ladder
 cpuidle: using governor menu
 Reprogramming SDRC clock to 400000000 Hz
-pinctrl-single 480025a0.pinmux: 46 pins at pa fa0025a0 size 92
 pinctrl-single 48002030.pinmux: 282 pins at pa fa002030 size 564
 pinctrl-single 48002a00.pinmux: 46 pins at pa fa002a00 size 92
+omap_gpio 48310000.gpio: could not find pctldev for node /ocp/pinmux at 480025a0/pinmux_gpio1_pins, deferring probe
+platform 48310000.gpio: Driver omap_gpio requests probe deferral

I believe this issue too gets fixed because of the drivers/Makefile order if we make them all module_init.

Regards,

Tony

author
#8 lore raw

PATCH 3/5 ARM: dts: omap3: set mcbsp2 status

In reply to Christoph Fritz

This patch fixes audio support for omap3-lilly-a83x.

Signed-off-by Christoph Fritz <[email protected]>
---
 arch/arm/boot/dts/omap3-lilly-a83x.dtsi |    4 ++++
 1 file changed, 4 insertions(+)
arch/arm/boot/dts/omap3-lilly-a83x.dtsi +4 -0
index cc1dce6..2b3af90 100644
@@ -357,6 +357,10 @@
 	power = <50>;
 };
 
+&mcbsp2 {
+	status = "okay";
+};
+
 &gpmc {
 	ranges = <0 0 0x30000000 0x1000000>,
 		<7 0 0x15000000 0x01000000>;
Signature · 1 line
1.7.10.4
maintainer
#9 lore raw

PATCH 3/5 ARM: dts: omap3: set mcbsp2 status

Quoted 1 line · Christoph Fritz

This patch fixes audio support for omap3-lilly-a83x.

Applying this into omap-for-v3.16/dt-v2 thanks.

Tony

Quoted 23 lines
Signed-off-by Christoph Fritz <[email protected]>
---
 arch/arm/boot/dts/omap3-lilly-a83x.dtsi |    4 ++++
 1 file changed, 4 insertions(+)
arch/arm/boot/dts/omap3-lilly-a83x.dtsi +4 -0
index cc1dce6..2b3af90 100644
@@ -357,6 +357,10 @@
 	power = <50>;
 };
 
+&mcbsp2 {
+	status = "okay";
+};
+
 &gpmc {
 	ranges = <0 0 0x30000000 0x1000000>,
 		<7 0 0x15000000 0x01000000>;
Signature · 1 line
1.7.10.4
author
#10 lore raw

RFC PATCH 4/5 ARM: OMAP2+: gpmc: fix gpmc_hwecc_bch_capable

In reply to Christoph Fritz

Most dt omap3 boards configure nand-ecc-opt as bch8. Due to lack of hardware elm support, bch8 software implementation gets set.

Since commit 0611c41934ab35ce84dea "ARM: OMAP2+: gpmc: update gpmc_hwecc_bch_capable() for new platforms and ECC schemes", nand support stops working.

This patch allows ecc software fallback.

---
 arch/arm/mach-omap2/gpmc-nand.c |   16 ++++++----------
 1 file changed, 6 insertions(+), 10 deletions(-)
arch/arm/mach-omap2/gpmc-nand.c +6 -10
index 4349e82..52c4834 100644
@@ -43,13 +43,17 @@ static struct platform_device gpmc_nand_device = {
 	.resource	= gpmc_nand_resource,
 };
 
-static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
+static bool gpmc_ecc_bch_capable(enum omap_ecc ecc_opt)
 {
 	/* platforms which support all ECC schemes */
 	if (soc_is_am33xx() || cpu_is_omap44xx() ||
 		 soc_is_omap54xx() || soc_is_dra7xx())
 		return 1;
 
+	if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW) ||
+		(ecc_opt == OMAP_ECC_BCH8_CODE_HW_DETECTION_SW))
+		return 1;
+
 	/* OMAP3xxx do not have ELM engine, so cannot support ECC schemes
 	 * which require H/W based ECC error detection */
 	if ((cpu_is_omap34xx() || cpu_is_omap3630()) &&

@@ -57,14 +61,6 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
 		 (ecc_opt == OMAP_ECC_BCH8_CODE_HW)))
 		return 0;
 
-	/*
-	 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1
-	 * and AM33xx derivates. Other chips may be added if confirmed to work.
-	 */
-	if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW) &&
-	    (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)))
-		return 0;
-
 	/* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
 	if (ecc_opt == OMAP_ECC_HAM1_CODE_HW)
 		return 1;

@@ -140,7 +136,7 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
 
 	gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
 
-	if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) {
+	if (!gpmc_ecc_bch_capable(gpmc_nand_data->ecc_opt)) {
 		dev_err(dev, "Unsupported NAND ECC scheme selected\n");
 		return -EINVAL;
 	}
Signature · 1 line
1.7.10.4
#11 lore raw

RFC PATCH 4/5 ARM: OMAP2+: gpmc: fix gpmc_hwecc_bch_capable

Quoted 11 lines

From: Christoph Fritz [mailto:chf.fritz at googlemail.com]

Most dt omap3 boards configure nand-ecc-opt as bch8. Due to lack of hardware elm support, bch8 software implementation gets set.

Since commit 0611c41934ab35ce84dea "ARM: OMAP2+: gpmc: update gpmc_hwecc_bch_capable() for new platforms and ECC schemes", nand support stops working.

This patch allows ecc software fallback.

Pleas add following tag at top of commit message.

Fixes commit 0611c41934ab35ce84dea34ab291897ad3cbc7be

ARM: OMAP2+: gpmc: update gpmc_hwecc_bch_capable() for new platforms and ECC schemes

And please mark it for 3.15 stable if this gets accepted after 3.15-rcx.
Cc: <[email protected]> # 3.15.x+

Quoted 9 lines

---
arch/arm/mach-omap2/gpmc-nand.c | 16 ++++++----------

1 file changed, 6 insertions(+), 10 deletions(-)
arch/arm/mach-omap2/gpmc-nand.c +0 -0
index 4349e82..52c4834 100644

arch/arm/mach-omap2/gpmc-nand.c static struct platform_device gpmc_nand_device = { · line 46

Quoted 5 lines
arch/arm/mach-omap2/gpmc-nand.c +1 -1
@@ -43,13 +43,17 @@ static struct platform_device gpmc_nand_device = {
 	.resource	= gpmc_nand_resource,
 };
 
-static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
+static bool gpmc_ecc_bch_capable(enum omap_ecc ecc_opt)

I don't think this renaming is really required with this fix, so please drop it and just keep it simple only for OMAP3 fix.

arch/arm/mach-omap2/gpmc-nand.c static struct platform_device gpmc_nand_device = { · line 56

Quoted 10 lines
arch/arm/mach-omap2/gpmc-nand.c +4 -0
 {
 	/* platforms which support all ECC schemes */
 	if (soc_is_am33xx() || cpu_is_omap44xx() ||
 		 soc_is_omap54xx() || soc_is_dra7xx())
 		return 1;
 
+	if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW) ||
+		(ecc_opt == OMAP_ECC_BCH8_CODE_HW_DETECTION_SW))
+		return 1;
+

Note: Some very old legacy platforms have initial version of GPMC engine which only supports Hamming ECC, and not BCH ECC scheme, so lets filter them out to maintain backward compatibility.

(1) As per TRM, OMAP2 platform does not support BCH ECC schemes, So please filter out OMAP2 devices from this check ...

(2) I don't know the history but below comment says:
"* For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1"

if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW) ||

	 (ecc_opt == OMAP_ECC_BCH8_CODE_HW_DETECTION_SW))  {
	if (cpu_is_omap24xx())
		return 0;
	else if (cpu_is_omap3630() && (GET_OMAP_REVISION() == 0))
		return 0;
	else
		return 1;
}
Quoted 5 lines
arch/arm/mach-omap2/gpmc-nand.c +0 -0
 	/* OMAP3xxx do not have ELM engine, so cannot support ECC schemes
 	 * which require H/W based ECC error detection */
 	if ((cpu_is_omap34xx() || cpu_is_omap3630()) &&

@@ -57,14 +61,6 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
 		 (ecc_opt == OMAP_ECC_BCH8_CODE_HW)))

arch/arm/mach-omap2/gpmc-nand.c static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) · line 67

Quoted 10 lines
arch/arm/mach-omap2/gpmc-nand.c +0 -8
 		return 0;
 
-	/*
-	 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1
-	 * and AM33xx derivates. Other chips may be added if confirmed to work.
-	 */
-	if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW) &&
-	    (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)))
-		return 0;
-

Thanks for removing this, I too wasn't confident of this either.

arch/arm/mach-omap2/gpmc-nand.c int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, · line 139

Quoted 9 lines
arch/arm/mach-omap2/gpmc-nand.c +1 -1
 	/* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
 	if (ecc_opt == OMAP_ECC_HAM1_CODE_HW)
 		return 1;

@@ -140,7 +136,7 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
 
 	gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
 
-	if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) {
+	if (!gpmc_ecc_bch_capable(gpmc_nand_data->ecc_opt)) {

Please drop this renaming from this patch.

Quoted 5 lines
arch/arm/mach-omap2/gpmc-nand.c +0 -1
 		dev_err(dev, "Unsupported NAND ECC scheme selected\n");
 		return -EINVAL;
 	}
--

1.7.10.4

You may send this patch separately apart from the series, so that this gets accepted in current 3.15-rcx.

with regards, pekon

#12 lore raw

RFC PATCH 4/5 ARM: OMAP2+: gpmc: fix gpmc_hwecc_bch_capable

Hi Cristoph,

Quoted 109 lines

From: Pekon Gupta <[email protected]>

Quoted 11 lines

From: Christoph Fritz [mailto:chf.fritz at googlemail.com]

Most dt omap3 boards configure nand-ecc-opt as bch8. Due to lack of hardware elm support, bch8 software implementation gets set.

Since commit 0611c41934ab35ce84dea "ARM: OMAP2+: gpmc: update gpmc_hwecc_bch_capable() for new platforms and ECC schemes", nand support stops working.

This patch allows ecc software fallback.

Pleas add following tag at top of commit message.

Fixes commit 0611c41934ab35ce84dea34ab291897ad3cbc7be

ARM: OMAP2+: gpmc: update gpmc_hwecc_bch_capable() for new platforms and ECC schemes

And please mark it for 3.15 stable if this gets accepted after 3.15-rcx.
Cc: <[email protected]> # 3.15.x+

Quoted 9 lines

---
arch/arm/mach-omap2/gpmc-nand.c | 16 ++++++----------

1 file changed, 6 insertions(+), 10 deletions(-)
arch/arm/mach-omap2/gpmc-nand.c +0 -0
index 4349e82..52c4834 100644

arch/arm/mach-omap2/gpmc-nand.c static struct platform_device gpmc_nand_device = { · line 46

Quoted 5 lines
arch/arm/mach-omap2/gpmc-nand.c +1 -1
@@ -43,13 +43,17 @@ static struct platform_device gpmc_nand_device = {
 	.resource	= gpmc_nand_resource,
 };
 
-static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
+static bool gpmc_ecc_bch_capable(enum omap_ecc ecc_opt)

I don't think this renaming is really required with this fix, so please drop it and just keep it simple only for OMAP3 fix.

arch/arm/mach-omap2/gpmc-nand.c static struct platform_device gpmc_nand_device = { · line 56

Quoted 10 lines
arch/arm/mach-omap2/gpmc-nand.c +4 -0
 {
 	/* platforms which support all ECC schemes */
 	if (soc_is_am33xx() || cpu_is_omap44xx() ||
 		 soc_is_omap54xx() || soc_is_dra7xx())
 		return 1;
 
+	if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW) ||
+		(ecc_opt == OMAP_ECC_BCH8_CODE_HW_DETECTION_SW))
+		return 1;
+

Note: Some very old legacy platforms have initial version of GPMC engine which only supports Hamming ECC, and not BCH ECC scheme, so lets filter them out to maintain backward compatibility.

(1) As per TRM, OMAP2 platform does not support BCH ECC schemes, So please filter out OMAP2 devices from this check ...

(2) I don't know the history but below comment says:
"* For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1"

if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW) ||

	 (ecc_opt == OMAP_ECC_BCH8_CODE_HW_DETECTION_SW))  {
	if (cpu_is_omap24xx())
		return 0;
	else if (cpu_is_omap3630() && (GET_OMAP_REVISION() == 0))
		return 0;
	else
		return 1;
}
Quoted 5 lines
arch/arm/mach-omap2/gpmc-nand.c +0 -0
 	/* OMAP3xxx do not have ELM engine, so cannot support ECC schemes
 	 * which require H/W based ECC error detection */
 	if ((cpu_is_omap34xx() || cpu_is_omap3630()) &&

@@ -57,14 +61,6 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
 		 (ecc_opt == OMAP_ECC_BCH8_CODE_HW)))

arch/arm/mach-omap2/gpmc-nand.c static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) · line 67

Quoted 10 lines
arch/arm/mach-omap2/gpmc-nand.c +0 -8
 		return 0;
 
-	/*
-	 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1
-	 * and AM33xx derivates. Other chips may be added if confirmed to work.
-	 */
-	if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW) &&
-	    (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)))
-		return 0;
-

Thanks for removing this, I too wasn't confident of this either.

arch/arm/mach-omap2/gpmc-nand.c int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, · line 139

Quoted 9 lines
arch/arm/mach-omap2/gpmc-nand.c +1 -1
 	/* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
 	if (ecc_opt == OMAP_ECC_HAM1_CODE_HW)
 		return 1;

@@ -140,7 +136,7 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
 
 	gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
 
-	if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) {
+	if (!gpmc_ecc_bch_capable(gpmc_nand_data->ecc_opt)) {

Please drop this renaming from this patch.

Quoted 5 lines
arch/arm/mach-omap2/gpmc-nand.c +0 -1
 		dev_err(dev, "Unsupported NAND ECC scheme selected\n");
 		return -EINVAL;
 	}
--

1.7.10.4

Quoted 4 lines

You may send this patch separately apart from the series, so that this gets accepted in current 3.15-rcx.

with regards, Pekon

Do you plan to re-spin this patch with above comments, and mark it for stable? It would be helpful for all OMAP3 users.

with regards, pekon

author
#13 lore raw

RFC PATCH 4/5 ARM: OMAP2+: gpmc: fix gpmc_hwecc_bch_capable

Quoted 3 lines · Pekon

Do you plan to re-spin this patch with above comments, and mark it for stable? It would be helpful for all OMAP3 users.

Thanks for the reminder. I'll respin the patchset this weekend.

-- Christoph

author
#14 lore raw

PATCH 5/5 ARM: dts: OMAP3 a83x: fix duplicate usb pin config

In reply to Christoph Fritz

Node usbhshost is supporting pinctrl, so the deprecated quirk call can be removed.

Signed-off-by Christoph Fritz <[email protected]>
---
 arch/arm/boot/dts/omap3-lilly-a83x.dtsi |    3 ---
 1 file changed, 3 deletions(-)
arch/arm/boot/dts/omap3-lilly-a83x.dtsi +0 -3
index 2b3af90..d973088 100644
@@ -176,9 +176,6 @@
 
 &omap3_pmx_core2 {
 	pinctrl-names = "default";
-	pinctrl-0 = <
-			&hsusb1_2_pins
-	>;
 
 	hsusb1_2_pins: pinmux_hsusb1_2_pins {
 		pinctrl-single,pins = <
Signature · 1 line
1.7.10.4
maintainer
#15 lore raw

PATCH 5/5 ARM: dts: OMAP3 a83x: fix duplicate usb pin config

Quoted 2 lines · Christoph Fritz

Node usbhshost is supporting pinctrl, so the deprecated quirk call can be removed.

Applying this too into omap-for-v3.16/dt-v2 thanks.

Tony

maintainer
#16 lore raw

cover ARM: omap3-lilly-a83x: update board support

In reply to Christoph Fritz
Quoted 4 lines · Christoph Fritz

This set of patches updates board support for omap3-lilly-a83x.

Christoph Fritz (5):
[RFC-HACK] pinctrl-single: init by postcore_initcall()

I would prefer to start initializing other things later as then we get proper error messages on the console. Let's first investigate a bit more if we can just initialize other drivers later on.

Which version of kernel are you using? With all the fixes that have gone into this -rc cycle, v3.15-rc4 is pretty much the first kernel that should behave for us properly for deferred probe for irqchips that get initialized later on.

Regards,

Tony

Quoted 15 lines

[RFC-HACK] ARM: dts: OMAP3: reorder pinmux_gpio1_pins
ARM: dts: omap3: set mcbsp2 status
[RFC] ARM: OMAP2+: gpmc: fix gpmc_hwecc_bch_capable
ARM: dts: OMAP3 a83x: fix duplicate usb pin config

 arch/arm/boot/dts/omap3-lilly-a83x.dtsi |    7 +++---
 arch/arm/boot/dts/omap34xx.dtsi         |   28 ++++++++++++----------
 arch/arm/boot/dts/omap36xx.dtsi         |   40 ++++++++++++++++---------------
 arch/arm/mach-omap2/gpmc-nand.c         |   16 +++++--------
 drivers/pinctrl/pinctrl-single.c        |   15 ++++++++++++
 5 files changed, 61 insertions(+), 45 deletions(-)
Signature · 1 line
1.7.10.4
author
#17 lore raw

cover ARM: omap3-lilly-a83x: update board support

Quoted 11 lines · Tony Lindgren
Quoted 4 lines · Christoph Fritz

This set of patches updates board support for omap3-lilly-a83x.

Christoph Fritz (5):
[RFC-HACK] pinctrl-single: init by postcore_initcall()

I would prefer to start initializing other things later as then we get proper error messages on the console. Let's first investigate a bit more if we can just initialize other drivers later on.

Quoted 4 lines

Which version of kernel are you using? With all the fixes that have gone into this -rc cycle, v3.15-rc4 is pretty much the first kernel that should behave for us properly for deferred probe for irqchips that get initialized later on.

It's 3.15-rc6.