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ARM: i.MX: Use of_clk_get_by_name() for timer clocks for DT case.

PATCH New Alexander Shiyan 2 participants 3 messages May 27, 2014 – May 30, 2014

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm i.MX and Layerscape
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Alexander Shiyan

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#0 lore raw

PATCH 1/2 ARM: i.MX: Use of_clk_get_by_name() for timer clocks for DT case.

Use of_clk_get_by_name() for timer clocks for DT case. This patch eliminates a lot of unneeded clk_register_clkdev() calls for GPT.

Signed-off-by Alexander Shiyan <[email protected]>
---
 arch/arm/mach-imx/clk-imx1.c        |  5 ++---
 arch/arm/mach-imx/clk-imx25.c       |  5 ++---
 arch/arm/mach-imx/clk-imx51-imx53.c |  2 --
 arch/arm/mach-imx/clk-imx6q.c       |  2 --
 arch/arm/mach-imx/clk-imx6sl.c      |  3 ---
 arch/arm/mach-imx/clk-imx6sx.c      |  3 ---
 arch/arm/mach-imx/time.c            | 33 +++++++++++++++++++++------------
 7 files changed, 25 insertions(+), 28 deletions(-)
arch/arm/mach-imx/clk-imx1.c +2 -3
index e9c391b..96b1eb6 100644
@@ -76,9 +76,6 @@ static void __init _mx1_clocks_init(unsigned long fref)
 		if (IS_ERR(clk[i]))
 			pr_err("imx1 clk %d: register failed with %ld\n",
 				i, PTR_ERR(clk[i]));
-
-	clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx-gpt.0");
-	clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx-gpt.0");
 }
 
 int __init mx1_clocks_init(unsigned long fref)

@@ -87,6 +84,8 @@ int __init mx1_clocks_init(unsigned long fref)
 
 	_mx1_clocks_init(fref);
 
+	clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx-gpt.0");
+	clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx-gpt.0");
 	clk_register_clkdev(clk[IMX1_CLK_DMA_GATE], "ahb", "imx1-dma");
 	clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-dma");
 	clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.0");
arch/arm/mach-imx/clk-imx25.c +2 -3
index ae578c0..2423c09 100644
@@ -234,9 +234,6 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
 	/* Clock source for gpt must be derived from AHB */
 	clk_set_parent(clk[per5_sel], clk[ahb]);
 
-	clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
-	clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
-
 	/*
 	 * Let's initially set up CLKO parent as ipg, since this configuration
 	 * is used on some imx25 board designs to clock the audio codec.

@@ -250,6 +247,8 @@ int __init mx25_clocks_init(void)
 {
 	__mx25_clocks_init(24000000);
 
+	clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
+	clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
 	/* i.mx25 has the i.mx21 type uart */
 	clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
 	clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
arch/arm/mach-imx/clk-imx51-imx53.c +0 -2
index 4e95865..e293f6a 100644
@@ -292,8 +292,6 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base)
 			pr_err("i.MX5 clk %d: register failed with %ld\n",
 				i, PTR_ERR(clk[i]));
 
-	clk_register_clkdev(clk[IMX5_CLK_GPT_HF_GATE], "per", "imx-gpt.0");
-	clk_register_clkdev(clk[IMX5_CLK_GPT_IPG_GATE], "ipg", "imx-gpt.0");
 	clk_register_clkdev(clk[IMX5_CLK_UART1_PER_GATE], "per", "imx21-uart.0");
 	clk_register_clkdev(clk[IMX5_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
 	clk_register_clkdev(clk[IMX5_CLK_UART2_PER_GATE], "per", "imx21-uart.1");
arch/arm/mach-imx/clk-imx6q.c +0 -2
index 8e795de..3674eb9 100644
@@ -442,8 +442,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	clk_data.clk_num = ARRAY_SIZE(clk);
 	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-	clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
-	clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
 	clk_register_clkdev(clk[enet_ref], "enet_ref", NULL);
 
 	if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
arch/arm/mach-imx/clk-imx6sl.c +0 -3
index 5408ca7..7431bfa 100644
@@ -357,9 +357,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 	clk_data.clk_num = ARRAY_SIZE(clks);
 	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-	clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0");
-	clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
-
 	/* Ensure the AHB clk is at 132MHz. */
 	ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
 	if (ret)
arch/arm/mach-imx/clk-imx6sx.c +0 -3
index 72f8902..5211cf6 100644
@@ -451,9 +451,6 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
 	clk_data.clk_num = ARRAY_SIZE(clks);
 	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-	clk_register_clkdev(clks[IMX6SX_CLK_GPT_BUS], "ipg", "imx-gpt.0");
-	clk_register_clkdev(clks[IMX6SX_CLK_GPT_SERIAL], "per", "imx-gpt.0");
-
 	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
 		clk_prepare_enable(clks[clks_init_on[i]]);
arch/arm/mach-imx/time.c +21 -12
index bed081e..2d96051 100644
@@ -290,23 +290,20 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
 	return 0;
 }
 
-void __init mxc_timer_init(void __iomem *base, int irq)
+static void __init _mxc_timer_init(void __iomem *base, int irq,
+				   struct clk *clk_per, struct clk *clk_ipg)
 {
 	uint32_t tctl_val;
-	struct clk *timer_clk;
-	struct clk *timer_ipg_clk;
 
-	timer_clk = clk_get_sys("imx-gpt.0", "per");
-	if (IS_ERR(timer_clk)) {
+	if (IS_ERR(clk_per)) {
 		pr_err("i.MX timer: unable to get clk\n");
 		return;
 	}
 
-	timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
-	if (!IS_ERR(timer_ipg_clk))
-		clk_prepare_enable(timer_ipg_clk);
+	if (!IS_ERR(clk_ipg))
+		clk_prepare_enable(clk_ipg);
 
-	clk_prepare_enable(timer_clk);
+	clk_prepare_enable(clk_per);
 
 	timer_base = base;
 

@@ -325,15 +322,24 @@ void __init mxc_timer_init(void __iomem *base, int irq)
 	__raw_writel(tctl_val, timer_base + MXC_TCTL);
 
 	/* init and register the timer to the framework */
-	mxc_clocksource_init(timer_clk);
-	mxc_clockevent_init(timer_clk);
+	mxc_clocksource_init(clk_per);
+	mxc_clockevent_init(clk_per);
 
 	/* Make irqs happen */
 	setup_irq(irq, &mxc_timer_irq);
 }
 
+void __init mxc_timer_init(void __iomem *base, int irq)
+{
+	struct clk *clk_per = clk_get_sys("imx-gpt.0", "per");
+	struct clk *clk_ipg = clk_get_sys("imx-gpt.0", "ipg");
+
+	_mxc_timer_init(base, irq, clk_per, clk_ipg);
+}
+
 void __init mxc_timer_init_dt(struct device_node *np)
 {
+	struct clk *clk_per, *clk_ipg;
 	void __iomem *base;
 	int irq;
 

@@ -341,5 +347,8 @@ void __init mxc_timer_init_dt(struct device_node *np)
 	WARN_ON(!base);
 	irq = irq_of_parse_and_map(np, 0);
 
-	mxc_timer_init(base, irq);
+	clk_per = of_clk_get_by_name(np, "per");
+	clk_ipg = of_clk_get_by_name(np, "ipg");
+
+	_mxc_timer_init(base, irq, clk_per, clk_ipg);
 }
Signature · 1 line
1.8.5.5
author
#1 lore raw

PATCH 2/2 ARM: i.MX: Remove excess variable

Base address for driver is global, there are no need to use intermediate variable for it.

Signed-off-by Alexander Shiyan <[email protected]>
---
 arch/arm/mach-imx/time.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)
arch/arm/mach-imx/time.c +7 -8
index 2d96051..1da2270 100644
@@ -290,7 +290,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
 	return 0;
 }
 
-static void __init _mxc_timer_init(void __iomem *base, int irq,
+static void __init _mxc_timer_init(int irq,
 				   struct clk *clk_per, struct clk *clk_ipg)
 {
 	uint32_t tctl_val;

@@ -305,8 +305,6 @@ static void __init _mxc_timer_init(void __iomem *base, int irq,
 
 	clk_prepare_enable(clk_per);
 
-	timer_base = base;
-
 	/*
 	 * Initialise to a known state (all timers off, and timing reset)
 	 */

@@ -334,21 +332,22 @@ void __init mxc_timer_init(void __iomem *base, int irq)
 	struct clk *clk_per = clk_get_sys("imx-gpt.0", "per");
 	struct clk *clk_ipg = clk_get_sys("imx-gpt.0", "ipg");
 
-	_mxc_timer_init(base, irq, clk_per, clk_ipg);
+	timer_base = base;
+
+	_mxc_timer_init(irq, clk_per, clk_ipg);
 }
 
 void __init mxc_timer_init_dt(struct device_node *np)
 {
 	struct clk *clk_per, *clk_ipg;
-	void __iomem *base;
 	int irq;
 
-	base = of_iomap(np, 0);
-	WARN_ON(!base);
+	timer_base = of_iomap(np, 0);
+	WARN_ON(!timer_base);
 	irq = irq_of_parse_and_map(np, 0);
 
 	clk_per = of_clk_get_by_name(np, "per");
 	clk_ipg = of_clk_get_by_name(np, "ipg");
 
-	_mxc_timer_init(base, irq, clk_per, clk_ipg);
+	_mxc_timer_init(irq, clk_per, clk_ipg);
 }
Signature · 1 line
1.8.5.5