ARM: shmobile: koelsch reference: Enable DMA for QSPI
Subsystems (4)
v2 cover ARM: shmobile: koelsch reference: Enable DMA for QSPI
This patch series enables DMA support for QSPI on r8a7791/koelsch reference. It's independent from the series "ARM: shmobile: koelsch
legacy: Enable DMA for QSPI", but it depends on the SHDMA work for r8a7790 by Ben Dooks (cfr. "[PATCH v2 0/9] Updates Renesas OF-DMA code").
Changes Compared to previous submission ("[PATCH/RFC 0/7] ARM: shmobile:
r8a7791: Add preliminary DMA support"):
- "[6/7] ARM: shmobile: r8a7791 dtsi: Enable DMA for MSIOF" was dropped,
- 2/7 was added,
- 7/7 was changed (see changelog in individual patch).
This was tested on r8a7791/koelsch.
Performance figures for reading from a QSPI FLASH driven at 24.375 MHz are:
- Single: 1.1 Mbps PIO, 23 Mbps DMA
- Dual : 12.7 Mbps PIO, 48 Mbps DMA
- Quad : 13 Mbps PIO, 70 Mbps DMA
Thanks for your comments!
[1/7] DMA: shdma: Add r8a7791 support
[2/7] DMA: shdma: Spelling s/controll/control/
[3/7] ARM: shmobile: r8a7791 dtsi: add SYS-DMAC clocks
[4/7] ARM: shmobile: r8a7791: Add SYS-DMAC channel definitions for bindings [5/7] ARM: shmobile: r8a7791 dtsi: Add SYS-DMAC0 and SYS-DMAC1 nodes [6/7] ARM: shmobile: koelsch dts: Enable sysdma0 and sysdma1 [7/7] ARM: shmobile: r8a7791 dtsi: Enable DMA for QSPI
Documentation/devicetree/bindings/dma/shdma.txt | 7 +- arch/arm/boot/dts/r8a7791-koelsch.dts | 8 ++ arch/arm/boot/dts/r8a7791.dtsi | 79 ++++++++++++++++- drivers/dma/sh/shdmac.c | 1 + include/dt-bindings/dma/r8a7791-dma.h | 111 ++++++++++++++++++++++++ 5 files changed, 201 insertions(+), 5 deletions(-) create mode 100644 include/dt-bindings/dma/r8a7791-dma.h
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH v2 1/7 DMA: shdma: Add r8a7791 support
---
v2:
- No changes
Documentation/devicetree/bindings/dma/shdma.txt | 5 +++-- drivers/dma/sh/shdmac.c | 1 + 2 files changed, 4 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/dma/shdma.txt +3 -2
@@ -24,8 +24,9 @@ Optional properties (currently unused): Required properties: - compatible: should be of the form "renesas,shdma-<soc>", where <soc> should be replaced with the desired SoC model, e.g. - "renesas,shdma-r8a73a4" for the system DMAC on r8a73a4 SoC - "renesas,shdma-r8a7790" for the DMAC on the R8A7790. + "renesas,shdma-r8a73a4" for the system DMAC on r8a73a4 SoC, + "renesas,shdma-r8a7790" for the DMAC on the R8A7790, + "renesas,shdma-r8a7791" for the DMAC on the R8A7791. Example: dmac: dma-multiplexer at 0 {
drivers/dma/sh/shdmac.c +1 -0
@@ -691,6 +691,7 @@ static const struct shdma_ops sh_dmae_shdma_ops = {static const struct of_device_id sh_dmae_of_match[] = { { .compatible ="renesas,shdma-r8a73a4" , .data = r8a73a4_shdma_devid }, { .compatible ="renesas,shdma-r8a7790" , .data = &shdma_arm_info }, + { .compatible ="renesas,shdma-r8a7791" , .data = &shdma_arm_info }, {} };MODULE_DEVICE_TABLE (of, sh_dmae_of_match);
Signature · 1 line
1.9.1
PATCH v2 1/7 DMA: shdma: Add r8a7791 support
Hi Geert,
Thank you for the patch.
On Monday 02 June 2014 15:42:05 Geert Uytterhoeven wrote:
Missing commit message ?
Quoted 18 lines
Signed-off-by Geert Uytterhoeven <[email protected]>---
v2:
- No changesDocumentation/devicetree/bindings/dma/shdma.txt | 5 +++-- drivers/dma/sh/shdmac.c | 1 + 2 files changed, 4 insertions(+), 2 deletions(-)(quoted diff) +0
-0
b/Documentation/devicetree/bindings/dma/shdma.txtindex86d5c509594b..d26b7065ae94100644Documentation/devicetree/bindings/dma/shdma.txt +0
-0@@ -24,8 +24,9 @@ Optional properties (currently unused): Required properties: - compatible: should be of the form "renesas,shdma-<soc>", where <soc>should be replaced with the desired SoC model, e.g.
Documentation/devicetree/bindings/dma/shdma.txt Optional properties (currently unused): · line 29
Quoted 5 lines
Documentation/devicetree/bindings/dma/shdma.txt +3
-2- "renesas,shdma-r8a73a4" for the system DMAC on r8a73a4 SoC - "renesas,shdma-r8a7790" for the DMAC on the R8A7790. + "renesas,shdma-r8a73a4" for the system DMAC on r8a73a4 SoC, + "renesas,shdma-r8a7790" for the DMAC on the R8A7790, + "renesas,shdma-r8a7791" for the DMAC on the R8A7791.
I would just remove the commas and full stop to avoid modifying unrelated lines in future patches.
The R8A7791 has several DMACs (LBSC, SYS, RT, Audio, 2D, USBHS). It would thus make sense to explicitly state which DMACs the bindings cover.
Quoted 14 lines
Example:
Documentation/devicetree/bindings/dma/shdma.txt +0
-0dmac: dma-multiplexer at 0 {drivers/dma/sh/shdmac.c +1
-0@@ -691,6 +691,7 @@ static const struct shdma_ops sh_dmae_shdma_ops = {static const struct of_device_id sh_dmae_of_match[] = { { .compatible ="renesas,shdma-r8a73a4" , .data = r8a73a4_shdma_devid }, { .compatible ="renesas,shdma-r8a7790" , .data = &shdma_arm_info }, + { .compatible ="renesas,shdma-r8a7791" , .data = &shdma_arm_info }, {} };MODULE_DEVICE_TABLE (of, sh_dmae_of_match);
Signature · 3 lines
Regards, Laurent Pinchart
PATCH v2 1/7 DMA: shdma: Add r8a7791 support
Quoted 3 lines · Laurent Pinchart
On Monday 02 June 2014 15:42:05 Geert Uytterhoeven wrote:
Missing commit message ?
I didn't have anything more to say than the one-liner ;-)
Quoted 27 lines
Quoted 18 lines
Signed-off-by Geert Uytterhoeven <[email protected]>---
v2:
- No changesDocumentation/devicetree/bindings/dma/shdma.txt | 5 +++-- drivers/dma/sh/shdmac.c | 1 + 2 files changed, 4 insertions(+), 2 deletions(-)(quoted diff) +0
-0
b/Documentation/devicetree/bindings/dma/shdma.txtindex86d5c509594b..d26b7065ae94100644Documentation/devicetree/bindings/dma/shdma.txt +0
-0@@ -24,8 +24,9 @@ Optional properties (currently unused): Required properties: - compatible: should be of the form "renesas,shdma-<soc>", where <soc>should be replaced with the desired SoC model, e.g.
Documentation/devicetree/bindings/dma/shdma.txt Optional properties (currently unused): · line 29
Quoted 5 lines
Documentation/devicetree/bindings/dma/shdma.txt +3
-2- "renesas,shdma-r8a73a4" for the system DMAC on r8a73a4 SoC - "renesas,shdma-r8a7790" for the DMAC on the R8A7790. + "renesas,shdma-r8a73a4" for the system DMAC on r8a73a4 SoC, + "renesas,shdma-r8a7790" for the DMAC on the R8A7790, + "renesas,shdma-r8a7791" for the DMAC on the R8A7791.I would just remove the commas and full stop to avoid modifying unrelated lines in future patches.
Quoted 2 lines
The R8A7791 has several DMACs (LBSC, SYS, RT, Audio, 2D, USBHS). It would thus make sense to explicitly state which DMACs the bindings cover.
Good point. That also applies to the r8a7790.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH v2 2/7 DMA: shdma: Spelling s/controll/control/
In reply to Geert Uytterhoeven---
v2:
- New
Documentation/devicetree/bindings/dma/shdma.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Documentation/devicetree/bindings/dma/shdma.txt +1 -1
@@ -73,7 +73,7 @@ Example: }; For r8a7790 and newer implementations, the information for the channel -controll register is found in the dma phandle and #dma-cells is set to 2. +control register is found in the dma phandle and #dma-cells is set to 2. dma0: dma-mux at 0 { compatible = "renesas,shdma-mux";
Signature · 1 line
1.9.1
PATCH v2 2/7 DMA: shdma: Spelling s/controll/control/
Quoted 14 lines · Geert Uytterhoeven
Signed-off-by Geert Uytterhoeven <[email protected]>---
v2:
- NewDocumentation/devicetree/bindings/dma/shdma.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)Documentation/devicetree/bindings/dma/shdma.txt +0
-0
Documentation/devicetree/bindings/dma/shdma.txt Example: · line 79
Quoted 8 lines
Documentation/devicetree/bindings/dma/shdma.txt +1
-1@@ -73,7 +73,7 @@ Example: }; For r8a7790 and newer implementations, the information for the channel -controll register is found in the dma phandle and #dma-cells is set to 2. +control register is found in the dma phandle and #dma-cells is set to 2. dma0: dma-mux at 0 { compatible = "renesas,shdma-mux";
Ok, if I don't fix this in the new series then you have my ack for this to be applied.
Signature · 2 lines
Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius
PATCH v2 2/7 DMA: shdma: Spelling s/controll/control/
In reply to Geert UytterhoevenHi Geert,
Thank you for the patch.
Quoted 1 line · On Monday 02 June 2014 15:42:06 Geert Uytterhoeven wrote:
Signed-off-by Geert Uytterhoeven <[email protected]>
Quoted 21 lines
---
v2:
- NewDocumentation/devicetree/bindings/dma/shdma.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)(quoted diff) +0
-0
b/Documentation/devicetree/bindings/dma/shdma.txtindexd26b7065ae94..2b61cab0525c100644Documentation/devicetree/bindings/dma/shdma.txt +1
-1@@ -73,7 +73,7 @@ Example: }; For r8a7790 and newer implementations, the information for the channel -controll register is found in the dma phandle and #dma-cells is set to 2. +control register is found in the dma phandle and #dma-cells is set to 2. dma0: dma-mux at 0 { compatible = "renesas,shdma-mux";
Signature · 3 lines
Regards, Laurent Pinchart
PATCH v2 3/7 ARM: shmobile: r8a7791 dtsi: add SYS-DMAC clocks
In reply to Geert UytterhoevenAdd clocks for the SYS-DMAC0 and SYS-DMAC1 hardware blocks.
Cfr. the r8a7790 version by Ben Dooks.
---
v2:
- No changes
arch/arm/boot/dts/r8a7791.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
arch/arm/boot/dts/r8a7791.dtsi +5 -2
@@ -743,16 +743,19 @@ compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&mp_clk>; + <&mp_clk>, <&mp_clk>, <&mp_clk>, + <&zs_clk>, <&zs_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 + R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0 >; clock-output-names = "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", - "scifb1", "msiof1", "scifb2"; + "scifb1", "msiof1", "scifb2", + "sys-dmac1", "sys-dmac0"; }; mstp3_clks: mstp3_clks at e615013c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
Signature · 1 line
1.9.1
PATCH v2 3/7 ARM: shmobile: r8a7791 dtsi: add SYS-DMAC clocks
Hi Geert,
Thank you for the patch.
Quoted 5 lines · On Monday 02 June 2014 15:42:07 Geert Uytterhoeven wrote:
Add clocks for the SYS-DMAC0 and SYS-DMAC1 hardware blocks.
Cfr. the r8a7790 version by Ben Dooks.
Signed-off-by Geert Uytterhoeven <[email protected]>
arch/arm/boot/dts/r8a7791.dtsi line 743
Quoted 13 lines
---
v2:
- No changesarch/arm/boot/dts/r8a7791.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)arch/arm/boot/dts/r8a7791.dtsi +0
-0@@ -743,16 +743,19 @@ compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-
clocks";
Quoted 20 lines
arch/arm/boot/dts/r8a7791.dtsi +5
-2reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&mp_clk>; + <&mp_clk>, <&mp_clk>, <&mp_clk>, + <&zs_clk>, <&zs_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 + R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0 >; clock-output-names = "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", - "scifb1", "msiof1", "scifb2"; + "scifb1", "msiof1", "scifb2", + "sys-dmac1", "sys-dmac0"; };
arch/arm/boot/dts/r8a7791.dtsi
Quoted 2 lines
arch/arm/boot/dts/r8a7791.dtsi +0
-0mstp3_clks: mstp3_clks at e615013c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-
clocks";
Signature · 3 lines
Regards, Laurent Pinchart
PATCH v2 3/7 ARM: shmobile: r8a7791 dtsi: add SYS-DMAC clocks
Quoted 4 lines · Laurent Pinchart
Hi Geert,
Thank you for the patch.
Quoted 8 lines
Quoted 5 lines · On Monday 02 June 2014 15:42:07 Geert Uytterhoeven wrote:
Add clocks for the SYS-DMAC0 and SYS-DMAC1 hardware blocks.
Cfr. the r8a7790 version by Ben Dooks.
Signed-off-by Geert Uytterhoeven <[email protected]>Acked-by Laurent Pinchart <[email protected]>
Thanks, I have queued this up.
PATCH v2 4/7 ARM: shmobile: r8a7791: Add SYS-DMAC channel definitions for bindings
In reply to Geert UytterhoevenAdd channel resource identifiers for the SYS DMA controller.
Cfr. the r8a7790 version by Ben Dooks.
---
v2:
- No changes
I don't like the CHCR_[RT]X_*BIT definitions
include/dt-bindings/dma/r8a7791-dma.h | 111 ++++++++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) create mode 100644 include/dt-bindings/dma/r8a7791-dma.h
include/dt-bindings/dma/r8a7791-dma.h new file +111 -0
@@ -0,0 +1,111 @@ +/* +* R8A7791 System DMA channel resource identifiers +*/ + +#ifndef __DT_BINDINGS_DMA_R8A7791_DMA_H__ +#define __DT_BINDINGS_DMA_R8A7791_DMA_H__ + +#include <dt-bindings/dma/shdma.h> + +/* System DMAC */ + +#define R8A7791_DMA_SCIFA0_TX (0x21) +#define R8A7791_DMA_SCIFA0_RX (0x22) +#define R8A7791_DMA_SCIFA1_TX (0x25) +#define R8A7791_DMA_SCIFA1_RX (0x26) +#define R8A7791_DMA_SCIFA2_TX (0x27) +#define R8A7791_DMA_SCIFA2_RX (0x28) +#define R8A7791_DMA_SCIFA3_TX (0x1B) +#define R8A7791_DMA_SCIFA3_RX (0x1C) +#define R8A7791_DMA_SCIFA4_TX (0x1F) +#define R8A7791_DMA_SCIFA4_RX (0x20) +#define R8A7791_DMA_SCIFA5_TX (0x23) +#define R8A7791_DMA_SCIFA5_RX (0x24) + +#define R8A7791_DMA_SCIFB0_TX (0x3D) +#define R8A7791_DMA_SCIFB0_RX (0x3E) +#define R8A7791_DMA_SCIFB1_TX (0x19) +#define R8A7791_DMA_SCIFB1_RX (0x1A) +#define R8A7791_DMA_SCIFB2_TX (0x1D) +#define R8A7791_DMA_SCIFB2_RX (0x1E) + +#define R8A7791_DMA_HSCIF0_TX (0x39) +#define R8A7791_DMA_HSCIF0_RX (0x3A) +#define R8A7791_DMA_HSCIF1_TX (0x4D) +#define R8A7791_DMA_HSCIF1_RX (0x4E) +#define R8A7791_DMA_HSCIF2_TX (0x3B) +#define R8A7791_DMA_HSCIF2_RX (0x3C) + +#define R8A7791_DMA_SCIF0_TX (0x29) +#define R8A7791_DMA_SCIF0_RX (0x2A) +#define R8A7791_DMA_SCIF1_TX (0x2D) +#define R8A7791_DMA_SCIF1_RX (0x2E) +#define R8A7791_DMA_SCIF2_TX (0x2B) +#define R8A7791_DMA_SCIF2_RX (0x2C) +#define R8A7791_DMA_SCIF3_TX (0x2F) +#define R8A7791_DMA_SCIF3_RX (0x30) +#define R8A7791_DMA_SCIF4_TX (0xFB) +#define R8A7791_DMA_SCIF4_RX (0xFC) +#define R8A7791_DMA_SCIF5_TX (0xFD) +#define R8A7791_DMA_SCIF5_RX (0xFE) + +#define R8A7791_DMA_MSIOF0_TX (0x51) +#define R8A7791_DMA_MSIOF0_RX (0x52) +#define R8A7791_DMA_MSIOF1_TX (0x55) +#define R8A7791_DMA_MSIOF1_RX (0x56) +#define R8A7791_DMA_MSIOF2_TX (0x41) +#define R8A7791_DMA_MSIOF2_RX (0x42) + +#define R8A7791_DMA_QSPI_TX (0x17) +#define R8A7791_DMA_QSPI_RX (0x18) + +#define R8A7791_DMA_SIM_TX (0xA1) +#define R8A7791_DMA_SIM_RX (0xA2) + +#define R8A7791_DMA_IIC0_TX (0x61) +#define R8A7791_DMA_IIC0_RX (0x62) +#define R8A7791_DMA_IIC1_TX (0x65) +#define R8A7791_DMA_IIC1_RX (0x66) +#define R8A7791_DMA_IICDVFS_TX (0x77) +#define R8A7791_DMA_IICDVFS_RX (0x78) + +#define R8A7791_DMA_SDHI0_TX (0xCD) +#define R8A7791_DMA_SDHI0_RX (0xCE) +#define R8A7791_DMA_SDHI2_TX (0xC1) +#define R8A7791_DMA_SDHI2_RX (0xC2) +#define R8A7791_DMA_SDHI2C2_TX (0xC5) +#define R8A7791_DMA_SDHI2C2_RX (0xC6) +#define R8A7791_DMA_SDHI3_TX (0xD3) +#define R8A7791_DMA_SDHI3_RX (0xD4) +#define R8A7791_DMA_SDHI3C2_TX (0xDF) +#define R8A7791_DMA_SDHI3C2_RX (0xDE) + +#define R8A7791_DMA_TPU0 (0xF1) +#define R8A7791_DMA_TSIF0 (0xEA) +#define R8A7791_DMA_TSIF1 (0xF0) + +#define R8A7791_DMA_AXISTATR (0xA6) +#define R8A7791_DMA_AXISTATS0 (0xAC) +#define R8A7791_DMA_AXISTATS1 (0xAA) +#define R8A7791_DMA_AXISTATS2 (0xA8) +#define R8A7791_DMA_AXISTATS3C (0xA4) + +#define R8A7791_DMA_MMCIF0_TX (0xD1) +#define R8A7791_DMA_MMCIF0_RX (0xD2) + +#define R8A7791_DMA_AXSTM (0xAE) + + +/* Misc */ + +// FIXME +#define CHCR_RX_8BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_8BIT) +#define CHCR_TX_8BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_8BIT) +#define CHCR_RX_16BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_16BIT) +#define CHCR_TX_16BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_16BIT) +#define CHCR_RX_32BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_32BIT) +#define CHCR_TX_32BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_32BIT) +#define CHCR_RX_256BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_256BIT) +#define CHCR_TX_256BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_256BIT) + +#endif /* __DT_BINDINGS_DMA_R8A7791_DMA_H__ */
Signature · 1 line
1.9.1
PATCH v2 4/7 ARM: shmobile: r8a7791: Add SYS-DMAC channel definitions for bindings
Quoted 120 lines · Geert Uytterhoeven
Add channel resource identifiers for the SYS DMA controller.
Cfr. the r8a7790 version by Ben Dooks.
Signed-off-by Geert Uytterhoeven <[email protected]>---
v2:
- No changesI don't like the CHCR_[RT]X_*BIT definitions
include/dt-bindings/dma/r8a7791-dma.h | 111 ++++++++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) create mode 100644 include/dt-bindings/dma/r8a7791-dma.hinclude/dt-bindings/dma/r8a7791-dma.h new file +99
-0@@ -0,0 +1,111 @@ +/* +* R8A7791 System DMA channel resource identifiers +*/ + +#ifndef __DT_BINDINGS_DMA_R8A7791_DMA_H__ +#define __DT_BINDINGS_DMA_R8A7791_DMA_H__ + +#include <dt-bindings/dma/shdma.h> + +/* System DMAC */ + +#define R8A7791_DMA_SCIFA0_TX (0x21) +#define R8A7791_DMA_SCIFA0_RX (0x22) +#define R8A7791_DMA_SCIFA1_TX (0x25) +#define R8A7791_DMA_SCIFA1_RX (0x26) +#define R8A7791_DMA_SCIFA2_TX (0x27) +#define R8A7791_DMA_SCIFA2_RX (0x28) +#define R8A7791_DMA_SCIFA3_TX (0x1B) +#define R8A7791_DMA_SCIFA3_RX (0x1C) +#define R8A7791_DMA_SCIFA4_TX (0x1F) +#define R8A7791_DMA_SCIFA4_RX (0x20) +#define R8A7791_DMA_SCIFA5_TX (0x23) +#define R8A7791_DMA_SCIFA5_RX (0x24) + +#define R8A7791_DMA_SCIFB0_TX (0x3D) +#define R8A7791_DMA_SCIFB0_RX (0x3E) +#define R8A7791_DMA_SCIFB1_TX (0x19) +#define R8A7791_DMA_SCIFB1_RX (0x1A) +#define R8A7791_DMA_SCIFB2_TX (0x1D) +#define R8A7791_DMA_SCIFB2_RX (0x1E) + +#define R8A7791_DMA_HSCIF0_TX (0x39) +#define R8A7791_DMA_HSCIF0_RX (0x3A) +#define R8A7791_DMA_HSCIF1_TX (0x4D) +#define R8A7791_DMA_HSCIF1_RX (0x4E) +#define R8A7791_DMA_HSCIF2_TX (0x3B) +#define R8A7791_DMA_HSCIF2_RX (0x3C) + +#define R8A7791_DMA_SCIF0_TX (0x29) +#define R8A7791_DMA_SCIF0_RX (0x2A) +#define R8A7791_DMA_SCIF1_TX (0x2D) +#define R8A7791_DMA_SCIF1_RX (0x2E) +#define R8A7791_DMA_SCIF2_TX (0x2B) +#define R8A7791_DMA_SCIF2_RX (0x2C) +#define R8A7791_DMA_SCIF3_TX (0x2F) +#define R8A7791_DMA_SCIF3_RX (0x30) +#define R8A7791_DMA_SCIF4_TX (0xFB) +#define R8A7791_DMA_SCIF4_RX (0xFC) +#define R8A7791_DMA_SCIF5_TX (0xFD) +#define R8A7791_DMA_SCIF5_RX (0xFE) + +#define R8A7791_DMA_MSIOF0_TX (0x51) +#define R8A7791_DMA_MSIOF0_RX (0x52) +#define R8A7791_DMA_MSIOF1_TX (0x55) +#define R8A7791_DMA_MSIOF1_RX (0x56) +#define R8A7791_DMA_MSIOF2_TX (0x41) +#define R8A7791_DMA_MSIOF2_RX (0x42) + +#define R8A7791_DMA_QSPI_TX (0x17) +#define R8A7791_DMA_QSPI_RX (0x18) + +#define R8A7791_DMA_SIM_TX (0xA1) +#define R8A7791_DMA_SIM_RX (0xA2) + +#define R8A7791_DMA_IIC0_TX (0x61) +#define R8A7791_DMA_IIC0_RX (0x62) +#define R8A7791_DMA_IIC1_TX (0x65) +#define R8A7791_DMA_IIC1_RX (0x66) +#define R8A7791_DMA_IICDVFS_TX (0x77) +#define R8A7791_DMA_IICDVFS_RX (0x78) + +#define R8A7791_DMA_SDHI0_TX (0xCD) +#define R8A7791_DMA_SDHI0_RX (0xCE) +#define R8A7791_DMA_SDHI2_TX (0xC1) +#define R8A7791_DMA_SDHI2_RX (0xC2) +#define R8A7791_DMA_SDHI2C2_TX (0xC5) +#define R8A7791_DMA_SDHI2C2_RX (0xC6) +#define R8A7791_DMA_SDHI3_TX (0xD3) +#define R8A7791_DMA_SDHI3_RX (0xD4) +#define R8A7791_DMA_SDHI3C2_TX (0xDF) +#define R8A7791_DMA_SDHI3C2_RX (0xDE) + +#define R8A7791_DMA_TPU0 (0xF1) +#define R8A7791_DMA_TSIF0 (0xEA) +#define R8A7791_DMA_TSIF1 (0xF0) + +#define R8A7791_DMA_AXISTATR (0xA6) +#define R8A7791_DMA_AXISTATS0 (0xAC) +#define R8A7791_DMA_AXISTATS1 (0xAA) +#define R8A7791_DMA_AXISTATS2 (0xA8) +#define R8A7791_DMA_AXISTATS3C (0xA4) + +#define R8A7791_DMA_MMCIF0_TX (0xD1) +#define R8A7791_DMA_MMCIF0_RX (0xD2) + +#define R8A7791_DMA_AXSTM (0xAE) + + +/* Misc */
include/dt-bindings/dma/r8a7791-dma.h line 109
Quoted 10 lines
include/dt-bindings/dma/r8a7791-dma.h new file +10
-0+ +// FIXME +#define CHCR_RX_8BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_8BIT) +#define CHCR_TX_8BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_8BIT) +#define CHCR_RX_16BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_16BIT) +#define CHCR_TX_16BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_16BIT) +#define CHCR_RX_32BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_32BIT) +#define CHCR_TX_32BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_32BIT) +#define CHCR_RX_256BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_256BIT) +#define CHCR_TX_256BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_256BIT)
I am pretty sure for round-2 we can remove these in favour of a table in the driver. The only device that has a non-standard setting is the SDHI and that will support 32bit and 256bit transfers.
Signature · 2 lines
Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius
PATCH v2 4/7 ARM: shmobile: r8a7791: Add SYS-DMAC channel definitions for bindings
Hi Ben,
Quoted 5 lines · Ben Dooks
Quoted 5 lines
include/dt-bindings/dma/r8a7791-dma.h new file +5
-0+// FIXME +#define CHCR_RX_8BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_8BIT) +#define CHCR_TX_8BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_8BIT) +#define CHCR_RX_16BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_16BIT) +#define CHCR_TX_16BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_16BIT)
Quoted 8 lines
include/dt-bindings/dma/r8a7791-dma.h line 109
Quoted 4 lines
include/dt-bindings/dma/r8a7791-dma.h new file +4
-0+#define CHCR_RX_32BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_32BIT) +#define CHCR_TX_32BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_32BIT) +#define CHCR_RX_256BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_256BIT) +#define CHCR_TX_256BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_256BIT)I am pretty sure for round-2 we can remove these in favour of a table in the driver. The only device that has a non-standard setting is the SDHI and that will support 32bit and 256bit transfers.
Thanks, I'm eagerly awaiting your next version...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH v2 4/7 ARM: shmobile: r8a7791: Add SYS-DMAC channel definitions for bindings
Quoted 15 lines · On Tuesday 03 June 2014 09:53:17 Geert Uytterhoeven wrote:
Quoted 5 lines · Ben Dooks
Quoted 5 lines
include/dt-bindings/dma/r8a7791-dma.h new file +5
-0+// FIXME +#define CHCR_RX_8BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_8BIT) +#define CHCR_TX_8BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_8BIT) +#define CHCR_RX_16BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_16BIT) +#define CHCR_TX_16BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_16BIT)Quoted 8 lines
include/dt-bindings/dma/r8a7791-dma.h line 109
Quoted 4 lines
include/dt-bindings/dma/r8a7791-dma.h new file +4
-0+#define CHCR_RX_32BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_32BIT) +#define CHCR_TX_32BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_32BIT) +#define CHCR_RX_256BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_256BIT) +#define CHCR_TX_256BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_256BIT)I am pretty sure for round-2 we can remove these in favour of a table in the driver. The only device that has a non-standard setting is the SDHI and that will support 32bit and 256bit transfers.
Quoted 1 line
Thanks, I'm eagerly awaiting your next version...
Speaking of that, Ben, do you have a git tree with your latest patches ?
Signature · 3 lines
Regards, Laurent Pinchart
PATCH v2 4/7 ARM: shmobile: r8a7791: Add SYS-DMAC channel definitions for bindings
Quoted 16 lines · Laurent Pinchart
Quoted 15 lines · On Tuesday 03 June 2014 09:53:17 Geert Uytterhoeven wrote:
Quoted 13 lines · Ben Dooks
include/dt-bindings/dma/r8a7791-dma.h line 109
Quoted 9 lines
include/dt-bindings/dma/r8a7791-dma.h new file +9
-0+// FIXME +#define CHCR_RX_8BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_8BIT) +#define CHCR_TX_8BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_8BIT) +#define CHCR_RX_16BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_16BIT) +#define CHCR_TX_16BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_16BIT) +#define CHCR_RX_32BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_32BIT) +#define CHCR_TX_32BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_32BIT) +#define CHCR_RX_256BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_256BIT) +#define CHCR_TX_256BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_256BIT)I am pretty sure for round-2 we can remove these in favour of a table in the driver. The only device that has a non-standard setting is the SDHI and that will support 32bit and 256bit transfers.
Quoted 3 lines
Quoted 1 line
Thanks, I'm eagerly awaiting your next version...
Speaking of that, Ben, do you have a git tree with your latest patches ?
Not yet, as currently working on sorting out the soc_camera before moving back to the DMA. I have a plan, just not had the time to sort it out.
Signature · 2 lines
Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius
PATCH v2 4/7 ARM: shmobile: r8a7791: Add SYS-DMAC channel definitions for bindings
Hi Ben,
Quoted 17 lines · On Wednesday 04 June 2014 12:45:19 Ben Dooks wrote:
Quoted 16 lines · Laurent Pinchart
Quoted 15 lines · On Tuesday 03 June 2014 09:53:17 Geert Uytterhoeven wrote:
Quoted 13 lines · Ben Dooks
include/dt-bindings/dma/r8a7791-dma.h line 109
Quoted 9 lines
include/dt-bindings/dma/r8a7791-dma.h new file +9
-0+// FIXME +#define CHCR_RX_8BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_8BIT) +#define CHCR_TX_8BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_8BIT) +#define CHCR_RX_16BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_16BIT) +#define CHCR_TX_16BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_16BIT) +#define CHCR_RX_32BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_32BIT) +#define CHCR_TX_32BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_32BIT) +#define CHCR_RX_256BIT SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_256BIT) +#define CHCR_TX_256BIT SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_256BIT)I am pretty sure for round-2 we can remove these in favour of a table in the driver. The only device that has a non-standard setting is the SDHI and that will support 32bit and 256bit transfers.
Quoted 7 lines
Quoted 3 lines
Quoted 1 line
Thanks, I'm eagerly awaiting your next version...
Speaking of that, Ben, do you have a git tree with your latest patches ?
Not yet, as currently working on sorting out the
soc_camerabefore moving back to the DMA. I have a plan, just not had the time to sort it out.
I need to start implementing LPAE support for the DMAC using descriptors, and I have to decide whether I'll go for a new driver of fix the existing one(s). Having access to your code, even if it's work in progress, would be helpful, otherwise there will be a high chance of conflicts.
Signature · 3 lines
Regards, Laurent Pinchart
PATCH v2 4/7 ARM: shmobile: r8a7791: Add PCIEC clock device tree node
In reply to Geert UytterhoevenThis patch adds the device tree clock node for the PCIe Controller
---
v2:
- Changed PCIe controller names,etc from pcie to pciec
- Corrected MTSP bit ordering
arch/arm/boot/dts/r8a7791.dtsi | 7 ++++--- include/dt-bindings/clock/r8a7791-clock.h | 1 + 2 files changed, 5 insertions(+), 3 deletions(-)
arch/arm/boot/dts/r8a7791.dtsi +4 -3
@@ -772,15 +772,16 @@ compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, - <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; + <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 - R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 + R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 + R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 >; clock-output-names "tpu0", "sdhi2", "sdhi1", "sdhi0", - "mmcif0", "i2c7", "i2c8", "ssusb", "cmt1"; + "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
include/dt-bindings/clock/r8a7791-clock.h +1 -0
@@ -53,6 +53,7 @@#define R8A7791_CLK_SDHI0 14#define R8A7791_CLK_MMCIF0 15#define R8A7791_CLK_IIC0 18 +#define R8A7791_CLK_PCIEC 19#define R8A7791_CLK_IIC1 23#define R8A7791_CLK_SSUSB 28#define R8A7791_CLK_CMT1 29
Signature · 1 line
2.0.0
Re: [PATCH v2 4/7] ARM: shmobile: r8a7791: Add PCIEC clock device tree node
In reply to Geert UytterhoevenHi Phil,
Thank you for the patch.
Quoted 3 lines · On Wednesday 11 June 2014 12:05:50 Phil Edworthy wrote:
This patch adds the device tree clock node for the PCIe Controller
Signed-off-by Phil Edworthy <[email protected]>
Quoted 14 lines
---
v2:
- Changed PCIe controller names,etc from pcie to pciec
- Corrected MTSP bit orderingarch/arm/boot/dts/r8a7791.dtsi | 7 ++++--- include/dt-bindings/clock/r8a7791-clock.h | 1 + 2 files changed, 5 insertions(+), 3 deletions(-)arch/arm/boot/dts/r8a7791.dtsi +0
-0
arch/arm/boot/dts/r8a7791.dtsi line 772
Quoted 1 line
arch/arm/boot/dts/r8a7791.dtsi +0
-0@@ -772,15 +772,16 @@ compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-
clocks";
arch/arm/boot/dts/r8a7791.dtsi line 775
Quoted 3 lines
arch/arm/boot/dts/r8a7791.dtsi +0
-0reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, - <&mmc0_clk>, <&hp_clk>, <&hp_clk>,
<&mp_clk>,
arch/arm/boot/dts/r8a7791.dtsi line 777
Quoted 2 lines
arch/arm/boot/dts/r8a7791.dtsi +1
-0<&rclk_clk>; + <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
<&rclk_clk>;
arch/arm/boot/dts/r8a7791.dtsi line 780
Quoted 3 lines
arch/arm/boot/dts/r8a7791.dtsi +0
-0#clock-cells = <1>; renesas,clock-indices = < R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1
R8A7791_CLK_SDHI0
arch/arm/boot/dts/r8a7791.dtsi line 780
Quoted 1 line
arch/arm/boot/dts/r8a7791.dtsi +0
-1- R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1
R8A7791_CLK_SSUSB
Quoted 1 line
R8A7791_CLK_CMT1+R8A7791_CLK_MMCIF0R8A7791_CLK_IIC0
R8A7791_CLK_PCIEC
arch/arm/boot/dts/r8a7791.dtsi
Quoted 10 lines
R8A7791_CLK_IIC1+R8A7791_CLK_SSUSBR8A7791_CLK_CMT1arch/arm/boot/dts/r8a7791.dtsi +1
-1>; clock-output-names > "tpu0", "sdhi2", "sdhi1", "sdhi0", - "mmcif0", "i2c7", "i2c8", "ssusb", "cmt1"; + "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-
clocks";
Quoted 12 lines
(quoted diff) +0
-0
b/include/dt-bindings/clock/r8a7791-clock.hindex b050d18..1101e64 100644include/dt-bindings/clock/r8a7791-clock.h +1
-0@@ -53,6 +53,7 @@#define R8A7791_CLK_SDHI0 14#define R8A7791_CLK_MMCIF0 15#define R8A7791_CLK_IIC0 18 +#define R8A7791_CLK_PCIEC 19#define R8A7791_CLK_IIC1 23#define R8A7791_CLK_SSUSB 28#define R8A7791_CLK_CMT1 29
Signature · 3 lines
Regards, Laurent Pinchart
PATCH v2 5/7 ARM: shmobile: r8a7791 dtsi: Add SYS-DMAC0 and SYS-DMAC1 nodes
In reply to Geert UytterhoevenAdd nodes for the SYS-DMA controllers, SYS-DMAC0 and SYS-DMAC1. These both share the same device sources, so are wrapped in the shdma-mux node to allow both to be used.
Cfr. the r8a7790 version by Ben Dooks.
---
v2:
- No changes
arch/arm/boot/dts/r8a7791.dtsi | 69 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+)
arch/arm/boot/dts/r8a7791.dtsi +69 -0
@@ -11,6 +11,7 @@ */ #include <dt-bindings/clock/r8a7791-clock.h> +#include <dt-bindings/dma/r8a7791-dma.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h>
@@ -55,6 +56,74 @@ }; }; + dma0: dma-mux at 0 { + compatible = "renesas,shdma-mux"; + #dma-cells = <2>; + dma-channels = <30>; + dma-requests = <256>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sysdma0: dma-controller at e6700020 { + compatible = "renesas,shdma-r8a7791"; + reg = <0 0xe6700020 0 0xffc0>; + clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>; + dma-channels = <15>; + interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH>, /* error */ + <0 200 IRQ_TYPE_LEVEL_HIGH>, /* ch0 */ + <0 201 IRQ_TYPE_LEVEL_HIGH>, + <0 202 IRQ_TYPE_LEVEL_HIGH>, + <0 203 IRQ_TYPE_LEVEL_HIGH>, + <0 204 IRQ_TYPE_LEVEL_HIGH>, + <0 205 IRQ_TYPE_LEVEL_HIGH>, + <0 206 IRQ_TYPE_LEVEL_HIGH>, + <0 207 IRQ_TYPE_LEVEL_HIGH>, + <0 208 IRQ_TYPE_LEVEL_HIGH>, + <0 209 IRQ_TYPE_LEVEL_HIGH>, + <0 210 IRQ_TYPE_LEVEL_HIGH>, + <0 211 IRQ_TYPE_LEVEL_HIGH>, + <0 212 IRQ_TYPE_LEVEL_HIGH>, + <0 213 IRQ_TYPE_LEVEL_HIGH>, + <0 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + status = "disabled"; + }; + + sysdma1: dma-controller at e6720020 { + compatible = "renesas,shdma-r8a7791"; + reg = <0 0xe6720020 0 0xffc0>; + clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>; + dma-channels = <15>; + interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>, + <0 216 IRQ_TYPE_LEVEL_HIGH>, + <0 217 IRQ_TYPE_LEVEL_HIGH>, + <0 218 IRQ_TYPE_LEVEL_HIGH>, + <0 219 IRQ_TYPE_LEVEL_HIGH>, + <0 308 IRQ_TYPE_LEVEL_HIGH>, + <0 309 IRQ_TYPE_LEVEL_HIGH>, + <0 310 IRQ_TYPE_LEVEL_HIGH>, + <0 311 IRQ_TYPE_LEVEL_HIGH>, + <0 312 IRQ_TYPE_LEVEL_HIGH>, + <0 313 IRQ_TYPE_LEVEL_HIGH>, + <0 314 IRQ_TYPE_LEVEL_HIGH>, + <0 315 IRQ_TYPE_LEVEL_HIGH>, + <0 316 IRQ_TYPE_LEVEL_HIGH>, + <0 317 IRQ_TYPE_LEVEL_HIGH>, + <0 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + status = "disabled"; + }; + }; + gic: interrupt-controller at f1001000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>;
Signature · 1 line
1.9.1
PATCH v2 5/7 ARM: shmobile: r8a7791 dtsi: Add SYS-DMAC0 and SYS-DMAC1 nodes
Hi Geert,
Thank you for the patch.
Quoted 32 lines · On Monday 02 June 2014 15:42:09 Geert Uytterhoeven wrote:
Add nodes for the SYS-DMA controllers, SYS-DMAC0 and SYS-DMAC1. These both share the same device sources, so are wrapped in the shdma-mux node to allow both to be used.
Cfr. the r8a7790 version by Ben Dooks.
Signed-off-by Geert Uytterhoeven <[email protected]>---
v2:
- No changesarch/arm/boot/dts/r8a7791.dtsi | 69 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+)arch/arm/boot/dts/r8a7791.dtsi +3
-0@@ -11,6 +11,7 @@ */ #include <dt-bindings/clock/r8a7791-clock.h> +#include <dt-bindings/dma/r8a7791-dma.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h>@@ -55,6 +56,74 @@ }; }; + dma0: dma-mux at 0 { + compatible = "renesas,shdma-mux";
arch/arm/boot/dts/r8a7791.dtsi line 70
Quoted 10 lines
arch/arm/boot/dts/r8a7791.dtsi +10
-0+ #dma-cells = <2>; + dma-channels = <30>; + dma-requests = <256>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sysdma0: dma-controller at e6700020 { + compatible = "renesas,shdma-r8a7791"; + reg = <0 0xe6700020 0 0xffc0>;
Even though the registered defined in the datasheet start at 0xe6700020, the documentation clearly states that "The base address of registers for the lower-numbered channels (0 to 14) is H'E670 0000". I'm also wondering where the size comes from, if you want to span the 0xe6700000 to 0xe670ffff range, the size should be 0xffe0, not 0xffc0.
Interrupts and clocks look fine to me.
Quoted 59 lines
arch/arm/boot/dts/r8a7791.dtsi +56
-0+ clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>; + dma-channels = <15>; + interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH>, /* error */ + <0 200 IRQ_TYPE_LEVEL_HIGH>, /* ch0 */ + <0 201 IRQ_TYPE_LEVEL_HIGH>, + <0 202 IRQ_TYPE_LEVEL_HIGH>, + <0 203 IRQ_TYPE_LEVEL_HIGH>, + <0 204 IRQ_TYPE_LEVEL_HIGH>, + <0 205 IRQ_TYPE_LEVEL_HIGH>, + <0 206 IRQ_TYPE_LEVEL_HIGH>, + <0 207 IRQ_TYPE_LEVEL_HIGH>, + <0 208 IRQ_TYPE_LEVEL_HIGH>, + <0 209 IRQ_TYPE_LEVEL_HIGH>, + <0 210 IRQ_TYPE_LEVEL_HIGH>, + <0 211 IRQ_TYPE_LEVEL_HIGH>, + <0 212 IRQ_TYPE_LEVEL_HIGH>, + <0 213 IRQ_TYPE_LEVEL_HIGH>, + <0 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + status = "disabled"; + }; + + sysdma1: dma-controller at e6720020 { + compatible = "renesas,shdma-r8a7791"; + reg = <0 0xe6720020 0 0xffc0>; + clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>; + dma-channels = <15>; + interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>, + <0 216 IRQ_TYPE_LEVEL_HIGH>, + <0 217 IRQ_TYPE_LEVEL_HIGH>, + <0 218 IRQ_TYPE_LEVEL_HIGH>, + <0 219 IRQ_TYPE_LEVEL_HIGH>, + <0 308 IRQ_TYPE_LEVEL_HIGH>, + <0 309 IRQ_TYPE_LEVEL_HIGH>, + <0 310 IRQ_TYPE_LEVEL_HIGH>, + <0 311 IRQ_TYPE_LEVEL_HIGH>, + <0 312 IRQ_TYPE_LEVEL_HIGH>, + <0 313 IRQ_TYPE_LEVEL_HIGH>, + <0 314 IRQ_TYPE_LEVEL_HIGH>, + <0 315 IRQ_TYPE_LEVEL_HIGH>, + <0 316 IRQ_TYPE_LEVEL_HIGH>, + <0 317 IRQ_TYPE_LEVEL_HIGH>, + <0 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + status = "disabled"; + }; + }; + gic: interrupt-controller at f1001000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>;
Signature · 3 lines
Regards, Laurent Pinchart
PATCH v2 5/7 ARM: shmobile: r8a7791 dtsi: Add SYS-DMAC0 and SYS-DMAC1 nodes
Hi Laurent
Quoted 8 lines
Quoted 8 lines
Add nodes for the SYS-DMA controllers, SYS-DMAC0 and SYS-DMAC1. These both share the same device sources, so are wrapped in the shdma-mux node to allow both to be used.
Cfr. the r8a7790 version by Ben Dooks.
Signed-off-by Geert Uytterhoeven <[email protected]>---
(snip)
Quoted 9 lines
arch/arm/boot/dts/r8a7791.dtsi line 70
Quoted 3 lines
arch/arm/boot/dts/r8a7791.dtsi +3
-0+ sysdma0: dma-controller at e6700020 { + compatible = "renesas,shdma-r8a7791"; + reg = <0 0xe6700020 0 0xffc0>;Even though the registered defined in the datasheet start at
0xe6700020, the documentation clearly states that "The base address of registers for the lower-numbered channels (0 to 14) is H'E670 0000". I'm also wondering where the size comes from, if you want to span the0xe6700000to0xe670ffffrange, the size should be0xffe0, not0xffc0.
Unfortunately, this mapping (form 0x20) is required from driver for historical reasons.
So, driver setting needs to care about it.
Please check DMA_CHANNEL macro for each setup-xxx.c
# but, it works without care about it (?)
# becase there are mirror register there (?), I'm not sure detail
Best regards
---
Kuninori Morimoto
PATCH v2 5/7 ARM: shmobile: r8a7791 dtsi: Add SYS-DMAC0 and SYS-DMAC1 nodes
Hi Morimoto-san,
Quoted 23 lines · On Wednesday 04 June 2014 17:17:53 Kuninori Morimoto wrote:
Hi Laurent
Quoted 8 lines
Quoted 8 lines
Add nodes for the SYS-DMA controllers, SYS-DMAC0 and SYS-DMAC1. These both share the same device sources, so are wrapped in the shdma-mux node to allow both to be used.
Cfr. the r8a7790 version by Ben Dooks.
Signed-off-by Geert Uytterhoeven <[email protected]>---
(snip)
Quoted 9 lines
arch/arm/boot/dts/r8a7791.dtsi line 70
Quoted 3 lines
arch/arm/boot/dts/r8a7791.dtsi +3
-0+ sysdma0: dma-controller at e6700020 { + compatible = "renesas,shdma-r8a7791"; + reg = <0 0xe6700020 0 0xffc0>;Even though the registered defined in the datasheet start at
0xe6700020, the documentation clearly states that "The base address of registers for the lower-numbered channels (0 to 14) is H'E670 0000". I'm also wondering where the size comes from, if you want to span the0xe6700000to0xe670ffffrange, the size should be0xffe0, not0xffc0.
Quoted 4 lines
Unfortunately, this mapping (form
0x20) is required from driver for historical reasons.
So, driver setting needs to care about it.
Please checkDMA_CHANNELmacro for eachsetup-xxx.c
Right, but that doesn't mean we shouldn't fix that while we still can :-) For the r8a73a4 we're probably stuck (I won't reiterate here my view of considering DT bindings as stable when it's clear they haven't gone through proper review), but before we add support for new SoCs I'd like to see to problems being fixed.
Quoted 2 lines
# but, it works without care about it (?)
# becase there are mirror register there (?), I'm not sure detail
Signature · 3 lines
Regards, Laurent Pinchart
PATCH v2 5/7 ARM: shmobile: r8a7791 dtsi: Add SYS-DMAC0 and SYS-DMAC1 nodes
In reply to Laurent PinchartQuoted 45 lines · Laurent Pinchart
Hi Geert,
Thank you for the patch.
Quoted 40 lines · On Monday 02 June 2014 15:42:09 Geert Uytterhoeven wrote:
Add nodes for the SYS-DMA controllers, SYS-DMAC0 and SYS-DMAC1. These both share the same device sources, so are wrapped in the shdma-mux node to allow both to be used.
Cfr. the r8a7790 version by Ben Dooks.
Signed-off-by Geert Uytterhoeven <[email protected]>---
v2:
- No changesarch/arm/boot/dts/r8a7791.dtsi | 69 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+)arch/arm/boot/dts/r8a7791.dtsi +11
-0@@ -11,6 +11,7 @@ */ #include <dt-bindings/clock/r8a7791-clock.h> +#include <dt-bindings/dma/r8a7791-dma.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h>@@ -55,6 +56,74 @@ }; }; + dma0: dma-mux at 0 { + compatible = "renesas,shdma-mux"; + #dma-cells = <2>; + dma-channels = <30>; + dma-requests = <256>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sysdma0: dma-controller at e6700020 {
Quoted 8 lines
arch/arm/boot/dts/r8a7791.dtsi line 70
Quoted 2 lines
arch/arm/boot/dts/r8a7791.dtsi +2
-0+ compatible = "renesas,shdma-r8a7791"; + reg = <0 0xe6700020 0 0xffc0>;Even though the registered defined in the datasheet start at
0xe6700020, the documentation clearly states that "The base address of registers for the lower-numbered channels (0 to 14) is H'E670 0000". I'm also wondering where the size comes from, if you want to span the0xe6700000to0xe670ffffrange, the size should be0xffe0, not0xffc0.
There seems to be no registers below the 0x20 point and therefore all current implementations assume that the first register is the point for the start. 0xffc0 is wrong, should be 0xffe0.
Signature · 2 lines
Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius
PATCH v2 6/7 ARM: shmobile: koelsch dts: Enable sysdma0 and sysdma1
In reply to Geert Uytterhoeven---
v2:
- No changes
arch/arm/boot/dts/r8a7791-koelsch.dts | 8 ++++++++ 1 file changed, 8 insertions(+)
arch/arm/boot/dts/r8a7791-koelsch.dts +8 -0
@@ -408,3 +408,11 @@ spi-cpha; }; }; + +&sysdma0 { + status = "okay"; +}; + +&sysdma1 { + status = "okay"; +};
Signature · 1 line
1.9.1
PATCH v2 7/7 ARM: shmobile: r8a7791 dtsi: Enable DMA for QSPI
In reply to Geert UytterhoevenAdd a DMA property to the QSPI node
---
v2:
- QSPI needs to use 8-bit accesses for DMA, not 32-bit,
- Reorder: TX first, RX second.
arch/arm/boot/dts/r8a7791.dtsi | 3 +++ 1 file changed, 3 insertions(+)
arch/arm/boot/dts/r8a7791.dtsi +3 -0
@@ -917,6 +917,9 @@ reg = <0 0xe6b10000 0 0x2c>; interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; + dmas = <&dma0 R8A7791_DMA_QSPI_TX CHCR_TX_8BIT>, + <&dma0 R8A7791_DMA_QSPI_RX CHCR_RX_8BIT>; + dma-names = "tx", "rx"; num-cs = <1>; #address-cells = <1>; #size-cells = <0>;
Signature · 1 line
1.9.1
PATCH v2 7/7 ARM: shmobile: r8a7791 dtsi: Enable DMA for QSPI
Quoted 16 lines · Geert Uytterhoeven
Add a DMA property to the QSPI node
Signed-off-by Geert Uytterhoeven <[email protected]>---
v2:
- QSPI needs to use 8-bit accesses for DMA, not 32-bit,
- Reorder: TX first, RX second.arch/arm/boot/dts/r8a7791.dtsi | 3 +++ 1 file changed, 3 insertions(+)arch/arm/boot/dts/r8a7791.dtsi +0
-0
arch/arm/boot/dts/r8a7791.dtsi line 922
Quoted 6 lines
arch/arm/boot/dts/r8a7791.dtsi +3
-0@@ -917,6 +917,9 @@ reg = <0 0xe6b10000 0 0x2c>; interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; + dmas = <&dma0 R8A7791_DMA_QSPI_TX CHCR_TX_8BIT>, + <&dma0 R8A7791_DMA_QSPI_RX CHCR_RX_8BIT>; + dma-names = "tx", "rx";
I am hopeful that we can remove the CHCR settings, each driver should configure the width when configuring the slave. V2 of the patches will reflect this.
Signature · 2 lines
Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius
v2 cover ARM: shmobile: koelsch reference: Enable DMA for QSPI
In reply to Geert UytterhoevenQuoted 36 lines · Geert Uytterhoeven
This patch series enables DMA support for QSPI on r8a7791/koelsch reference. It's independent from the series "ARM: shmobile: koelsch
legacy: Enable DMA for QSPI", but it depends on the SHDMA work for r8a7790 by Ben Dooks (cfr. "[PATCH v2 0/9] Updates Renesas OF-DMA code").Changes Compared to previous submission ("[PATCH/RFC 0/7] ARM: shmobile:
r8a7791: Add preliminary DMA support"):
- "[6/7] ARM: shmobile: r8a7791 dtsi: Enable DMA for MSIOF" was dropped,
- 2/7 was added,
- 7/7 was changed (see changelog in individual patch).This was tested on r8a7791/koelsch.
Performance figures for reading from a QSPI FLASH driven at 24.375 MHz are:
- Single: 1.1 Mbps PIO, 23 Mbps DMA
- Dual : 12.7 Mbps PIO, 48 Mbps DMA
- Quad : 13 Mbps PIO, 70 Mbps DMAThanks for your comments!
[1/7] DMA: shdma: Add r8a7791 support
[2/7] DMA: shdma: Spelling s/controll/control/
[3/7] ARM: shmobile: r8a7791 dtsi: add SYS-DMAC clocks
[4/7] ARM: shmobile: r8a7791: Add SYS-DMAC channel definitions for bindings [5/7] ARM: shmobile: r8a7791 dtsi: Add SYS-DMAC0 and SYS-DMAC1 nodes [6/7] ARM: shmobile: koelsch dts: Enable sysdma0 and sysdma1 [7/7] ARM: shmobile: r8a7791 dtsi: Enable DMA for QSPIDocumentation/devicetree/bindings/dma/shdma.txt | 7 +- arch/arm/boot/dts/r8a7791-koelsch.dts | 8 ++ arch/arm/boot/dts/r8a7791.dtsi | 79 ++++++++++++++++- drivers/dma/sh/shdmac.c | 1 + include/dt-bindings/dma/r8a7791-dma.h | 111 ++++++++++++++++++++++++ 5 files changed, 201 insertions(+), 5 deletions(-) create mode 100644 include/dt-bindings/dma/r8a7791-dma.h
Quoted 1 line
Gr{oetje,eeting}s,
Hi, thanks for testing against the current DMA series, I will try and get a new series out for you in the next few days with the changes to use 1 parameter phandles instead of 2 parameter ones.
Signature · 2 lines
Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius
v2 cover ARM: shmobile: koelsch reference: Enable DMA for QSPI
In reply to Geert UytterhoevenHi Geert,
Thanks for the patches.
I think this patch series should be divided into 2 parts, one for DMA in general and one for DMA supporting QSPI.
How do you think about it ?
Best regards,
KHIEM Nguyen
Quoted 50 lines · Geert Uytterhoeven
This patch series enables DMA support for QSPI on r8a7791/koelsch reference. It's independent from the series "ARM: shmobile: koelsch
legacy: Enable DMA for QSPI", but it depends on the SHDMA work for r8a7790 by Ben Dooks (cfr. "[PATCH v2 0/9] Updates Renesas OF-DMA code").Changes Compared to previous submission ("[PATCH/RFC 0/7] ARM: shmobile:
r8a7791: Add preliminary DMA support"):
- "[6/7] ARM: shmobile: r8a7791 dtsi: Enable DMA for MSIOF" was dropped,
- 2/7 was added,
- 7/7 was changed (see changelog in individual patch).This was tested on r8a7791/koelsch.
Performance figures for reading from a QSPI FLASH driven at 24.375 MHz are:
- Single: 1.1 Mbps PIO, 23 Mbps DMA
- Dual : 12.7 Mbps PIO, 48 Mbps DMA
- Quad : 13 Mbps PIO, 70 Mbps DMAThanks for your comments!
[1/7] DMA: shdma: Add r8a7791 support
[2/7] DMA: shdma: Spelling s/controll/control/
[3/7] ARM: shmobile: r8a7791 dtsi: add SYS-DMAC clocks
[4/7] ARM: shmobile: r8a7791: Add SYS-DMAC channel definitions for bindings [5/7] ARM: shmobile: r8a7791 dtsi: Add SYS-DMAC0 and SYS-DMAC1 nodes [6/7] ARM: shmobile: koelsch dts: Enable sysdma0 and sysdma1 [7/7] ARM: shmobile: r8a7791 dtsi: Enable DMA for QSPIDocumentation/devicetree/bindings/dma/shdma.txt | 7 +- arch/arm/boot/dts/r8a7791-koelsch.dts | 8 ++ arch/arm/boot/dts/r8a7791.dtsi | 79 ++++++++++++++++- drivers/dma/sh/shdmac.c | 1 + include/dt-bindings/dma/r8a7791-dma.h | 111 ++++++++++++++++++++++++ 5 files changed, 201 insertions(+), 5 deletions(-)create mode 100644
include/dt-bindings/dma/r8a7791-dma.hGr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.orgIn personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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v2 cover ARM: shmobile: koelsch reference: Enable DMA for QSPI
Quoted 4 lines · Khiem Nguyen
I think this patch series should be divided into 2 parts, one for DMA in general and one for DMA supporting QSPI.
How do you think about it ?
I don't think it's worth splitting off just the last patch into a separate series.
This is a series, not a single patch. The applyer can always drop some patches.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
v2 cover ARM: shmobile: koelsch reference: Enable DMA for QSPI
Quoted 5 lines · Geert Uytterhoeven
Quoted 3 lines · Khiem Nguyen
I think this patch series should be divided into 2 parts, one for DMA in general and one for DMA supporting QSPI.
Quoted 7 lines
Quoted 1 line
How do you think about it ?
I don't think it's worth splitting off just the last patch into a separate series.
This is a series, not a single patch. The applyer can always drop some patches.
FWIW, that seems reasonable to me.
v2 cover ARM: shmobile: koelsch reference: Enable DMA for QSPI
Hi Geert, Simon,
Quoted 6 lines · Simon Horman
Quoted 5 lines · Geert Uytterhoeven
Quoted 3 lines · Khiem Nguyen
I think this patch series should be divided into 2 parts, one for DMA in general and one for DMA supporting QSPI.
Quoted 7 lines
Quoted 6 lines
Quoted 1 line
How do you think about it ?
I don't think it's worth splitting off just the last patch into a separate series.
This is a series, not a single patch. The applyer can always drop some patches.
FWIW, that seems reasonable to me.
Thanks for your explanation.
I got it.
Sorry for the noise.
Best regards,
KHIEM Nguyen