KVM: PPC: Book3S PR: Fix ABIv2 issues
Subsystems (3)
PATCH 1/4 KVM: PPC: Book3S PR: Fix ABIv2 issues
binutils knows that a branch to a function descriptor is actually a branch to the function text. By removing the explicit branch to dot symbols, we maintain both ABIv1 and ABIv2 compatibility.
---
arch/powerpc/kvm/book3s_interrupts.S +4 -6
@@ -25,11 +25,9 @@ #include <asm/exception-64s.h> #if defined(CONFIG_PPC_BOOK3S_64) -#define FUNC(name) GLUE(.,name) #define GET_SHADOW_VCPU(reg) addi reg, r13, PACA_SVCPU #elif defined(CONFIG_PPC_BOOK3S_32) -#define FUNC(name) name #define GET_SHADOW_VCPU(reg) lwz reg, (THREAD + THREAD_KVM_SVCPU)(r2) #endif /* CONFIG_PPC_BOOK3S_XX */
@@ -93,7 +91,7 @@ kvm_start_entry: kvm_start_lightweight: /* Copy registers into shadow vcpu so we can access them in real mode */ GET_SHADOW_VCPU(r3) - bl FUNC(kvmppc_copy_to_svcpu) + bl kvmppc_copy_to_svcpu nop REST_GPR(4, r1)
@@ -131,7 +129,7 @@ after_sprg3_load: PPC_LL r4, VCPU_SHADOW_MSR(r4) /* get shadow_msr */ /* Jump to segment patching handler and into our guest */ - bl FUNC(kvmppc_entry_trampoline) + bl kvmppc_entry_trampoline nop /*
@@ -164,7 +162,7 @@ after_sprg3_load: /* On 64-bit, interrupts are still off at this point */ GET_SHADOW_VCPU(r4) - bl FUNC(kvmppc_copy_from_svcpu) + bl kvmppc_copy_from_svcpu nop #ifdef CONFIG_PPC_BOOK3S_64
@@ -203,7 +201,7 @@ after_sprg3_load: /* Restore r3 (kvm_run) and r4 (vcpu) */ REST_2GPRS(3, r1) - bl FUNC(kvmppc_handle_exit_pr) + bl kvmppc_handle_exit_pr /* If RESUME_GUEST, get back in the loop */ cmpwi r3, RESUME_GUEST
arch/powerpc/kvm/book3s_rmhandlers.S +1 -7
@@ -34,13 +34,7 @@ * * ****************************************************************************/ -#if defined(CONFIG_PPC_BOOK3S_64) - -#define FUNC(name) GLUE(.,name) - -#elif defined(CONFIG_PPC_BOOK3S_32) - -#define FUNC(name) name +#ifdef CONFIG_PPC_BOOK3S_32 .macro INTERRUPT_TRAMPOLINE intno
PATCH 2/4 KVM: PPC: Book3S HV: Fix ABIv2 issues
binutils knows that a branch to a function descriptor is actually a branch to the function text. By removing the explicit branch to dot symbols, we maintain both ABIv1 and ABIv2 compatibility.
---
Index: b/arch/powerpc/kvm/book3s_hv_rmhandlers.S =================================--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -675,9 +675,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_TM)
mr r31, r4
addi r3, r31, VCPU_FPRS_TM
- bl .load_fp_state
+ bl load_fp_state
addi r3, r31, VCPU_VRS_TM
- bl .load_vr_state
+ bl load_vr_state
mr r4, r31
lwz r7, VCPU_VRSAVE_TM(r4)
mtspr SPRN_VRSAVE, r7
@@ -1421,9 +1421,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_TM)
/* Save FP/VSX. */
addi r3, r9, VCPU_FPRS_TM
- bl .store_fp_state
+ bl store_fp_state
addi r3, r9, VCPU_VRS_TM
- bl .store_vr_state
+ bl store_vr_state
mfspr r6, SPRN_VRSAVE
stw r6, VCPU_VRSAVE_TM(r9)
1:
@@ -2421,11 +2421,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
mtmsrd r8
isync
addi r3,r3,VCPU_FPRS
- bl .store_fp_state
+ bl store_fp_state
#ifdef CONFIG_ALTIVEC
BEGIN_FTR_SECTION
addi r3,r31,VCPU_VRS
- bl .store_vr_state
+ bl store_vr_state
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
#endif
mfspr r6,SPRN_VRSAVE
@@ -2457,11 +2457,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
mtmsrd r8
isync
addi r3,r4,VCPU_FPRS
- bl .load_fp_state
+ bl load_fp_state
#ifdef CONFIG_ALTIVEC
BEGIN_FTR_SECTION
addi r3,r31,VCPU_VRS
- bl .load_vr_state
+ bl load_vr_state
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
#endif
lwz r7,VCPU_VRSAVE(r31)
PATCH 3/4 KVM: PPC: Book3S HV: Fix ABIv2 indirect branch issue
In reply to Anton BlanchardTo establish addressability quickly, ABIv2 requires the target address of the function being called to be in r12.
---
Index: b/arch/powerpc/kvm/book3s_hv_rmhandlers.S =================================--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -1920,8 +1920,8 @@ hcall_try_real_mode:
lwax r3,r3,r4
cmpwi r3,0
beq guest_exit_cont
- add r3,r3,r4
- mtctr r3
+ add r12,r3,r4
+ mtctr r12
mr r3,r9 /* get vcpu pointer */
ld r4,VCPU_GPR(R4)(r9)
bctrl
Alexander Graf
AppliedRe: [PATCH 3/4] KVM: PPC: Book3S HV: Fix ABIv2 indirect branch issue
Quoted 4 lines · Anton Blanchard
To establish addressability quickly, ABIv2 requires the target address of the function being called to be in r12.
Signed-off-by Anton Blanchard <[email protected]>
Thanks, applied to kvm-ppc-queue.
Alex
Quoted 17 lines
---
Index:
b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
===================================================================arch/powerpc/kvm/book3s_hv_rmhandlers.S +2
-2@@ -1920,8 +1920,8 @@ hcall_try_real_mode: lwax r3,r3,r4 cmpwi r3,0 beq guest_exit_cont - add r3,r3,r4 - mtctr r3 + add r12,r3,r4 + mtctr r12 mr r3,r9 /* get vcpu pointer */ ld r4,VCPU_GPR(R4)(r9) bctrl
PATCH 4/4 KVM: PPC: Assembly functions exported to modules need _GLOBAL_TOC()
In reply to Anton BlanchardBoth kvmppc_hv_entry_trampoline and kvmppc_entry_trampoline are assembly functions that are exported to modules and also require a valid r2.
As such we need to use _GLOBAL_TOC so we provide a global entry point that establishes the TOC (r2).
---
arch/powerpc/kvm/book3s_hv_rmhandlers.S +1 -1
@@ -51,7 +51,7 @@ * * LR = return address to continue at after eventually re-enabling MMU */ -_GLOBAL(kvmppc_hv_entry_trampoline) +_GLOBAL_TOC(kvmppc_hv_entry_trampoline) mflr r0 std r0, PPC_LR_STKOFF(r1) stdu r1, -112(r1)
arch/powerpc/kvm/book3s_rmhandlers.S +1 -1
@@ -140,7 +140,7 @@ kvmppc_handler_skip_ins: * On entry, r4 contains the guest shadow MSR * MSR.EE has to be 0 when calling this function */ -_GLOBAL(kvmppc_entry_trampoline) +_GLOBAL_TOC(kvmppc_entry_trampoline) mfmsr r5 LOAD_REG_ADDR(r7, kvmppc_handler_trampoline_enter) toreal(r7)
Alexander Graf
AppliedRe: [PATCH 4/4] KVM: PPC: Assembly functions exported to modules need _GLOBAL_TOC()
Quoted 8 lines · Anton Blanchard
Both
kvmppc_hv_entry_trampolineandkvmppc_entry_trampolineare assembly functions that are exported to modules and also require a valid r2.As such we need to use
_GLOBAL_TOCso we provide a global entry point that establishes the TOC (r2).Signed-off-by Anton Blanchard <[email protected]>
Thanks, applied to kvm-ppc-queue.
I've not applied patches 1 and 2 for now, as they break BE module support.
Alex