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of: Add vendor prefix for Chips&Media, Inc.

PATCH New Philipp Zabel 5 participants 9 messages Jun 13, 2014 – Nov 14, 2014

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Device tree bindings Media (V4L/DVB) Arm i.MX and Layerscape
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Philipp Zabel

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#0 lore raw

PATCH 1/4 of: Add vendor prefix for Chips&Media, Inc.

Chips&Media is a developer of Video Codec IP cores.

Signed-off-by Philipp Zabel <[email protected]>
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/vendor-prefixes.txt +1 -0
index abc3080..a628127 100644
@@ -29,6 +29,7 @@ cavium	Cavium, Inc.
 cdns	Cadence Design Systems Inc.
 chrp	Common Hardware Reference Platform
 chunghwa	Chunghwa Picture Tubes Ltd.
+cnm	Chips&Media, Inc.
 cirrus	Cirrus Logic, Inc.
 cortina	Cortina Systems, Inc.
 crystalfontz	Crystalfontz America, Inc.
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#1 lore raw

PATCH 2/4 of: Add new compatibles for CODA bindings

This patch adds new compatibles using the new Chips&Media vendor prefix "cnm" and CODA model name as well as a Freescale specific compatible value for i.MX6DL/S.
The latter is because for some reason the i.MX6DL/S firmware provided by Freescale differs from the i.MX6Q/D version.

Signed-off-by Philipp Zabel <[email protected]>
---
 Documentation/devicetree/bindings/media/coda.txt | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)
Documentation/devicetree/bindings/media/coda.txt +6 -5
index 2865d04..f5e4d4b 100644
@@ -5,10 +5,11 @@ Coda codec IPs are present in i.MX SoCs in various versions,
 called VPU (Video Processing Unit).
 
 Required properties:
-- compatible : should be "fsl,<chip>-src" for i.MX SoCs:
-  (a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27
-  (b) "fsl,imx53-vpu" for CODA7541 present in i.MX53
-  (c) "fsl,imx6q-vpu" for CODA960 present in i.MX6q
+- compatible : should be "fsl,<chip>-src", "cnm,coda<model>" for i.MX SoCs:
+  (a) "fsl,imx27-vpu", "cnm,codadx6" for CodaDx6 present in i.MX27
+  (b) "fsl,imx53-vpu", "cnm,coda7541" for CODA7541 present in i.MX53
+  (c) "fsl,imx6q-vpu", "cnm,coda960" for CODA960 present in i.MX6Q/D
+  (d) "fsl,imx6dl-vpu", "cnm,coda960" for CODA960 present in i.MX6DL/S
 - reg: should be register base and length as documented in the
   SoC reference manual
 - interrupts : Should contain the VPU interrupt. For CODA960,

@@ -21,7 +22,7 @@ Required properties:
 Example:
 
 vpu: vpu at 63ff4000 {
-	compatible = "fsl,imx53-vpu";
+	compatible = "fsl,imx53-vpu", "cnm,coda7541";
 	reg = <0x63ff4000 0x1000>;
 	interrupts = <9>;
 	clocks = <&clks 63>, <&clks 63>;
Signature · 1 line
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#2 lore raw

PATCH 3/4 of: Add named interrupts to CODA bindings

In reply to Philipp Zabel

This patch documents named interrupt bindings for the CODA video processing units.

Signed-off-by Philipp Zabel <[email protected]>
---
 Documentation/devicetree/bindings/media/coda.txt | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/media/coda.txt +7 -2
index f5e4d4b..a44c4aa 100644
@@ -12,19 +12,24 @@ Required properties:
   (d) "fsl,imx6dl-vpu", "cnm,coda960" for CODA960 present in i.MX6DL/S
 - reg: should be register base and length as documented in the
   SoC reference manual
-- interrupts : Should contain the VPU interrupt. For CODA960,
-  a second interrupt is needed for the MJPEG unit.
+- interrupts : Should contain the VPU (BIT processor) interrupt.
+  For CODA960, a second interrupt is needed for the JPEG unit.
 - clocks : Should contain the ahb and per clocks, in the order
   determined by the clock-names property.
 - clock-names : Should be "ahb", "per"
 - iram : phandle pointing to the SRAM device node
 
+Optional properties:
+- interrupt-names: Should be "bit" for the BIT processor interrupt
+  and "jpeg" for the JPEG unit interrupt on CODA960.
+
 Example:
 
 vpu: vpu at 63ff4000 {
 	compatible = "fsl,imx53-vpu", "cnm,coda7541";
 	reg = <0x63ff4000 0x1000>;
 	interrupts = <9>;
+	interrupt-names = "bit";
 	clocks = <&clks 63>, <&clks 63>;
 	clock-names = "ahb", "per";
 	iram = <&ocram>;
Signature · 1 line
2.0.0
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#3 lore raw

PATCH 4/4 ARM: dts: imx6qdl: Enable CODA960 VPU

In reply to Philipp Zabel

This patch adds links to the on-chip SRAM and reset controller nodes and switches the interrupts. Make the BIT processor interrupt, which exists on all variants, the first one. The JPEG unit interrupt, which does not exist on i.MX27 and i.MX5 thus is an optional second interrupt.
Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to load separate firmware images for some reason.

Signed-off-by Philipp Zabel <[email protected]>
---
 arch/arm/boot/dts/imx6dl.dtsi  |  4 ++++
 arch/arm/boot/dts/imx6q.dtsi   |  4 ++++
 arch/arm/boot/dts/imx6qdl.dtsi | 10 ++++++++--
 3 files changed, 16 insertions(+), 2 deletions(-)
arch/arm/boot/dts/imx6dl.dtsi +4 -0
index 5c5f574..fbbdfca 100644
@@ -110,3 +110,7 @@
 		      "di0_sel", "di1_sel",
 		      "di0", "di1";
 };
+
+&vpu {
+	compatible = "fsl,imx6dl-vpu", "cnm,coda960";
+};
arch/arm/boot/dts/imx6q.dtsi +4 -0
index addd3f8..2c1dbf8 100644
@@ -291,3 +291,7 @@
 		};
 	};
 };
+
+&vpu {
+	compatible = "fsl,imx6q-vpu", "cnm,coda960";
+};
arch/arm/boot/dts/imx6qdl.dtsi +8 -2
index eca0971..2052303 100644
@@ -315,9 +315,15 @@
 			};
 
 			vpu: vpu at 02040000 {
+				compatible = "cnm,coda960";
 				reg = <0x02040000 0x3c000>;
-				interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
-				             <0 12 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
+				             <0 3 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "bit", "jpeg";
+				clocks = <&clks 168>, <&clks 168>;
+				clock-names = "per", "ahb";
+				resets = <&src 1>;
+				iram = <&ocram>;
 			};
 
 			aipstz at 0207c000 { /* AIPSTZ1 */
Signature · 1 line
2.0.0
#4 lore raw

PATCH 4/4 ARM: dts: imx6qdl: Enable CODA960 VPU

Quoted 43 lines · Philipp Zabel

This patch adds links to the on-chip SRAM and reset controller nodes and switches the interrupts. Make the BIT processor interrupt, which exists on all variants, the first one. The JPEG unit interrupt, which does not exist on i.MX27 and i.MX5 thus is an optional second interrupt.
Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to load separate firmware images for some reason.

Signed-off-by Philipp Zabel <[email protected]>
---
 arch/arm/boot/dts/imx6dl.dtsi  |  4 ++++
 arch/arm/boot/dts/imx6q.dtsi   |  4 ++++
 arch/arm/boot/dts/imx6qdl.dtsi | 10 ++++++++--
 3 files changed, 16 insertions(+), 2 deletions(-)
arch/arm/boot/dts/imx6dl.dtsi +4 -0
index 5c5f574..fbbdfca 100644
@@ -110,3 +110,7 @@
                      "di0_sel", "di1_sel",
                      "di0", "di1";
 };
+
+&vpu {
+       compatible = "fsl,imx6dl-vpu", "cnm,coda960";
+};
arch/arm/boot/dts/imx6q.dtsi +4 -0
index addd3f8..2c1dbf8 100644
@@ -291,3 +291,7 @@
                };
        };
 };
+
+&vpu {
+       compatible = "fsl,imx6q-vpu", "cnm,coda960";
+};
arch/arm/boot/dts/imx6qdl.dtsi +0 -0
index eca0971..2052303 100644

arch/arm/boot/dts/imx6qdl.dtsi line 321

Quoted 9 lines
arch/arm/boot/dts/imx6qdl.dtsi +3 -2
@@ -315,9 +315,15 @@
                        };
 
                        vpu: vpu at 02040000 {
+                               compatible = "cnm,coda960";
                                reg = <0x02040000 0x3c000>;
-                               interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
-                                            <0 12 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
+                                            <0 3 IRQ_TYPE_LEVEL_HIGH>;

Is there an existing user? This would break things if so.

Rob

#5 lore raw

PATCH 4/4 ARM: dts: imx6qdl: Enable CODA960 VPU

Quoted 46 lines · Rob Herring
Quoted 45 lines · Philipp Zabel

This patch adds links to the on-chip SRAM and reset controller nodes and switches the interrupts. Make the BIT processor interrupt, which exists on all variants, the first one. The JPEG unit interrupt, which does not exist on i.MX27 and i.MX5 thus is an optional second interrupt.
Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to load separate firmware images for some reason.

Signed-off-by Philipp Zabel <[email protected]>
---
 arch/arm/boot/dts/imx6dl.dtsi  |  4 ++++
 arch/arm/boot/dts/imx6q.dtsi   |  4 ++++
 arch/arm/boot/dts/imx6qdl.dtsi | 10 ++++++++--
 3 files changed, 16 insertions(+), 2 deletions(-)
arch/arm/boot/dts/imx6dl.dtsi +4 -0
index 5c5f574..fbbdfca 100644
@@ -110,3 +110,7 @@
                      "di0_sel", "di1_sel",
                      "di0", "di1";
 };
+
+&vpu {
+       compatible = "fsl,imx6dl-vpu", "cnm,coda960";
+};
arch/arm/boot/dts/imx6q.dtsi +4 -0
index addd3f8..2c1dbf8 100644
@@ -291,3 +291,7 @@
                };
        };
 };
+
+&vpu {
+       compatible = "fsl,imx6q-vpu", "cnm,coda960";
+};
arch/arm/boot/dts/imx6qdl.dtsi +0 -0
index eca0971..2052303 100644
@@ -315,9 +315,15 @@
                        };
Quoted 9 lines

arch/arm/boot/dts/imx6qdl.dtsi line 321

Quoted 7 lines
arch/arm/boot/dts/imx6qdl.dtsi +3 -2
                        vpu: vpu at 02040000 {
+                               compatible = "cnm,coda960";
                                reg = <0x02040000 0x3c000>;
-                               interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
-                                            <0 12 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
+                                            <0 3 IRQ_TYPE_LEVEL_HIGH>;

Is there an existing user? This would break things if so.

Not that I know of, there wasn't even a compatible value in this node.

There is an existing driver for coda7 that expects the first interrupt to be the BIT processor interrupt (<0 12 ...> in this case). Today I have submitted patches to linux-media that add support for coda9, which only works with this change.

regards
Philipp

#6 lore raw

PATCH 4/4 ARM: dts: imx6qdl: Enable CODA960 VPU

In reply to Philipp Zabel
Quoted 8 lines · Philipp Zabel

This patch adds links to the on-chip SRAM and reset controller nodes and switches the interrupts. Make the BIT processor interrupt, which exists on all variants, the first one. The JPEG unit interrupt, which does not exist on i.MX27 and i.MX5 thus is an optional second interrupt.
Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to load separate firmware images for some reason.

Signed-off-by Philipp Zabel <[email protected]>

The whole series looks good to me.

Rob,

Do you want to apply the first patch through DT tree, or may I have your ACK to take the whole series via IMX tree?

Shawn

Quoted 55 lines
---
 arch/arm/boot/dts/imx6dl.dtsi  |  4 ++++
 arch/arm/boot/dts/imx6q.dtsi   |  4 ++++
 arch/arm/boot/dts/imx6qdl.dtsi | 10 ++++++++--
 3 files changed, 16 insertions(+), 2 deletions(-)
arch/arm/boot/dts/imx6dl.dtsi +4 -0
index 5c5f574..fbbdfca 100644
@@ -110,3 +110,7 @@
 		      "di0_sel", "di1_sel",
 		      "di0", "di1";
 };
+
+&vpu {
+	compatible = "fsl,imx6dl-vpu", "cnm,coda960";
+};
arch/arm/boot/dts/imx6q.dtsi +4 -0
index addd3f8..2c1dbf8 100644
@@ -291,3 +291,7 @@
 		};
 	};
 };
+
+&vpu {
+	compatible = "fsl,imx6q-vpu", "cnm,coda960";
+};
arch/arm/boot/dts/imx6qdl.dtsi +8 -2
index eca0971..2052303 100644
@@ -315,9 +315,15 @@
 			};
 
 			vpu: vpu at 02040000 {
+				compatible = "cnm,coda960";
 				reg = <0x02040000 0x3c000>;
-				interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
-				             <0 12 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
+				             <0 3 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "bit", "jpeg";
+				clocks = <&clks 168>, <&clks 168>;
+				clock-names = "per", "ahb";
+				resets = <&src 1>;
+				iram = <&ocram>;
 			};
 
 			aipstz at 0207c000 { /* AIPSTZ1 */
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#7 lore raw

PATCH 4/4 ARM: dts: imx6qdl: Enable CODA960 VPU

Am Mittwoch, den 18.06.2014, 23:12 +0800 schrieb Shawn Guo:

Quoted 8 lines · Philipp Zabel
Quoted 7 lines

This patch adds links to the on-chip SRAM and reset controller nodes and switches the interrupts. Make the BIT processor interrupt, which exists on all variants, the first one. The JPEG unit interrupt, which does not exist on i.MX27 and i.MX5 thus is an optional second interrupt.
Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to load separate firmware images for some reason.

Quoted 8 lines
Quoted 1 line
Signed-off-by Philipp Zabel <[email protected]>

The whole series looks good to me.

Rob,

Do you want to apply the first patch through DT tree, or may I have your ACK to take the whole series via IMX tree?

Hi,

are there any reservations about these patches being merged through Shawn's IMX tree?

regards
Philipp