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ARM: shmobile: Lager SYS-DMAC and MSIOF prototype

PATCH New Magnus Damm 1 participant 1 message Jun 25, 2014

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Device tree bindings Arm (32-bit) Arm sub-architectures SuperH +1 more subsystems
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Magnus Damm

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PATCH 3/5 ARM: shmobile: Lager SYS-DMAC and MSIOF prototype

From: Magnus Damm <[email protected]>

Enable DMA for MSIOF on r8a7790 Lager.

Signed-off-by Magnus Damm <[email protected]>

---

 arch/arm/boot/dts/r8a7790.dtsi                 |    8 ++++----
 arch/arm/mach-shmobile/board-lager-reference.c |   22 ++++++++++++++++++++++
 2 files changed, 26 insertions(+), 4 deletions(-)
arch/arm/boot/dts/r8a7790.dtsi +4 -4
@@ -892,7 +892,7 @@
 
 	msiof0: spi@e6e20000 {
 		compatible = "renesas,msiof-r8a7790";
-		reg = <0 0xe6e20000 0 0x0064>;
+		reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
 		interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
 		#address-cells = <1>;

@@ -902,7 +902,7 @@
 
 	msiof1: spi@e6e10000 {
 		compatible = "renesas,msiof-r8a7790";
-		reg = <0 0xe6e10000 0 0x0064>;
+		reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
 		interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
 		#address-cells = <1>;

@@ -912,7 +912,7 @@
 
 	msiof2: spi@e6e00000 {
 		compatible = "renesas,msiof-r8a7790";
-		reg = <0 0xe6e00000 0 0x0064>;
+		reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
 		interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
 		#address-cells = <1>;

@@ -922,7 +922,7 @@
 
 	msiof3: spi@e6c90000 {
 		compatible = "renesas,msiof-r8a7790";
-		reg = <0 0xe6c90000 0 0x0064>;
+		reg = <0 0xe6c90000 0 0x0064>, <0 0xe7c90000 0 0x0064>;
 		interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
 		#address-cells = <1>;
arch/arm/mach-shmobile/board-lager-reference.c +22 -0
@@ -77,6 +77,7 @@ static const struct resource du_resource
 #include <linux/mfd/tmio.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/serial_sci.h>
+#include <linux/spi/sh_msiof.h>
 
 /* Local DMA slave IDs */
 enum {

@@ -109,6 +110,14 @@ enum {
 	SYS_DMAC_SLAVE_HSCIF0_RX,
 	SYS_DMAC_SLAVE_HSCIF1_TX,
 	SYS_DMAC_SLAVE_HSCIF1_RX,
+	SYS_DMAC_SLAVE_MSIOF0_TX,
+	SYS_DMAC_SLAVE_MSIOF0_RX,
+	SYS_DMAC_SLAVE_MSIOF1_TX,
+	SYS_DMAC_SLAVE_MSIOF1_RX,
+	SYS_DMAC_SLAVE_MSIOF2_TX,
+	SYS_DMAC_SLAVE_MSIOF2_RX,
+	SYS_DMAC_SLAVE_MSIOF3_TX,
+	SYS_DMAC_SLAVE_MSIOF3_RX,
 };
 
 #define DMAE_CHANNEL(a, b)			\

@@ -156,6 +165,10 @@ static const struct sh_dmae_slave_config
 	SYS_DMAC_SLAVE_TX(SCIFB2, 8, 0xe6ce0000, 0x40, 0x60, 0x1d, 0x1e),
 	SYS_DMAC_SLAVE_TX(HSCIF0, 8, 0xe62c0000, 0xc, 0x14, 0x39, 0x3a),
 	SYS_DMAC_SLAVE_TX(HSCIF1, 8, 0xe62c8000, 0xc, 0x14, 0x4d, 0x4e),
+	SYS_DMAC_SLAVE(MSIOF0, 32, 0xe7e20000, 0x50, 0x60, 0x51, 0x52),
+	SYS_DMAC_SLAVE(MSIOF1, 32, 0xe7e10000, 0x50, 0x60, 0x55, 0x56),
+	SYS_DMAC_SLAVE(MSIOF2, 32, 0xe7e00000, 0x50, 0x60, 0x41, 0x42),
+	SYS_DMAC_SLAVE(MSIOF3, 32, 0xec900000, 0x50, 0x60, 0x45, 0x46),
 };
 
 static const struct sh_dmae_channel r8a7790_sys_dmac_channels[] = {

@@ -284,6 +297,13 @@ PDATA_HSCIF(9, 0xe62c8000, gic_spi(155),
 #define AUXDATA_SCIFB(index, baseaddr, irq) SCIF_AD("scifb", index, baseaddr)
 #define AUXDATA_HSCIF(index, baseaddr, irq) SCIF_AD("hscif", index, baseaddr)
 
+static struct sh_msiof_spi_info msiof1_info = {
+	.rx_fifo_override       = 256,
+	.num_chipselect         = 1,
+	.dma_tx_id              = SYS_DMAC_SLAVE_MSIOF1_TX,
+	.dma_rx_id              = SYS_DMAC_SLAVE_MSIOF1_RX,
+};
+
 static struct of_dev_auxdata lager_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("renesas,mmcif-r8a7790", 0xee220000, "sh_mmcif",
 			&mmcif1_pdata),

@@ -301,6 +321,8 @@ static struct of_dev_auxdata lager_auxda
 	AUXDATA_SCIF(7,  0xe6e68000, gic_spi(153)), /* SCIF1 */
 	AUXDATA_HSCIF(8, 0xe62c0000, gic_spi(154)), /* HSCIF0 */
 	AUXDATA_HSCIF(9, 0xe62c8000, gic_spi(155)), /* HSCIF1 */
+	OF_DEV_AUXDATA("renesas,msiof-r8a7790", 0xe6e10000,
+		       "spi_r8a7790_msiof.0", &msiof1_info),
 	{},
 };