ARM: i.MX21 clk: Clock initialization rework

PATCH New Alexander Shiyan 2 participants 5 messages Jun 22, 2014 – Jun 25, 2014

Subsystems (6)

Device tree bindings Arm (32-bit) Arm sub-architectures Arm i.MX and Layerscape +2 more subsystems

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Alexander Shiyan

author

2014-06-22 13:17 UTC #0 lore raw

PATCH 1/4 ARM: i.MX21 clk: Clock initialization rework

This patch perform rework i.MX21 clock initialization. This includes adding missing clocks and sort clocks by register address.

Signed-off-by Alexander Shiyan <[email protected]>

---
 arch/arm/mach-imx/clk-imx21.c | 113 +++++++++++++++++++++++++-----------------
 arch/arm/mach-imx/clk.h       |   7 +++
 2 files changed, 75 insertions(+), 45 deletions(-)

arch/arm/mach-imx/clk-imx21.c +68 ~~-45~~

index 4a20c66..d7f1561 100644
@@ -47,19 +47,23 @@
 #define CCM_PMCOUNT		IO_ADDR_CCM(0x30)
 #define CCM_WKGDCTL		IO_ADDR_CCM(0x34)
 
-static const char *mpll_sel_clks[] = { "fpm", "ckih", };
-static const char *spll_sel_clks[] = { "fpm", "ckih", };
+static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", };
+static const char *mpll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };
+static const char *spll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };
+static const char *ssi_sel_clks[] = { "spll_gate", "mpll_gate", };
 
 enum imx21_clks {
-	ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1,
+	dummy, ckil, ckih, fpm, ckih_div1p5, mpll_gate, spll_gate, fpm_gate,
+	ckih_gate, mpll_osc_sel, ipg, hclk, mpll_sel, spll_sel, ssi1_sel,
+	ssi2_sel, usb_div, fclk, mpll, spll, nfc_div, ssi1_div, ssi2_div, per1,
 	per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate,
-	uart4_ipg_gate, gpt1_ipg_gate, gpt2_ipg_gate, gpt3_ipg_gate,
-	pwm_ipg_gate, sdhc1_ipg_gate, sdhc2_ipg_gate, lcdc_ipg_gate,
-	lcdc_hclk_gate, cspi3_ipg_gate, cspi2_ipg_gate, cspi1_ipg_gate,
-	per4_gate, csi_hclk_gate, usb_div, usb_gate, usb_hclk_gate, ssi1_gate,
-	ssi2_gate, nfc_div, nfc_gate, dma_gate, dma_hclk_gate, brom_gate,
-	emma_gate, emma_hclk_gate, slcdc_gate, slcdc_hclk_gate, wdog_gate,
-	gpio_gate, i2c_gate, kpp_gate, owire_gate, rtc_gate, clk_max
+	uart4_ipg_gate, cspi1_ipg_gate, cspi2_ipg_gate, ssi1_gate, ssi2_gate,
+	sdhc1_ipg_gate, sdhc2_ipg_gate, gpio_gate, i2c_gate, dma_gate, usb_gate,
+	emma_gate, ssi2_baud_gate, ssi1_baud_gate, lcdc_ipg_gate, nfc_gate,
+	lcdc_hclk_gate, per4_gate, bmi_gate, usb_hclk_gate, slcdc_gate,
+	slcdc_hclk_gate, emma_hclk_gate, brom_gate, dma_hclk_gate,
+	csi_hclk_gate, cspi3_ipg_gate, wdog_gate, gpt1_ipg_gate, gpt2_ipg_gate,
+	gpt3_ipg_gate, pwm_ipg_gate, rtc_gate, kpp_gate, owire_gate, clk_max
 };
 
 static struct clk *clk[clk_max];

@@ -70,59 +74,78 @@ static struct clk *clk[clk_max];
  */
 int __init mx21_clocks_init(unsigned long lref, unsigned long href)
 {
+	clk[dummy] = imx_clk_fixed("dummy", 0);
 	clk[ckil] = imx_clk_fixed("ckil", lref);
 	clk[ckih] = imx_clk_fixed("ckih", href);
 	clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
-	clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
-			ARRAY_SIZE(mpll_sel_clks));
-	clk[spll_sel] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks,
-			ARRAY_SIZE(spll_sel_clks));
+	clk[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3);
+
+	clk[mpll_gate] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
+	clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
+	clk[fpm_gate] = imx_clk_gate("fpm_gate", "fpm", CCM_CSCR, 2);
+	clk[ckih_gate] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3);
+	clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks));
+	clk[ipg] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
+	clk[hclk] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
+	clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));
+	clk[spll_sel] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, ARRAY_SIZE(spll_sel_clks));
+	clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 19, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
+	clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 20, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
+	clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 26, 3);
+	clk[fclk] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 29, 3);
+
 	clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
+
 	clk[spll] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);
-	clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 29, 3);
-	clk[hclk] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
-	clk[ipg] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
-	clk[per1] = imx_clk_divider("per1", "mpll", CCM_PCDR1, 0, 6);
-	clk[per2] = imx_clk_divider("per2", "mpll", CCM_PCDR1, 8, 6);
-	clk[per3] = imx_clk_divider("per3", "mpll", CCM_PCDR1, 16, 6);
-	clk[per4] = imx_clk_divider("per4", "mpll", CCM_PCDR1, 24, 6);
+
+	clk[nfc_div] = imx_clk_divider("nfc_div", "fclk", CCM_PCDR0, 12, 4);
+	clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
+	clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
+
+	clk[per1] = imx_clk_divider("per1", "mpll_gate", CCM_PCDR1, 0, 6);
+	clk[per2] = imx_clk_divider("per2", "mpll_gate", CCM_PCDR1, 8, 6);
+	clk[per3] = imx_clk_divider("per3", "mpll_gate", CCM_PCDR1, 16, 6);
+	clk[per4] = imx_clk_divider("per4", "mpll_gate", CCM_PCDR1, 24, 6);
+
 	clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
 	clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
 	clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
 	clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
-	clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
-	clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
-	clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
-	clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
-	clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
-	clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
-	clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
-	clk[lcdc_hclk_gate] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
-	clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
-	clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
 	clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
-	clk[per4_gate] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
-	clk[csi_hclk_gate] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
-	clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 26, 3);
-	clk[usb_gate] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
-	clk[usb_hclk_gate] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
+	clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
 	clk[ssi1_gate] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
 	clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
-	clk[nfc_div] = imx_clk_divider("nfc_div", "ipg", CCM_PCDR0, 12, 4);
-	clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
+	clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
+	clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
+	clk[gpio_gate] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
+	clk[i2c_gate] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
 	clk[dma_gate] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
-	clk[dma_hclk_gate] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
-	clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
+	clk[usb_gate] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
 	clk[emma_gate] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
-	clk[emma_hclk_gate] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
-	clk[slcdc_gate] = imx_clk_gate("slcdc_gate", "ipg", CCM_PCCR0, 25);
+	clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ipg", CCM_PCCR0, 16);
+	clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ipg", CCM_PCCR0, 17);
+	clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
+	clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
 	clk[slcdc_hclk_gate] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
+	clk[per4_gate] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
+	clk[bmi_gate] = imx_clk_gate("bmi_gate", "hclk", CCM_PCCR0, 23);
+	clk[usb_hclk_gate] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
+	clk[slcdc_gate] = imx_clk_gate("slcdc_gate", "hclk", CCM_PCCR0, 25);
+	clk[lcdc_hclk_gate] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
+	clk[emma_hclk_gate] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
+	clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
+	clk[dma_hclk_gate] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
+	clk[csi_hclk_gate] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
+
+	clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
 	clk[wdog_gate] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
-	clk[gpio_gate] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
-	clk[i2c_gate] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
+	clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
+	clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
+	clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
+	clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
+	clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
 	clk[kpp_gate] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
 	clk[owire_gate] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
-	clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
 
 	imx_check_clocks(clk, ARRAY_SIZE(clk));

arch/arm/mach-imx/clk.h +7 -0

index 45c1eb7..f1f04e3 100644
@@ -97,6 +97,13 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent,
 			shift, 0, &imx_ccm_lock);
 }
 
+static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
+		void __iomem *reg, u8 shift)
+{
+	return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+			shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
+}
+
 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
 		u8 shift, u8 width, const char **parents, int num_parents)
 {

Signature · 1 line

1.8.5.5

Alexander Shiyan

author

2014-06-22 13:17 UTC #1 lore raw

PATCH 2/4 ARM: i.MX21 clk: Remove clk_register_clkdev() for unused clocks

This patch removes clk_register_clkdev() for the clocks that do not have any users for boards and drivers.

Signed-off-by Alexander Shiyan <[email protected]>

---
 arch/arm/mach-imx/clk-imx21.c | 19 -------------------
 1 file changed, 19 deletions(-)

arch/arm/mach-imx/clk-imx21.c +0 ~~-19~~

index d7f1561..3f914e4 100644
@@ -149,10 +149,6 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
 
 	imx_check_clocks(clk, ARRAY_SIZE(clk));
 
-	clk_register_clkdev(clk[per1], "per1", NULL);
-	clk_register_clkdev(clk[per2], "per2", NULL);
-	clk_register_clkdev(clk[per3], "per3", NULL);
-	clk_register_clkdev(clk[per4], "per4", NULL);
 	clk_register_clkdev(clk[per1], "per", "imx21-uart.0");
 	clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
 	clk_register_clkdev(clk[per1], "per", "imx21-uart.1");

@@ -163,10 +159,6 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
 	clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
 	clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
 	clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
-	clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1");
-	clk_register_clkdev(clk[per1], "per", "imx-gpt.1");
-	clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
-	clk_register_clkdev(clk[per1], "per", "imx-gpt.2");
 	clk_register_clkdev(clk[per2], "per", "imx21-cspi.0");
 	clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0");
 	clk_register_clkdev(clk[per2], "per", "imx21-cspi.1");

@@ -183,18 +175,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
 	clk_register_clkdev(clk[dma_gate], "ipg", "imx21-dma");
 	clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
 	clk_register_clkdev(clk[i2c_gate], NULL, "imx21-i2c.0");
-	clk_register_clkdev(clk[kpp_gate], NULL, "mxc-keypad");
 	clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
-	clk_register_clkdev(clk[brom_gate], "brom", NULL);
-	clk_register_clkdev(clk[emma_gate], "emma", NULL);
-	clk_register_clkdev(clk[slcdc_gate], "slcdc", NULL);
-	clk_register_clkdev(clk[gpio_gate], "gpio", NULL);
-	clk_register_clkdev(clk[rtc_gate], "rtc", NULL);
-	clk_register_clkdev(clk[csi_hclk_gate], "csi", NULL);
-	clk_register_clkdev(clk[ssi1_gate], "ssi1", NULL);
-	clk_register_clkdev(clk[ssi2_gate], "ssi2", NULL);
-	clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL);
-	clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL);
 
 	mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1);

Signature · 1 line

1.8.5.5

Alexander Shiyan

author

2014-06-22 13:17 UTC #2 lore raw

PATCH 3/4 ARM: i.MX21 clk: Cleanup driver

In reply to Alexander Shiyan

This is a cleanup for i.MX21 clk driver. This change includes:
- Reduce license text.
- Remove unused definitions.
- Remove unused #include and sort the rest.
- Remove useless comment.

Signed-off-by Alexander Shiyan <[email protected]>

---
 arch/arm/mach-imx/clk-imx21.c | 25 +------------------------
 1 file changed, 1 insertion(+), 24 deletions(-)

arch/arm/mach-imx/clk-imx21.c +1 ~~-24~~

index 3f914e4..9907135 100644
@@ -7,23 +7,11 @@
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version 2
  * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
  */
 
 #include <linux/clk.h>
-#include <linux/clkdev.h>
 #include <linux/clk-provider.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/err.h>
+#include <linux/clkdev.h>
 
 #include "clk.h"
 #include "common.h"

@@ -34,18 +22,11 @@
 /* Register offsets */
 #define CCM_CSCR		IO_ADDR_CCM(0x0)
 #define CCM_MPCTL0		IO_ADDR_CCM(0x4)
-#define CCM_MPCTL1		IO_ADDR_CCM(0x8)
 #define CCM_SPCTL0		IO_ADDR_CCM(0xc)
-#define CCM_SPCTL1		IO_ADDR_CCM(0x10)
-#define CCM_OSC26MCTL		IO_ADDR_CCM(0x14)
 #define CCM_PCDR0		IO_ADDR_CCM(0x18)
 #define CCM_PCDR1		IO_ADDR_CCM(0x1c)
 #define CCM_PCCR0		IO_ADDR_CCM(0x20)
 #define CCM_PCCR1		IO_ADDR_CCM(0x24)
-#define CCM_CCSR		IO_ADDR_CCM(0x28)
-#define CCM_PMCTL		IO_ADDR_CCM(0x2c)
-#define CCM_PMCOUNT		IO_ADDR_CCM(0x30)
-#define CCM_WKGDCTL		IO_ADDR_CCM(0x34)
 
 static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", };
 static const char *mpll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };

@@ -68,10 +49,6 @@ enum imx21_clks {
 
 static struct clk *clk[clk_max];
 
-/*
- * must be called very early to get information about the
- * available clock rate when the timer framework starts
- */
 int __init mx21_clocks_init(unsigned long lref, unsigned long href)
 {
 	clk[dummy] = imx_clk_fixed("dummy", 0);

Signature · 1 line

1.8.5.5

Alexander Shiyan

author

2014-06-22 13:17 UTC #3 lore raw

PATCH 4/4 ARM: i.MX21 clk: Add devicetree support

In reply to Alexander Shiyan

This patch adds devicetree support CCM module for i.MX21 CPUs.

Signed-off-by Alexander Shiyan <[email protected]>

---
 .../devicetree/bindings/clock/imx21-clock.txt      |  28 +++
 arch/arm/mach-imx/clk-imx21.c                      | 259 +++++++++++----------
 include/dt-bindings/clock/imx21-clock.h            |  80 +++++++
 3 files changed, 244 insertions(+), 123 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/imx21-clock.txt
 create mode 100644 include/dt-bindings/clock/imx21-clock.h

Documentation/devicetree/bindings/clock/imx21-clock.txt new file +28 -0

new file mode 100644
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+* Clock bindings for Freescale i.MX21
+
+Required properties:
+- compatible  : Should be "fsl,imx21-ccm".
+- reg         : Address and length of the register set.
+- interrupts  : Should contain CCM interrupt.
+- #clock-cells: Should be <1>.
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h
+for the full list of i.MX21 clock IDs.
+
+Examples:
+	clks: ccm at 10027000{
+		compatible = "fsl,imx21-ccm";
+		reg = <0x10027000 0x800>;
+		#clock-cells = <1>;
+	};
+
+	uart1: serial at 1000a000 {
+		compatible = "fsl,imx21-uart";
+		reg = <0x1000a000 0x1000>;
+		interrupts = <20>;
+		clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
+			 <&clks IMX21_CLK_PER1>;
+		clock-names = "ipg", "per";
+		status = "disabled";
+	};

arch/arm/mach-imx/clk-imx21.c +136 ~~-123~~

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include/dt-bindings/clock/imx21-clock.h new file +80 -0

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Signature · 1 line

1.8.5.5

Shawn Guo

Applied

2014-06-25 16:17 UTC #4 lore raw

PATCH 1/4 ARM: i.MX21 clk: Clock initialization rework

In reply to Alexander Shiyan

Quoted 4 lines · Alexander Shiyan

This patch perform rework i.MX21 clock initialization. This includes adding missing clocks and sort clocks by register address.
Signed-off-by Alexander Shiyan <[email protected]>

Applied all, thanks.