mtd: hisilicon: add a new driver for NAND controller of hisilicon hip04 Soc
Subsystems (3)
cover mtd: hisilicon: add a new driver for NAND controller of hisilicon hip04 Soc
This series patches add the support for NAND controller of hisilicon hip04 Soc. These patches are base on branch integration-hilt-working-v3.14 in linaro landing-team git repository[1].
The NAND controller IP was developed by hisilicon and need a new driver to support. The driver is usable and I tested it on hisilicon hip04-d01 board.
[1] ssh://git at git.linaro.org/landing-teams/working/hisilicon/kernel.git
Zhou Wang (3):
mtd: hisilicon: add device tree node for nand controller
mtd: hisilicon: add a new nand controller driver for hisilicon hip04
Soc
mtd: hisilicon: add device tree binding documentation
.../devicetree/bindings/mtd/hisi-nand.txt | 38 + arch/arm/boot/dts/hip04.dtsi | 31 + drivers/mtd/nand/Kconfig | 5 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/hisi_nand.c | 847 ++++++++++++++++++++ 5 files changed, 922 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/hisi-nand.txt create mode 100644 drivers/mtd/nand/hisi_nand.c
Signature · 1 line
1.7.9.5
PATCH 1/3 mtd: hisilicon: add device tree node for nand controller
--- arch/arm/boot/dts/hip04.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)
arch/arm/boot/dts/hip04.dtsi +31 -0
@@ -386,5 +386,36 @@ interrupts = <0 389 4>; }; }; + + nand: nand at 4020000 { + compatible = "hisilicon,504-nfc"; + reg = <0x4020000 0x10000>, <0x5000000 0x1000>; + interrupts = <0 379 4>; + nand-bus-width = <8>; + nand-ecc-mode = "none"; + hisi,nand-ecc-bits = <0>; + #address-cells = <1>; + #size-cells = <1>; + + partition at 0 { + label = "nand_text"; + reg = <0x00000000 0x00400000>; + }; + + partition at 00400000 { + label = "nand_monitor"; + reg = <0x00400000 0x00400000>; + }; + + partition at 00800000 { + label = "nand_kernel"; + reg = <0x00800000 0x00800000>; + }; + + partition at 01000000 { + label = "nand_fs"; + reg = <0x01000000 0x1f000000>; + }; + }; }; };
Signature · 1 line
1.7.9.5
Re: [PATCH 1/3] mtd: hisilicon: add device tree node for nand controller
Quoted 10 lines · Zhou Wang
Signed-off-by Zhou Wang <[email protected]>--- arch/arm/boot/dts/hip04.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)arch/arm/boot/dts/hip04.dtsi +0
-0
arch/arm/boot/dts/hip04.dtsi line 391
Quoted 6 lines
arch/arm/boot/dts/hip04.dtsi +3
-0@@ -386,5 +386,36 @@ interrupts = <0 389 4>; }; }; + + nand: nand at 4020000 { + compatible = "hisilicon,504-nfc";
In PATCH 2/3 and 3/3 you are using "hisilicon,nfc504".
Quoted 31 lines
arch/arm/boot/dts/hip04.dtsi +28
-0+ reg = <0x4020000 0x10000>, <0x5000000 0x1000>; + interrupts = <0 379 4>; + nand-bus-width = <8>; + nand-ecc-mode = "none"; + hisi,nand-ecc-bits = <0>; + #address-cells = <1>; + #size-cells = <1>; + + partition at 0 { + label = "nand_text"; + reg = <0x00000000 0x00400000>; + }; + + partition at 00400000 { + label = "nand_monitor"; + reg = <0x00400000 0x00400000>; + }; + + partition at 00800000 { + label = "nand_kernel"; + reg = <0x00800000 0x00800000>; + }; + + partition at 01000000 { + label = "nand_fs"; + reg = <0x01000000 0x1f000000>; + }; + }; }; };
Signature · 1 line
Jerome
Re: [PATCH 1/3] mtd: hisilicon: add device tree node for nand controller
Quoted 6 lines · Jerome FORISSIER
Quoted 5 lines · Zhou Wang
Signed-off-by Zhou Wang <[email protected]>--- arch/arm/boot/dts/hip04.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)
Quoted 14 lines
arch/arm/boot/dts/hip04.dtsi line 391
Quoted 11 lines
arch/arm/boot/dts/hip04.dtsi +3
-0@@ -386,5 +386,36 @@ interrupts = <0 389 4>; }; }; + + nand: nand at 4020000 { + compatible = "hisilicon,504-nfc";In PATCH 2/3 and 3/3 you are using "hisilicon,nfc504".
It was my mistake. All should be "hisilicon,504-nfc". Thanks a lot.
Quoted 32 lines
Quoted 31 lines
arch/arm/boot/dts/hip04.dtsi +28
-0+ reg = <0x4020000 0x10000>, <0x5000000 0x1000>; + interrupts = <0 379 4>; + nand-bus-width = <8>; + nand-ecc-mode = "none"; + hisi,nand-ecc-bits = <0>; + #address-cells = <1>; + #size-cells = <1>; + + partition at 0 { + label = "nand_text"; + reg = <0x00000000 0x00400000>; + }; + + partition at 00400000 { + label = "nand_monitor"; + reg = <0x00400000 0x00400000>; + }; + + partition at 00800000 { + label = "nand_kernel"; + reg = <0x00800000 0x00800000>; + }; + + partition at 01000000 { + label = "nand_fs"; + reg = <0x01000000 0x1f000000>; + }; + }; }; };
PATCH 2/3 mtd: hisilicon: add a new nand controller driver for hisilicon hip04 Soc
In reply to Zhou Wang--- drivers/mtd/nand/Kconfig | 5 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/hisi_nand.c | 847 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 853 insertions(+) create mode 100644 drivers/mtd/nand/hisi_nand.c
drivers/mtd/nand/Kconfig +5 -0
@@ -510,4 +510,9 @@ config MTD_NAND_XWAY Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached to the External Bus Unit (EBU). +config MTD_NAND_HISI + tristate "Support for NAND controller on Hisilicon SoC" + help + Enables support for NAND controller on Hisilicon SoC. + endif # MTD_NAND
drivers/mtd/nand/Makefile +1 -0
@@ -49,5 +49,6 @@ obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/ obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/ +obj-$(CONFIG_MTD_NAND_HISI) += hisi_nand.o nand-objs := nand_base.o nand_bbt.o
drivers/mtd/nand/hisi_nand.c new file +847 -0
847 lines not on this page · raw message
Signature · 1 line
1.7.9.5
Re: [PATCH 2/3] mtd: hisilicon: add a new nand controller driver for hisilicon hip04 Soc
Overall a very nice driver. I didn't find any real bugs, but a few things that could be changed for readability and micro-optimizations:
drivers/mtd/nand/hisi_nand.c line 137
Quoted 3 lines · On Monday 30 June 2014 16:03:28 Zhou Wang wrote:
drivers/mtd/nand/hisi_nand.c new file +3
-0+#define hinfc_read (_host, _reg) readl(_host->iobase + (_reg)) +#define hinfc_write (_host, _value, _reg)\ + writel((_value), _host->iobase + (_reg))
I'd recommend making these inline functions rather than macros.
drivers/mtd/nand/hisi_nand.c line 141
Quoted 3 lines
drivers/mtd/nand/hisi_nand.c new file +3
-0+struct hinfc_host { +struct nand_chip *chip; +struct mtd_info *mtd;
I notice that you allocate the nand_chip and mtd_info together with the hinfc_host and then assign these pointers. A preferred method is normally to just embed the structures in this case:
struct hinfc_host {
struct nand_chip chip;
struct mtd_info mtd;so you avoid the pointer overhead, and can go back from these two structures to the hinfc_host using container_of().
Quoted 13 lines
drivers/mtd/nand/hisi_nand.c new file +13
-0+struct device *dev; +void __iomem *iobase; +struct completion cmd_complete; +unsigned int offset; +unsigned int command; +int chipselect; +unsigned int addr_cycle; +unsigned int addr_value[2 ]; +unsigned int cache_addr_value[2 ]; +char *buffer; +dma_addr_t dma_buffer; +dma_addr_t dma_oob; +int version;
drivers/mtd/nand/hisi_nand.c line 164
Quoted 10 lines
drivers/mtd/nand/hisi_nand.c new file +10
-0+unsigned int ecc_bits; +unsigned int irq_status;/* interrupt status */ + +int (*send_cmd_pageprog)(struct hinfc_host *host); +int (*send_cmd_status)(struct hinfc_host *host); +int (*send_cmd_readstart)(struct hinfc_host *host); +int (*send_cmd_erase)(struct hinfc_host *host); +int (*send_cmd_readid)(struct hinfc_host *host); +int (*send_cmd_reset)(struct hinfc_host *host,int chipselect); +};
Why do you need function pointers here? The current version of the driver you posted always assigns these to the same functions, so it would be more efficient to just call those directly.
If you plan to add another variant later that uses a different set of functions here, you can add the function pointers then, in a separate patch. Also, a common style element is to have a separate constant structure with the function pointers:
const struct hinfc_host_ops ops = {
.send_cmd_pageprog = hisi_nfc_send_cmd_pageprog,
...
};if you actually end up needing function pointers. That simplifies the code a bit and is slightly more robust to attacks overwriting the function pointers.
Quoted 14 lines
drivers/mtd/nand/hisi_nand.c new file +14
-0+ +void wait_controller_finished (struct hinfc_host *host) +{ +unsigned long timeout = jiffies +HINFC504_NFC_TIMEOUT ; +int val; + +while (time_before (jiffies, timeout)) { + val =hinfc_read (host,HINFC504_STATUS ); +if (host->command ==NAND_CMD_ERASE2 ) { +/* nfc is ready */ +while (!(val &HINFC504_READY )) { +usleep_range (500 ,1000 ); + val =hinfc_read (host,HINFC504_STATUS ); + }
drivers/mtd/nand/hisi_nand.c line 188
Quoted 10 lines
drivers/mtd/nand/hisi_nand.c new file +10
-0+return ; + }else { +if (val &HINFC504_READY ) +return ; + } + } + +/* wait cmd timeout */ +dev_err (host->dev,"Wait NAND controller exec cmd timeout.\n" ); +}
Since the timeout is much bigger than the wait time here, I guess you can use a wider range for the usleep_range(), e.g.
usleep_range(500, 50000);
which is nicer to other tasks. You will normally be woken up much earlier.
Arnd
PATCH 2/3 mtd: hisilicon: add a new nand controller driver for hisilicon hip04 Soc
Quoted 33 lines
-----Original Message-----
From: Arnd Bergmann [mailto:arnd at arndb.de]
Sent: Monday, June 30, 2014 5:01 PM
To: linux-arm-kernel at lists.infradead.org
Cc: Zhou Wang; Rob Herring; Pawel Moll; Mark Rutland; Ian Campbell; Kumar Gala; Russell King; David Woodhouse; Brian Norris; Grant Likely; Ezequiel Garcia; Pekon Gupta; Artem Bityutskiy; Alexander Shiyan; Ivan Khoronzhuk; Jussi Kivilinna; Joern Engel; Randy Dunlap; devicetree at vger.kernel.org; linux-mtd at lists.infradead.org; linux-doc at vger.kernel.org; linux-kernel at vger.kernel.org; Caizhiyong; Wangzhou (B)
Subject: Re: [PATCH 2/3] mtd: hisilicon: add a new nand controller driver for hisilicon hip04 SocQuoted 19 lines
drivers/mtd/nand/hisi_nand.c new file +19
-0+struct device *dev; +void __iomem *iobase; +struct completion cmd_complete; +unsigned int offset; +unsigned int command; +int chipselect; +unsigned int addr_cycle; +unsigned int addr_value[2 ]; +unsigned int cache_addr_value[2 ]; +char *buffer; +dma_addr_t dma_buffer; +dma_addr_t dma_oob; +int version; +unsigned int ecc_bits; +unsigned int irq_status;/* interrupt status */ + +int (*send_cmd_pageprog)(struct hinfc_host *host); +int (*send_cmd_status)(struct hinfc_host *host); +int (*send_cmd_readstart)(struct hinfc_host *host);
Quoted 9 lines
drivers/mtd/nand/hisi_nand.c line 164
Quoted 4 lines
drivers/mtd/nand/hisi_nand.c new file +4
-0+int (*send_cmd_erase)(struct hinfc_host *host); +int (*send_cmd_readid)(struct hinfc_host *host); +int (*send_cmd_reset)(struct hinfc_host *host,int chipselect); +};Why do you need function pointers here? The current version of the driver you posted always assigns these to the same functions, so it would be more efficient to just call those directly.
I agree with you.
This feature was originally designed to support a variety version of NAND controllers. But in fact, this feature is not used now.
PATCH 2/3 mtd: hisilicon: add a new nand controller driver for hisilicon hip04 Soc
Quoted 43 lines · Caizhiyong
Quoted 33 lines
-----Original Message-----
From: Arnd Bergmann [mailto:arnd at arndb.de]
Sent: Monday, June 30, 2014 5:01 PM
To: linux-arm-kernel at lists.infradead.org
Cc: Zhou Wang; Rob Herring; Pawel Moll; Mark Rutland; Ian Campbell; Kumar Gala; Russell King; David Woodhouse; Brian Norris; Grant Likely; Ezequiel Garcia; Pekon Gupta; Artem Bityutskiy; Alexander Shiyan; Ivan Khoronzhuk; Jussi Kivilinna; Joern Engel; Randy Dunlap; devicetree at vger.kernel.org; linux-mtd at lists.infradead.org; linux-doc at vger.kernel.org; linux-kernel at vger.kernel.org; Caizhiyong; Wangzhou (B)
Subject: Re: [PATCH 2/3] mtd: hisilicon: add a new nand controller driver for hisilicon hip04 SocQuoted 19 lines
drivers/mtd/nand/hisi_nand.c new file +19
-0+struct device *dev; +void __iomem *iobase; +struct completion cmd_complete; +unsigned int offset; +unsigned int command; +int chipselect; +unsigned int addr_cycle; +unsigned int addr_value[2 ]; +unsigned int cache_addr_value[2 ]; +char *buffer; +dma_addr_t dma_buffer; +dma_addr_t dma_oob; +int version; +unsigned int ecc_bits; +unsigned int irq_status;/* interrupt status */ + +int (*send_cmd_pageprog)(struct hinfc_host *host); +int (*send_cmd_status)(struct hinfc_host *host); +int (*send_cmd_readstart)(struct hinfc_host *host);Quoted 9 lines
drivers/mtd/nand/hisi_nand.c line 164
Quoted 4 lines
drivers/mtd/nand/hisi_nand.c new file +4
-0+int (*send_cmd_erase)(struct hinfc_host *host); +int (*send_cmd_readid)(struct hinfc_host *host); +int (*send_cmd_reset)(struct hinfc_host *host,int chipselect); +};Why do you need function pointers here? The current version of the driver you posted always assigns these to the same functions, so it would be more efficient to just call those directly.
Quoted 4 lines
I agree with you.
This feature was originally designed to support a variety version of NAND controllers. But in fact, this feature is not used now.
I will move them out the host, thanks for your opinion!
Re: [PATCH 2/3] mtd: hisilicon: add a new nand controller driver for hisilicon hip04 Soc
In reply to Arnd BergmannQuoted 11 lines · Arnd Bergmann
Overall a very nice driver. I didn't find any real bugs, but a few things that could be changed for readability and micro-optimizations:
drivers/mtd/nand/hisi_nand.c line 137
Quoted 3 lines · On Monday 30 June 2014 16:03:28 Zhou Wang wrote:
drivers/mtd/nand/hisi_nand.c new file +3
-0+#define hinfc_read (_host, _reg) readl(_host->iobase + (_reg)) +#define hinfc_write (_host, _value, _reg)\ + writel((_value), _host->iobase + (_reg))I'd recommend making these inline functions rather than macros.
I will change above macros to inline functions, thanks.
Quoted 8 lines
drivers/mtd/nand/hisi_nand.c line 141
Quoted 3 lines
drivers/mtd/nand/hisi_nand.c new file +3
-0+struct hinfc_host { +struct nand_chip *chip; +struct mtd_info *mtd;I notice that you allocate the
nand_chipandmtd_infotogether with thehinfc_hostand then assign these pointers. A preferred method is normally to just embed the structures in this case:
Quoted 7 lines
struct hinfc_host { struct nand_chip chip; struct mtd_info mtd;so you avoid the pointer overhead, and can go back from these two structures to the
hinfc_hostusingcontainer_of().
It is better to embed chip and mtd in host, I will change this, thanks.
Quoted 33 lines
Quoted 13 lines
drivers/mtd/nand/hisi_nand.c new file +13
-0+struct device *dev; +void __iomem *iobase; +struct completion cmd_complete; +unsigned int offset; +unsigned int command; +int chipselect; +unsigned int addr_cycle; +unsigned int addr_value[2 ]; +unsigned int cache_addr_value[2 ]; +char *buffer; +dma_addr_t dma_buffer; +dma_addr_t dma_oob; +int version;drivers/mtd/nand/hisi_nand.c line 164
Quoted 10 lines
drivers/mtd/nand/hisi_nand.c new file +10
-0+unsigned int ecc_bits; +unsigned int irq_status;/* interrupt status */ + +int (*send_cmd_pageprog)(struct hinfc_host *host); +int (*send_cmd_status)(struct hinfc_host *host); +int (*send_cmd_readstart)(struct hinfc_host *host); +int (*send_cmd_erase)(struct hinfc_host *host); +int (*send_cmd_readid)(struct hinfc_host *host); +int (*send_cmd_reset)(struct hinfc_host *host,int chipselect); +};Why do you need function pointers here? The current version of the driver you posted always assigns these to the same functions, so it would be more efficient to just call those directly.
If you plan to add another variant later that uses a different set of functions here, you can add the function pointers then, in a separate patch. Also, a common style element is to have a separate constant structure with the function pointers:
Quoted 9 lines
const struct hinfc_host_ops ops = { .send_cmd_pageprog = hisi_nfc_send_cmd_pageprog, ... };if you actually end up needing function pointers. That simplifies the code a bit and is slightly more robust to attacks overwriting the function pointers.
I will move above function pointers out of host and directly call the functions, thanks for your good comment.
Quoted 28 lines
Quoted 14 lines
drivers/mtd/nand/hisi_nand.c new file +14
-0+ +void wait_controller_finished (struct hinfc_host *host) +{ +unsigned long timeout = jiffies +HINFC504_NFC_TIMEOUT ; +int val; + +while (time_before (jiffies, timeout)) { + val =hinfc_read (host,HINFC504_STATUS ); +if (host->command ==NAND_CMD_ERASE2 ) { +/* nfc is ready */ +while (!(val &HINFC504_READY )) { +usleep_range (500 ,1000 ); + val =hinfc_read (host,HINFC504_STATUS ); + }drivers/mtd/nand/hisi_nand.c line 188
Quoted 10 lines
drivers/mtd/nand/hisi_nand.c new file +10
-0+return ; + }else { +if (val &HINFC504_READY ) +return ; + } + } + +/* wait cmd timeout */ +dev_err (host->dev,"Wait NAND controller exec cmd timeout.\n" ); +}Since the timeout is much bigger than the wait time here, I guess you can use a wider range for the
usleep_range(), e.g.
Quoted 6 lines
usleep_range(500, 50000);which is nicer to other tasks. You will normally be woken up much earlier.
Arnd
As I know that the operating time of NAND flash erasure is about ms-level, so I set sleep time as usleep_range(500, 1000) here. And the timeout means that relative operations don't finish in this time, so maybe there is something wrong with the operations. In normal situation, after detecting the operation finished, the above function will return before timeout arriving.
Re: [PATCH 2/3] mtd: hisilicon: add a new nand controller driver for hisilicon hip04 Soc
In reply to Zhou WangQuoted 235 lines · Zhou Wang
Signed-off-by Zhou Wang <[email protected]>--- drivers/mtd/nand/Kconfig | 5 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/hisi_nand.c | 847 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 853 insertions(+)create mode 100644
drivers/mtd/nand/hisi_nand.cdrivers/mtd/nand/Kconfig +5
-0@@ -510,4 +510,9 @@ config MTD_NAND_XWAY Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached to the External Bus Unit (EBU). +config MTD_NAND_HISI + tristate "Support for NAND controller on Hisilicon SoC" + help + Enables support for NAND controller on Hisilicon SoC. + endif # MTD_NANDdrivers/mtd/nand/Makefile +1
-0@@ -49,5 +49,6 @@ obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/ obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/ +obj-$(CONFIG_MTD_NAND_HISI) += hisi_nand.o nand-objs := nand_base.o nand_bbt.odrivers/mtd/nand/hisi_nand.c new file +196
-0@@ -0,0 +1,847 @@ +/* +* Hisilicon NAND Flash controller driver +* +* Copyright ? 2012-2014 HiSilicon Technologies Co., Ltd. +* http://www.hisilicon.com +* +* Author: Zhou Wang <[email protected]> +* The initial developer of the original code is Zhiyong Cai +* <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ +#include <linux/of.h> +#include <linux/of_mtd.h> +#include <linux/mtd/mtd.h> +#include <linux/sizes.h> +#include <linux/clk.h> +#include <linux/slab.h> +#include <linux/module.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/mtd/nand.h> +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> +#include <linux/mtd/partitions.h> + +#define HINFC504_MAX_CHIP (4) +#define HINFC504_W_LATCH (5) +#define HINFC504_R_LATCH (7) +#define HINFC504_RW_LATCH (3) + +#define HINFC504_NFC_TIMEOUT (2 * HZ) +#define HINFC504_NFC_DMA_TIMEOUT (5 * HZ) +#define HINFC504_CHIP_DELAY (25) + +#define HINFC504_REG_BASE_ADDRESS_LEN (0x100) +#define HINFC504_BUFFER_BASE_ADDRESS_LEN (2048 + 128) + +#define HINFC504_ADDR_CYCLE_MASK 0x4 + +#define HINFC504_CON 0x00 +#define HINFC504_CON_OP_MODE_NORMAL (1U << 0) +#define HINFC504_CON_PAGEISZE_SHIFT (1) +#define HINFC504_CON_PAGESIZE_MASK (0x07) +#define HINFC504_CON_BUS_WIDTH (1U << 4) +#define HINFC504_CON_READY_BUSY_SEL (1U << 8) +#define HINFC504_CON_ECCTYPE_SHIFT (9) +#define HINFC504_CON_ECCTYPE_MASK (0x07) + +#define HINFC504_PWIDTH 0x04 +#define SET_HINFC504_PWIDTH (_w_lcnt, _r_lcnt, _rw_hcnt) \ + ((_w_lcnt) | (((_r_lcnt) & 0x0F) << 4) | (((_rw_hcnt) & 0x0F) << 8)) + +#define HINFC504_CMD 0x0C +#define HINFC504_ADDRL 0x10 +#define HINFC504_ADDRH 0x14 +#define HINFC504_DATA_NUM 0x18 + +#define HINFC504_OP 0x1C +#define HINFC504_OP_READ_DATA_EN (1U << 1) +#define HINFC504_OP_WAIT_READY_EN (1U << 2) +#define HINFC504_OP_CMD2_EN (1U << 3) +#define HINFC504_OP_WRITE_DATA_EN (1U << 4) +#define HINFC504_OP_ADDR_EN (1U << 5) +#define HINFC504_OP_CMD1_EN (1U << 6) +#define HINFC504_OP_NF_CS_SHIFT (7) +#define HINFC504_OP_NF_CS_MASK (3) +#define HINFC504_OP_ADDR_CYCLE_SHIFT (9) +#define HINFC504_OP_ADDR_CYCLE_MASK (7) + +#define HINFC504_STATUS 0x20 +#define HINFC504_READY (1U << 0) + +#define HINFC504_INTEN 0x24 +#define HINFC504_INTEN_DMA (1U << 9) +#define HINFC504_INTEN_UE (1U << 6) +#define HINFC504_INTEN_CE (1U << 5) + +#define HINFC504_INTS 0x28 +#define HINFC504_INTS_DMA (1U << 9) +#define HINFC504_INTS_UE (1U << 6) +#define HINFC504_INTS_CE (1U << 5) + +#define HINFC504_INTCLR 0x2C +#define HINFC504_INTCLR_DMA (1U << 9) +#define HINFC504_INTCLR_UE (1U << 6) +#define HINFC504_INTCLR_CE (1U << 5) + +#define HINFC504_ECC_STATUS 0x5C +#define HINFC504_ECC_1_BIT_SHIFT 16 +#define HINFC504_ECC_16_BIT_SHIFT 12 + +#define HINFC504_DMA_CTRL 0x60 +#define HINFC504_DMA_CTRL_DMA_START (1U << 0) +#define HINFC504_DMA_CTRL_WE (1U << 1) +#define HINFC504_DMA_CTRL_DATA_AREA_EN (1U << 2) +#define HINFC504_DMA_CTRL_OOB_AREA_EN (1U << 3) +#define HINFC504_DMA_CTRL_BURST4_EN (1U << 4) +#define HINFC504_DMA_CTRL_BURST8_EN (1U << 5) +#define HINFC504_DMA_CTRL_BURST16_EN (1U << 6) +#define HINFC504_DMA_CTRL_ADDR_NUM_SHIFT (7) +#define HINFC504_DMA_CTRL_ADDR_NUM_MASK (1) +#define HINFC504_DMA_CTRL_CS_SHIFT (8) +#define HINFC504_DMA_CTRL_CS_MASK (0x03) + +#define HINFC504_DMA_ADDR_DATA 0x64 +#define HINFC504_DMA_ADDR_OOB 0x68 + +#define HINFC504_DMA_LEN 0x6C +#define HINFC504_DMA_LEN_OOB_SHIFT (16) +#define HINFC504_DMA_LEN_OOB_MASK (0xFFF) + +#define HINFC504_DMA_PARA 0x70 +#define HINFC504_DMA_PARA_DATA_RW_EN (1U << 0) +#define HINFC504_DMA_PARA_OOB_RW_EN (1U << 1) +#define HINFC504_DMA_PARA_DATA_EDC_EN (1U << 2) +#define HINFC504_DMA_PARA_OOB_EDC_EN (1U << 3) +#define HINFC504_DMA_PARA_DATA_ECC_EN (1U << 4) +#define HINFC504_DMA_PARA_OOB_ECC_EN (1U << 5) + +#define HINFC_VERSION 0x74 +#define HINFC504_LOG_READ_ADDR 0x7C +#define HINFC504_LOG_READ_LEN 0x80 + +#define HINFC504_NANDINFO_LEN 0x10 + +#define hinfc_read (_host, _reg) readl(_host->iobase + (_reg)) +#define hinfc_write (_host, _value, _reg)\ + writel((_value), _host->iobase + (_reg)) + +struct hinfc_host { +struct nand_chip *chip; +struct mtd_info *mtd; +struct device *dev; +void __iomem *iobase; +struct completion cmd_complete; +unsigned int offset; +unsigned int command; +int chipselect; +unsigned int addr_cycle; +unsigned int addr_value[2 ]; +unsigned int cache_addr_value[2 ]; +char *buffer; +dma_addr_t dma_buffer; +dma_addr_t dma_oob; +int version; +unsigned int ecc_bits; +unsigned int irq_status;/* interrupt status */ + +int (*send_cmd_pageprog)(struct hinfc_host *host); +int (*send_cmd_status)(struct hinfc_host *host); +int (*send_cmd_readstart)(struct hinfc_host *host); +int (*send_cmd_erase)(struct hinfc_host *host); +int (*send_cmd_readid)(struct hinfc_host *host); +int (*send_cmd_reset)(struct hinfc_host *host,int chipselect); +}; + +void wait_controller_finished (struct hinfc_host *host) +{ +unsigned long timeout = jiffies +HINFC504_NFC_TIMEOUT ; +int val; + +while (time_before (jiffies, timeout)) { + val =hinfc_read (host,HINFC504_STATUS ); +if (host->command ==NAND_CMD_ERASE2 ) { +/* nfc is ready */ +while (!(val &HINFC504_READY )) { +usleep_range (500 ,1000 ); + val =hinfc_read (host,HINFC504_STATUS ); + } +return ; + }else { +if (val &HINFC504_READY ) +return ; + } + } + +/* wait cmd timeout */ +dev_err (host->dev,"Wait NAND controller exec cmd timeout.\n" ); +} + +static void hisi_nfc_dma_transfer (struct hinfc_host *host,int todev) +{ +struct mtd_info *mtd = host->mtd; +struct nand_chip *chip = mtd->priv; +unsigned long val; +int ret; +
drivers/mtd/nand/hisi_nand.c line 206
Quoted 10 lines
drivers/mtd/nand/hisi_nand.c new file +10
-0+hinfc_write (host, host->dma_buffer,HINFC504_DMA_ADDR_DATA ); +hinfc_write (host, host->dma_oob,HINFC504_DMA_ADDR_OOB ); + +if (chip->ecc.mode ==NAND_ECC_NONE ) { +hinfc_write (host, ((mtd->oobsize &HINFC504_DMA_LEN_OOB_MASK ) + <<HINFC504_DMA_LEN_OOB_SHIFT ),HINFC504_DMA_LEN ); + +hinfc_write (host,HINFC504_DMA_PARA_DATA_RW_EN + |HINFC504_DMA_PARA_OOB_RW_EN ,HINFC504_DMA_PARA ); + }else
Add {} for else also./scripts/checkpatch.pl.
Signature · 2 lines
Regards, Ivan Khoronzhuk
Re: [PATCH 2/3] mtd: hisilicon: add a new nand controller driver for hisilicon hip04 Soc
Quoted 242 lines · Ivan Khoronzhuk
Quoted 240 lines · Zhou Wang
Signed-off-by Zhou Wang <[email protected]>--- drivers/mtd/nand/Kconfig | 5 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/hisi_nand.c | 847 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 853 insertions(+)create mode 100644
drivers/mtd/nand/hisi_nand.cdrivers/mtd/nand/Kconfig +0
-0@@ -510,4 +510,9 @@ config MTD_NAND_XWAY Enables support for NAND Flash chips on Lantiq XWAY SoCs. NANDis attached
to the External Bus Unit (EBU).drivers/mtd/nand/Kconfig +5
-0+config MTD_NAND_HISI + tristate "Support for NAND controller on Hisilicon SoC" + help + Enables support for NAND controller on Hisilicon SoC. + endif # MTD_NANDdrivers/mtd/nand/Makefile +1
-0@@ -49,5 +49,6 @@ obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/ obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/ +obj-$(CONFIG_MTD_NAND_HISI) += hisi_nand.o nand-objs := nand_base.o nand_bbt.odrivers/mtd/nand/hisi_nand.c new file +201
-0@@ -0,0 +1,847 @@ +/* +* Hisilicon NAND Flash controller driver +* +* Copyright ? 2012-2014 HiSilicon Technologies Co., Ltd. +* http://www.hisilicon.com +* +* Author: Zhou Wang <[email protected]> +* The initial developer of the original code is Zhiyong Cai +* <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ +#include <linux/of.h> +#include <linux/of_mtd.h> +#include <linux/mtd/mtd.h> +#include <linux/sizes.h> +#include <linux/clk.h> +#include <linux/slab.h> +#include <linux/module.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/mtd/nand.h> +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> +#include <linux/mtd/partitions.h> + +#define HINFC504_MAX_CHIP (4) +#define HINFC504_W_LATCH (5) +#define HINFC504_R_LATCH (7) +#define HINFC504_RW_LATCH (3) + +#define HINFC504_NFC_TIMEOUT (2 * HZ) +#define HINFC504_NFC_DMA_TIMEOUT (5 * HZ) +#define HINFC504_CHIP_DELAY (25) + +#define HINFC504_REG_BASE_ADDRESS_LEN (0x100) +#define HINFC504_BUFFER_BASE_ADDRESS_LEN (2048 + 128) + +#define HINFC504_ADDR_CYCLE_MASK 0x4 + +#define HINFC504_CON 0x00 +#define HINFC504_CON_OP_MODE_NORMAL (1U << 0) +#define HINFC504_CON_PAGEISZE_SHIFT (1) +#define HINFC504_CON_PAGESIZE_MASK (0x07) +#define HINFC504_CON_BUS_WIDTH (1U << 4) +#define HINFC504_CON_READY_BUSY_SEL (1U << 8) +#define HINFC504_CON_ECCTYPE_SHIFT (9) +#define HINFC504_CON_ECCTYPE_MASK (0x07) + +#define HINFC504_PWIDTH 0x04 +#define SET_HINFC504_PWIDTH (_w_lcnt, _r_lcnt, _rw_hcnt) \ + ((_w_lcnt) | (((_r_lcnt) & 0x0F) << 4) | (((_rw_hcnt) & 0x0F) << 8)) + +#define HINFC504_CMD 0x0C +#define HINFC504_ADDRL 0x10 +#define HINFC504_ADDRH 0x14 +#define HINFC504_DATA_NUM 0x18 + +#define HINFC504_OP 0x1C +#define HINFC504_OP_READ_DATA_EN (1U << 1) +#define HINFC504_OP_WAIT_READY_EN (1U << 2) +#define HINFC504_OP_CMD2_EN (1U << 3) +#define HINFC504_OP_WRITE_DATA_EN (1U << 4) +#define HINFC504_OP_ADDR_EN (1U << 5) +#define HINFC504_OP_CMD1_EN (1U << 6) +#define HINFC504_OP_NF_CS_SHIFT (7) +#define HINFC504_OP_NF_CS_MASK (3) +#define HINFC504_OP_ADDR_CYCLE_SHIFT (9) +#define HINFC504_OP_ADDR_CYCLE_MASK (7) + +#define HINFC504_STATUS 0x20 +#define HINFC504_READY (1U << 0) + +#define HINFC504_INTEN 0x24 +#define HINFC504_INTEN_DMA (1U << 9) +#define HINFC504_INTEN_UE (1U << 6) +#define HINFC504_INTEN_CE (1U << 5) + +#define HINFC504_INTS 0x28 +#define HINFC504_INTS_DMA (1U << 9) +#define HINFC504_INTS_UE (1U << 6) +#define HINFC504_INTS_CE (1U << 5) + +#define HINFC504_INTCLR 0x2C +#define HINFC504_INTCLR_DMA (1U << 9) +#define HINFC504_INTCLR_UE (1U << 6) +#define HINFC504_INTCLR_CE (1U << 5) + +#define HINFC504_ECC_STATUS 0x5C +#define HINFC504_ECC_1_BIT_SHIFT 16 +#define HINFC504_ECC_16_BIT_SHIFT 12 + +#define HINFC504_DMA_CTRL 0x60 +#define HINFC504_DMA_CTRL_DMA_START (1U << 0) +#define HINFC504_DMA_CTRL_WE (1U << 1) +#define HINFC504_DMA_CTRL_DATA_AREA_EN (1U << 2) +#define HINFC504_DMA_CTRL_OOB_AREA_EN (1U << 3) +#define HINFC504_DMA_CTRL_BURST4_EN (1U << 4) +#define HINFC504_DMA_CTRL_BURST8_EN (1U << 5) +#define HINFC504_DMA_CTRL_BURST16_EN (1U << 6) +#define HINFC504_DMA_CTRL_ADDR_NUM_SHIFT (7) +#define HINFC504_DMA_CTRL_ADDR_NUM_MASK (1) +#define HINFC504_DMA_CTRL_CS_SHIFT (8) +#define HINFC504_DMA_CTRL_CS_MASK (0x03) + +#define HINFC504_DMA_ADDR_DATA 0x64 +#define HINFC504_DMA_ADDR_OOB 0x68 + +#define HINFC504_DMA_LEN 0x6C +#define HINFC504_DMA_LEN_OOB_SHIFT (16) +#define HINFC504_DMA_LEN_OOB_MASK (0xFFF) + +#define HINFC504_DMA_PARA 0x70 +#define HINFC504_DMA_PARA_DATA_RW_EN (1U << 0) +#define HINFC504_DMA_PARA_OOB_RW_EN (1U << 1) +#define HINFC504_DMA_PARA_DATA_EDC_EN (1U << 2) +#define HINFC504_DMA_PARA_OOB_EDC_EN (1U << 3) +#define HINFC504_DMA_PARA_DATA_ECC_EN (1U << 4) +#define HINFC504_DMA_PARA_OOB_ECC_EN (1U << 5) + +#define HINFC_VERSION 0x74 +#define HINFC504_LOG_READ_ADDR 0x7C +#define HINFC504_LOG_READ_LEN 0x80 + +#define HINFC504_NANDINFO_LEN 0x10 + +#define hinfc_read (_host, _reg) readl(_host->iobase + (_reg)) +#define hinfc_write (_host, _value, _reg)\ + writel((_value), _host->iobase + (_reg)) + +struct hinfc_host { +struct nand_chip *chip; +struct mtd_info *mtd; +struct device *dev; +void __iomem *iobase; +struct completion cmd_complete; +unsigned int offset; +unsigned int command; +int chipselect; +unsigned int addr_cycle; +unsigned int addr_value[2 ]; +unsigned int cache_addr_value[2 ]; +char *buffer; +dma_addr_t dma_buffer; +dma_addr_t dma_oob; +int version; +unsigned int ecc_bits; +unsigned int irq_status;/* interrupt status */ + +int (*send_cmd_pageprog)(struct hinfc_host *host); +int (*send_cmd_status)(struct hinfc_host *host); +int (*send_cmd_readstart)(struct hinfc_host *host); +int (*send_cmd_erase)(struct hinfc_host *host); +int (*send_cmd_readid)(struct hinfc_host *host); +int (*send_cmd_reset)(struct hinfc_host *host,int chipselect); +}; + +void wait_controller_finished (struct hinfc_host *host) +{ +unsigned long timeout = jiffies +HINFC504_NFC_TIMEOUT ; +int val; + +while (time_before (jiffies, timeout)) { + val =hinfc_read (host,HINFC504_STATUS ); +if (host->command ==NAND_CMD_ERASE2 ) { +/* nfc is ready */ +while (!(val &HINFC504_READY )) { +usleep_range (500 ,1000 ); + val =hinfc_read (host,HINFC504_STATUS ); + } +return ; + }else { +if (val &HINFC504_READY ) +return ; + } + } + +/* wait cmd timeout */ +dev_err (host->dev,"Wait NAND controller exec cmd timeout.\n" ); +} + +static void hisi_nfc_dma_transfer (struct hinfc_host *host,int todev) +{ +struct mtd_info *mtd = host->mtd; +struct nand_chip *chip = mtd->priv; +unsigned long val; +int ret; + +hinfc_write (host, host->dma_buffer,HINFC504_DMA_ADDR_DATA ); +hinfc_write (host, host->dma_oob,HINFC504_DMA_ADDR_OOB ); + +if (chip->ecc.mode ==NAND_ECC_NONE ) { + hinfc_write(host, ((mtd->oobsize & HINFC504_DMA_LEN_OOB_MASK)
Quoted 9 lines
drivers/mtd/nand/hisi_nand.c line 206
Quoted 5 lines
drivers/mtd/nand/hisi_nand.c new file +5
-0+ << HINFC504_DMA_LEN_OOB_SHIFT), HINFC504_DMA_LEN); + +hinfc_write (host,HINFC504_DMA_PARA_DATA_RW_EN + |HINFC504_DMA_PARA_OOB_RW_EN ,HINFC504_DMA_PARA ); + }else Add {} for else also
./scripts/checkpatch.pl.
ok, I will add them, thanks.
PATCH 2/3 mtd: hisilicon: add a new nand controller driver for hisilicon hip04 Soc
In reply to Zhou WangQuoted 7 lines · Zhou Wang
Signed-off-by Zhou Wang <[email protected]>--- drivers/mtd/nand/Kconfig | 5 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/hisi_nand.c | 847 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 853 insertions(+) create mode 100644 drivers/mtd/nand/hisi_nand.c
[...]
Quoted 26 lines
drivers/mtd/nand/hisi_nand.c new file +26
-0+struct hinfc_host { +struct nand_chip *chip; +struct mtd_info *mtd; +struct device *dev; +void __iomem *iobase; +struct completion cmd_complete; +unsigned int offset; +unsigned int command; +int chipselect; +unsigned int addr_cycle; +unsigned int addr_value[2 ]; +unsigned int cache_addr_value[2 ]; +char *buffer; +dma_addr_t dma_buffer; +dma_addr_t dma_oob; +int version; +unsigned int ecc_bits; +unsigned int irq_status;/* interrupt status */ + +int (*send_cmd_pageprog)(struct hinfc_host *host); +int (*send_cmd_status)(struct hinfc_host *host); +int (*send_cmd_readstart)(struct hinfc_host *host); +int (*send_cmd_erase)(struct hinfc_host *host); +int (*send_cmd_readid)(struct hinfc_host *host); +int (*send_cmd_reset)(struct hinfc_host *host,int chipselect); +};
[...]
Quoted 10 lines
drivers/mtd/nand/hisi_nand.c new file +10
-0+static int hisi_nfc_probe (struct platform_device *pdev) +{ +int ret =0 , irq, buswidth, flag, max_chips =HINFC504_MAX_CHIP ; +struct device *dev = &pdev->dev; +struct hinfc_host *host; +struct nand_chip *chip; +struct mtd_info *mtd; +struct resource *res; +struct device_node *np = dev->of_node; +struct mtd_part_parser_data ppdata;
drivers/mtd/nand/hisi_nand.c line 671
Quoted 10 lines
drivers/mtd/nand/hisi_nand.c new file +10
-0+ + host =devm_kzalloc (dev,sizeof (*host) +sizeof (*chip) +sizeof (*mtd), +GFP_KERNEL ); +if (!host) +return -ENOMEM ; + host->dev = dev; + +platform_set_drvdata (pdev, host); + chip = (struct nand_chip *)&host[1 ]; + mtd = (struct mtd_info *)&chip[1 ];
Why not embed the whole struct rather than pointers? Then you can allocate just the host and extract pointers to the chip and mtd sub structures.
Thanks,
Mark.
PATCH 2/3 mtd: hisilicon: add a new nand controller driver for hisilicon hip04 Soc
Quoted 65 lines · Mark Rutland
Quoted 7 lines · Zhou Wang
Signed-off-by Zhou Wang <[email protected]>--- drivers/mtd/nand/Kconfig | 5 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/hisi_nand.c | 847 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 853 insertions(+)create mode 100644
drivers/mtd/nand/hisi_nand.c[...]
Quoted 26 lines
drivers/mtd/nand/hisi_nand.c new file +26
-0+struct hinfc_host { +struct nand_chip *chip; +struct mtd_info *mtd; +struct device *dev; +void __iomem *iobase; +struct completion cmd_complete; +unsigned int offset; +unsigned int command; +int chipselect; +unsigned int addr_cycle; +unsigned int addr_value[2 ]; +unsigned int cache_addr_value[2 ]; +char *buffer; +dma_addr_t dma_buffer; +dma_addr_t dma_oob; +int version; +unsigned int ecc_bits; +unsigned int irq_status;/* interrupt status */ + +int (*send_cmd_pageprog)(struct hinfc_host *host); +int (*send_cmd_status)(struct hinfc_host *host); +int (*send_cmd_readstart)(struct hinfc_host *host); +int (*send_cmd_erase)(struct hinfc_host *host); +int (*send_cmd_readid)(struct hinfc_host *host); +int (*send_cmd_reset)(struct hinfc_host *host,int chipselect); +};[...]
Quoted 10 lines
drivers/mtd/nand/hisi_nand.c new file +10
-0+static int hisi_nfc_probe (struct platform_device *pdev) +{ +int ret =0 , irq, buswidth, flag, max_chips =HINFC504_MAX_CHIP ; +struct device *dev = &pdev->dev; +struct hinfc_host *host; +struct nand_chip *chip; +struct mtd_info *mtd; +struct resource *res; +struct device_node *np = dev->of_node; +struct mtd_part_parser_data ppdata;drivers/mtd/nand/hisi_nand.c line 671
Quoted 10 lines
drivers/mtd/nand/hisi_nand.c new file +10
-0+ + host =devm_kzalloc (dev,sizeof (*host) +sizeof (*chip) +sizeof (*mtd), +GFP_KERNEL ); +if (!host) +return -ENOMEM ; + host->dev = dev; + +platform_set_drvdata (pdev, host); + chip = (struct nand_chip *)&host[1 ]; + mtd = (struct mtd_info *)&chip[1 ];Why not embed the whole struct rather than pointers? Then you can allocate just the host and extract pointers to the chip and mtd sub structures.
Quoted 3 lines
Thanks,
Mark.
I will change this as your comment, thanks.
Quoted 5 lines
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PATCH 3/3 mtd: hisilicon: add device tree binding documentation
In reply to Zhou Wang--- .../devicetree/bindings/mtd/hisi-nand.txt | 38 ++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/hisi-nand.txt
Documentation/devicetree/bindings/mtd/hisi-nand.txt new file +38 -0
@@ -0,0 +1,38 @@ +Hisilicon Hip04 Soc NAND controller DT binding + +Required properties: +- compatible: Should be "hisilicon,nfc504". +- reg: Contain registers location and length for reg and data. +- interrupts: Interrupt number for nfc. +- nand-bus-width: See nand.txt. +- nand-ecc-mode: See nand.txt. +- hisi,nand-ecc-bits: ECC bits type support. + <0>: none ecc + <1>: Can correct 1bit per 512byte. + <6>: Can correct 16bits per 1K byte. +- #address-cells: partition address. +- #size-cells: partition size. + +Flash chip may optionally contain additional sub-nodes describing partitions of +the address space. See partition.txt for more detail. + +Example: + + nand: nand at 4020000 { + compatible = "hisilicon,nfc504"; + reg = <0x4020000 0x10000>, <0x5000000 0x1000>; + interrupts = <0 379 4>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + hisi,nand-ecc-bits = <1>; + #address-cells = <1>; + #size-cells = <1>; + + partition at 0 { + label = "nand_text"; + reg = <0x00000000 0x00400000>; + }; + + ... + + };
Signature · 1 line
1.7.9.5
PATCH 3/3 mtd: hisilicon: add device tree binding documentation
Quoted 12 lines · Zhou Wang
Signed-off-by Zhou Wang <[email protected]>--- .../devicetree/bindings/mtd/hisi-nand.txt | 38 ++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/hisi-nand.txtDocumentation/devicetree/bindings/mtd/hisi-nand.txt new file +0
-0
Documentation/devicetree/bindings/mtd/hisi-nand.txt line 5
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Documentation/devicetree/bindings/mtd/hisi-nand.txt new file +5
-0@@ -0,0 +1,38 @@ +Hisilicon Hip04 Soc NAND controller DT binding + +Required properties: +- compatible: Should be "hisilicon,nfc504". +- reg: Contain registers location and length for reg and data.
I'm not sure I follow. The example below has two reg entries. What does each entry represent, and what does the presence of multiple entries mean?
Documentation/devicetree/bindings/mtd/hisi-nand.txt line 6
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Documentation/devicetree/bindings/mtd/hisi-nand.txt new file +1
-0+- interrupts: Interrupt number for nfc.
Just the one?
Documentation/devicetree/bindings/mtd/hisi-nand.txt line 12
Quoted 6 lines
Documentation/devicetree/bindings/mtd/hisi-nand.txt new file +6
-0+- nand-bus-width: See nand.txt. +- nand-ecc-mode: See nand.txt. +- hisi,nand-ecc-bits: ECC bits type support. + <0>: none ecc + <1>: Can correct 1bit per 512byte. + <6>: Can correct 16bits per 1K byte.
Is this an enumeration, or a number of bits?
Documentation/devicetree/bindings/mtd/hisi-nand.txt line 14
Quoted 2 lines
Documentation/devicetree/bindings/mtd/hisi-nand.txt new file +2
-0+- #address-cells: partition address. +- #size-cells: partition size.
Are these only allowed to be 1 cell, or can they be more?
Thanks,
Mark.
Quoted 28 lines
Documentation/devicetree/bindings/mtd/hisi-nand.txt new file +24
-0+ +Flash chip may optionally contain additional sub-nodes describing partitions of +the address space. See partition.txt for more detail. + +Example: + + nand: nand at 4020000 { + compatible = "hisilicon,nfc504"; + reg = <0x4020000 0x10000>, <0x5000000 0x1000>; + interrupts = <0 379 4>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + hisi,nand-ecc-bits = <1>; + #address-cells = <1>; + #size-cells = <1>; + + partition at 0 { + label = "nand_text"; + reg = <0x00000000 0x00400000>; + }; + + ... + + };Signature · 1 line
1.7.9.5
PATCH 3/3 mtd: hisilicon: add device tree binding documentation
Quoted 7 lines · Mark Rutland
Quoted 6 lines · Zhou Wang
Signed-off-by Zhou Wang <[email protected]>--- .../devicetree/bindings/mtd/hisi-nand.txt | 38 ++++++++++++++++++++ 1 file changed, 38 insertions(+)create mode 100644
Documentation/devicetree/bindings/mtd/hisi-nand.txt
Quoted 16 lines
Documentation/devicetree/bindings/mtd/hisi-nand.txt line 5
Quoted 11 lines
Documentation/devicetree/bindings/mtd/hisi-nand.txt new file +5
-0@@ -0,0 +1,38 @@ +Hisilicon Hip04 Soc NAND controller DT binding + +Required properties: +- compatible: Should be "hisilicon,nfc504". +- reg: Contain registers location and length for reg and data.I'm not sure I follow. The example below has two reg entries. What does each entry represent, and what does the presence of multiple entries mean?
Maybe I could not express it clearly here. The first reg entry represents the basic address of registers of NAND controller, and the second represents the basic address of buffer of NAND controller.
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Documentation/devicetree/bindings/mtd/hisi-nand.txt line 6
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Documentation/devicetree/bindings/mtd/hisi-nand.txt new file +1
-0+- interrupts: Interrupt number for nfc.Just the one?
Yes, Just one interrupt number. And there is an interrupt relative register in the NAND controller, we can get information about interrupt from the register after an interrupt triggered.
Quoted 9 lines
Documentation/devicetree/bindings/mtd/hisi-nand.txt line 12
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Documentation/devicetree/bindings/mtd/hisi-nand.txt new file +6
-0+- nand-bus-width: See nand.txt. +- nand-ecc-mode: See nand.txt. +- hisi,nand-ecc-bits: ECC bits type support. + <0>: none ecc + <1>: Can correct 1bit per 512byte. + <6>: Can correct 16bits per 1K byte.Is this an enumeration, or a number of bits?
This is an enumeration which is just relative register configure, so we can directly use it to configure relative register bits in driver.
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Documentation/devicetree/bindings/mtd/hisi-nand.txt line 14
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Documentation/devicetree/bindings/mtd/hisi-nand.txt new file +2
-0+- #address-cells: partition address. +- #size-cells: partition size.Are these only allowed to be 1 cell, or can they be more?
Thanks,
Mark.
These are only allowed to be 1 cell. Address-cells represents basic address of a partition, and size-cells represents the size of a partition.
I will rewrite the unclear parts as your comments. Thanks for your comments.
-Zhou Wang
Quoted 34 lines
Quoted 25 lines
Documentation/devicetree/bindings/mtd/hisi-nand.txt new file +24
-1+ +Flash chip may optionally contain additional sub-nodes describing partitions of +the address space. See partition.txt for more detail. + +Example: + + nand: nand at 4020000 { + compatible = "hisilicon,nfc504"; + reg = <0x4020000 0x10000>, <0x5000000 0x1000>; + interrupts = <0 379 4>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + hisi,nand-ecc-bits = <1>; + #address-cells = <1>; + #size-cells = <1>; + + partition at 0 { + label = "nand_text"; + reg = <0x00000000 0x00400000>; + }; + + ... + + }; --Quoted 3 lines
1.7.9.5
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