arm64: mm: Make icache synchronisation logic huge page aware

The __sync_icache_dcache routine will only flush the dcache for the first page of a compound page, potentially leading to stale icache data residing further on in a hugetlb page.

This patch addresses this issue by taking into consideration the order of the page when flushing the dcache.

Reported-by Mark Brown <[email protected]>

Tested-by Mark Brown <[email protected]>

Signed-off-by Steve Capper <[email protected]>

---
 arch/arm64/mm/flush.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

arch/arm64/mm/flush.c +2 -1

index e4193e3..0d64089 100644
@@ -79,7 +79,8 @@ void __sync_icache_dcache(pte_t pte, unsigned long addr)
 		return;
 
 	if (!test_and_set_bit(PG_dcache_clean, &page->flags)) {
-		__flush_dcache_area(page_address(page), PAGE_SIZE);
+		__flush_dcache_area(page_address(page),
+				PAGE_SIZE << compound_order(page));
 		__flush_icache_all();
 	} else if (icache_is_aivivt()) {
 		__flush_icache_all();

Signature · 1 line

1.9.3