ARM: imx: Add Freescale LS1021A SoC and board support
Subsystems (5)
cover ARM: imx: Add Freescale LS1021A SoC and board support
This series contain the support for Freescale LS1021A CPU and LS1021A-QDS and LS1021A-TWR board.
The LS1021A SoC combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors and with a comprehensive enablement model focused on ease of programmability.
The LS1021A SoC shares IPs with i.MX family, Vybrid family and Freescale PowerPC platform.
For the detail information about LS1021A SoC, please refer to the RM doc.
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Jingchang Lu (5):
ARM: dts: Add SoC level device tree support for LS1021A
ARM: dts: Add initial LS1021A QDS board dts support
ARM: dts: Add initial LS1021A TWR board dts support
ARM: imx: Add initial support for Freescale LS1021A
ARM: imx: Add Freescale LS1021A SMP support
arch/arm/boot/dts/Makefile | 4 +- arch/arm/boot/dts/ls1021a-qds.dts | 380 ++++++++++++++++++++++++++++ arch/arm/boot/dts/ls1021a-twr.dts | 236 +++++++++++++++++ arch/arm/boot/dts/ls1021a.dtsi | 852 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/Kconfig | 17 ++ arch/arm/mach-imx/Makefile | 2 + arch/arm/mach-imx/common.h | 2 + arch/arm/mach-imx/headsmp.S | 11 + arch/arm/mach-imx/mach-ls1021a.c | 50 ++++ arch/arm/mach-imx/platsmp.c | 44 ++++ 10 files changed, 1597 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/ls1021a-qds.dts create mode 100755 arch/arm/boot/dts/ls1021a-twr.dts create mode 100644 arch/arm/boot/dts/ls1021a.dtsi create mode 100644 arch/arm/mach-imx/mach-ls1021a.c
PATCH 1/5 ARM: dts: Add SoC level device tree support for LS1021A
From: Jingchang Lu <[email protected]>
Add Freescale LS1021A SoC device tree support
--- arch/arm/boot/dts/ls1021a.dtsi | 852 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 852 insertions(+) create mode 100644 arch/arm/boot/dts/ls1021a.dtsi
arch/arm/boot/dts/ls1021a.dtsi new file +852 -0
@@ -0,0 +1,852 @@ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include "skeleton64.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "fsl,ls1021a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + serial4 = &lpuart4; + serial5 = &lpuart5; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + }; + + memory { + reg = <0x0 0x80000000 0x0 0x20000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu at 0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf00>; + }; + + cpu at 1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf01>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + gic: interrupt-controller at 1400000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1401000 0x0 0x1000>, + <0x0 0x1402000 0x0 0x1000>, + <0x0 0x1404000 0x0 0x2000>, + <0x0 0x1406000 0x0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + + }; + + tzasc: tzasc at 1500000 { + reg = <0x0 0x1500000 0x0 0x10000>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + ifc: ifc at 1530000 { + compatible = "fsl,ls1021a-ifc", "fsl,ifc", "simple-bus"; + reg = <0x0 0x1530000 0x0 0x10000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + }; + + dcfg: dcfg at 1ee0000 { + compatible = "fsl,ls1021a-dcfg"; + reg = <0x0 0x1ee0000 0x0 0x10000>; + }; + + qspi: quadspi at 1550000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-qspi"; + reg = <0x0 0x1550000 0x0 0x10000>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "qspi_en", "qspi"; + clocks = <&platform_clk 1>, <&platform_clk 1>; + big-endian; + amba-base = <0x40000000>; + status = "disabled"; + }; + + esdhc: esdhc at 1560000 { + compatible = "fsl,ls1021a-esdhc", "fsl,esdhc"; + reg = <0x0 0x1560000 0x0 0x10000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <0>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + big-endian; + bus-width = <4>; + status = "disabled"; + }; + + scfg: scfg at 1570000 { + compatible = "fsl,ls1021a-scfg"; + reg = <0x0 0x1570000 0x0 0x10000>; + }; + + crypto: crypto at 1700000 { + compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <4>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x1700000 0x0 0x100000>; + ranges = <0x0 0x0 0x1700000 0x100000>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + + sec_jr0: jr at 10000 { + compatible = "fsl,sec-v5.3-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr at 20000 { + compatible = "fsl,sec-v5.3-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr at 30000 { + compatible = "fsl,sec-v5.3-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr3: jr at 40000 { + compatible = "fsl,sec-v5.3-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + }; + + }; + + clockgen: clocking at 1ee1000 { + compatible = "fsl,ls1021a-clockgen"; + reg = <0x0 0x1ee1000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1ee1000 0x10000>; + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + cga_pll1: pll1 at 800 { + compatible = "fsl,qoriq-core-pll-2.0"; + #clock-cells = <1>; + reg = <0x800 0x10>; + clocks = <&sysclk>; + clock-output-names = "cga-pll1", "cga-pll1-div2", + "cga-pll1-div3", "cga-pll1-div4"; + }; + + cga_pll2: pll2 at 820 { + compatible = "fsl,qoriq-core-pll-2.0"; + #clock-cells = <1>; + reg = <0x820 0x10>; + clocks = <&sysclk>; + clock-output-names = "cga-pll2", "cga-pll2-div2", + "cga-pll2-div3", "cga-pll2-div4"; + }; + + platform_clk: pll at c00 { + compatible = "fsl,qoriq-core-pll-2.0"; + #clock-cells = <1>; + reg = <0xc00 0x10>; + clocks = <&sysclk>; + clock-output-names = "platform-clk", "platform-clk-div2"; + }; + + + cluster1_clk: clk0c0 at 0 { + compatible = "fsl,qoriq-core-mux-2.0"; + #clock-cells = <1>; + reg = <0x0 0x10>; + clock-names = "pll1cga", "pll1cga-div2"; + clocks = <&cga_pll1 0>, <&cga_pll1 2>; + clock-output-names = "cluster1-clk"; + + }; + + }; + + rcpm: rcpm at 1ee2000 { + compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1"; + reg = <0x0 0x1ee2000 0x0 0x10000>; + }; + + dspi0: dspi at 2100000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-dspi"; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dspi"; + clocks = <&platform_clk 1>; + spi-num-chipselects = <5>; + big-endian; + status = "disabled"; + }; + + dspi1: dspi at 2110000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-dspi"; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dspi"; + clocks = <&platform_clk 1>; + spi-num-chipselects = <5>; + big-endian; + status = "disabled"; + }; + + i2c0: i2c at 2180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-i2c"; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "i2c"; + clocks = <&platform_clk 1>; + status = "disabled"; + }; + + i2c1: i2c at 2190000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-i2c"; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "i2c"; + clocks = <&platform_clk 1>; + status = "disabled"; + }; + + i2c2: i2c at 21a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-i2c"; + reg = <0x0 0x21a0000 0x0 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "i2c"; + clocks = <&platform_clk 1>; + status = "disabled"; + }; + + duart0: serial at 21c0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0500 0x0 0x100>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <0>; + fifo-size = <8>; + status = "disabled"; + }; + + duart1: serial at 21c0600 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0600 0x0 0x100>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <0>; + fifo-size = <8>; + status = "disabled"; + }; + + duart2: serial at 21d0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21d0500 0x0 0x100>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <0>; + fifo-size = <8>; + status = "disabled"; + }; + + duart3: serial at 21d0600 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21d0600 0x0 0x100>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <0>; + fifo-size = <8>; + status = "disabled"; + }; + + gpio1: gpio at 2300000 { + compatible = "fsl,ls1021a-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio at 2310000 { + compatible = "fsl,ls1021a-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio at 2320000 { + compatible = "fsl,ls1021a-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio at 2330000 { + compatible = "fsl,ls1021a-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + uqe: uqe at 2400000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "qe"; + compatible = "fsl,qe"; + fsl,qe-num-riscs = <1>; + fsl,qe-num-snums = <28>; + + qeic: qeic at 80 { + compatible = "fsl,qe-ic"; + reg = <0x80 0x80>; + #address-cells = <0>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + < GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + }; + + ucc at 2000 { + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + }; + + ucc at 2200 { + cell-index = <3>; + reg = <0x2200 0x200>; + interrupts = <34>; + interrupt-parent = <&qeic>; + }; + + muram at 10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0x0 0x10000 0x6000>; + + data-only at 0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0x0 0x6000>; + }; + }; + }; + + lpuart0: serial at 2950000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2950000 0x0 0x1000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysclk>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart1: serial at 2960000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2960000 0x0 0x1000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial at 2970000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2970000 0x0 0x1000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart3: serial at 2980000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2980000 0x0 0x1000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart4: serial at 2990000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2990000 0x0 0x1000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial at 29a0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x29a0000 0x0 0x1000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + ftm0_1: ftm0_1 at 29d0000 { + compatible = "fsl,ftm-timer"; + reg = <0x0 0x29d0000 0x0 0x10000>, + <0x0 0x29e0000 0x0 0x10000>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ftm-evt", "ftm-src", + "ftm-evt-counter-en", "ftm-src-counter-en"; + clocks = <&platform_clk 1>, <&platform_clk 1>, + <&platform_clk 1>, <&platform_clk 1>; + big-endian; + status = "disabled"; + }; + + ftm2: ftm at 29f0000 { + reg = <0x0 0x29f0000 0x0 0x10000>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pwm3: ftm at 2a00000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2a00000 0x0 0x10000>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&platform_clk 1>, <&platform_clk 1>, + <&platform_clk 1>, <&platform_clk 1>; + big-endian; + status = "disabled"; + }; + + ftm4: ftm at 2a10000 { + reg = <0x0 0x2a10000 0x0 0x10000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + ftm5: ftm at 2a20000 { + reg = <0x0 0x2a20000 0x0 0x10000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pwm6: ftm at 2a30000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2a30000 0x0 0x10000>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&platform_clk 1>, <&platform_clk 1>, + <&platform_clk 1>, <&platform_clk 1>; + big-endian; + status = "disabled"; + }; + + pwm7: ftm at 2a40000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2a40000 0x0 0x10000>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&platform_clk 1>, <&platform_clk 1>, + <&platform_clk 1>, <&platform_clk 1>; + big-endian; + status = "disabled"; + }; + + wdog0: wdog at 2ad0000 { + compatible = "fsl,ls1021a-wdt", "fsl,imx21-wdt"; + reg = <0x0 0x2ad0000 0x0 0x10000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "wdog"; + big-endian; + }; + + sai2: sai at 2b60000 { + compatible = "fsl,vf610-sai"; + reg = <0x0 0x2b60000 0x0 0x10000>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "sai"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 45>, + <&edma0 1 44>; + big-endian-regs; + status = "disabled"; + }; + + edma0: edma at 2c00000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x0 0x2c00000 0x0 0x10000>, + <0x0 0x2c10000 0x0 0x10000>, + <0x0 0x2c20000 0x0 0x10000>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma-tx", "edma-err"; + dma-channels = <32>; + big-endian; + clock-names = "dmamux0", "dmamux1"; + clocks = <&platform_clk 1>, + <&platform_clk 1>; + }; + + dcu0: dcu at 2ce0000 { + compatible = "fsl,vf610-dcu"; + reg = <0x0 0x2ce000 0x0 0x10000>; + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "dcu"; + big-endian; + status = "disabled"; + }; + + mdio0: mdio at 2d24000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "mdio"; + compatible = "gianfar"; + reg = <0x0 0x2d24000 0x0 0x4000>; + tbi0: tbi-phy at 8 { + reg = <0x8>; + device_type = "tbi-phy"; + }; + }; + + enet0: ethernet at 2d10000 { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + fsl,dma-endian-le; + fsl,num_rx_queues = <0x1>; + fsl,num_tx_queues = <0x1>; + local-mac-address = [ 00 00 00 00 00 00 ]; + ranges; + + queue-group at 0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x2d10000 0x0 0x8000>; + fsl,rx-bit-map = <0xff>; + fsl,tx-bit-map = <0xff>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + }; + + }; + + enet1: ethernet at 2d50000 { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + fsl,dma-endian-le; + fsl,num_rx_queues = <0x1>; + fsl,num_tx_queues = <0x1>; + local-mac-address = [ 00 00 00 00 00 00 ]; + ranges; + + queue-group at 0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x2d50000 0x0 0x8000>; + fsl,rx-bit-map = <0xff>; + fsl,tx-bit-map = <0xff>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + }; + + }; + + enet2: ethernet at 2d90000 { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + fsl,dma-endian-le; + fsl,num_rx_queues = <0x1>; + fsl,num_tx_queues = <0x1>; + local-mac-address = [ 00 00 00 00 00 00 ]; + ranges; + + queue-group at 0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x2d90000 0x0 0x8000>; + fsl,rx-bit-map = <0xff>; + fsl,tx-bit-map = <0xff>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + usb at 8600000 { + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; + reg = <0x0 0x8600000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + phy_type = "ulpi"; + }; + + usb at 3100000 { + compatible = "fsl,fsl-dwc3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dwc3 { + compatible = "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + maximum-speed = "high-speed"; + }; + }; + + can0: can at 2a70000 { + compatible = "fsl,ls1021a-flexcan"; + reg = <0x0 0x2a70000 0x0 0x1000>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "per"; + status = "disabled"; + }; + + can1: can at 2a80000 { + compatible = "fsl,ls1021a-flexcan"; + reg = <0x0 0x2a80000 0x0 0x1000>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "per"; + status = "disabled"; + }; + + can2: can at 2a90000 { + compatible = "fsl,ls1021a-flexcan"; + reg = <0x0 0x2a90000 0x0 0x1000>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "per"; + status = "disabled"; + }; + + can3: can at 2aa0000 { + compatible = "fsl,ls1021a-flexcan"; + reg = <0x0 0x2aa0000 0x0 0x1000>; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "per"; + status = "disabled"; + }; + }; + + dcsr at 20000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ls1021a-dcsr", "simple-bus"; + + ranges = <0x0 0x0 0x20000000 0x1000000>; + + dcsr-epu at 0 { + compatible = "fsl,ls1021a-dcsr-epu"; + reg = <0x0 0x10000>; + }; + + dcsr-gdi at 100000 { + compatible = "fsl,ls1021a-dcsr-gdi"; + reg = <0x100000 0x10000>; + }; + + dcsr-dddi at 120000 { + compatible = "fsl,ls1021a-dcsr-dddi"; + reg = <0x120000 0x10000>; + }; + + dcsr-dcfg at 220000 { + compatible = "fsl,ls1021a-dcsr-dcfg"; + reg = <0x220000 0x1000>; + }; + + dcsr-clock at 221000 { + compatible = "fsl,ls1021a-dcsr-clock"; + reg = <0x221000 0x1000>; + }; + + dcsr-rcpm at 222000 { + compatible = "fsl,ls1021a-dcsr-rcpm"; + reg = <0x222000 0x1000 0x223000 0x1000>; + }; + + dcsr-ccp at 225000 { + compatible = "fsl,ls1021a-dcsr-ccp"; + reg = <0x225000 0x1000>; + }; + + dcsr-fusectrl at 226000 { + compatible = "fsl,ls1021a-dcsr-fusectrl"; + reg = <0x226000 0x1000>; + }; + + dcsr-dap at 300000 { + compatible = "fsl,ls1021a-dcsr-dap"; + reg = <0x300000 0x10000>; + }; + + dcsr-cstf at 350000 { + compatible = "fsl,ls1021a-dcsr-cstf"; + reg = <0x350000 0x1000 0x3a7000 0x1000>; + }; + + dcsr-a7rom at 360000 { + compatible = "fsl,ls1021a-dcsr-a7rom"; + reg = <0x360000 0x10000>; + }; + + dcsr-a7cpu at 370000 { + compatible = "fsl,ls1021a-dcsr-a7cpu"; + reg = <0x370000 0x8000>; + }; + + dcsr-a7cti at 378000 { + compatible = "fsl,ls1021a-dcsr-a7cti"; + reg = <0x378000 0x4000>; + }; + + dcsr-etm at 37c000 { + compatible = "fsl,ls1021a-dcsr-etm"; + reg = <0x37c000 0x1000 0x37d000 0x3000>; + }; + + dcsr-hugorom at 3a0000 { + compatible = "fsl,ls1021a-dcsr-hugorom"; + reg = <0x3a0000 0x1000>; + }; + + dcsr-etf at 3a1000 { + compatible = "fsl,ls1021a-dcsr-etf"; + reg = <0x3a1000 0x1000 0x3a2000 0x1000>; + }; + + dcsr-etr at 3a3000 { + compatible = "fsl,ls1021a-dcsr-etr"; + reg = <0x3a3000 0x1000>; + }; + + dcsr-cti at 3a4000 { + compatible = "fsl,ls1021a-dcsr-cti"; + reg = <0x3a4000 0x1000 0x3a5000 0x1000 0x3a6000 0x1000>; + }; + + dcsr-atbrepl at 3a8000 { + compatible = "fsl,ls1021a-dcsr-atbrepl"; + reg = <0x3a8000 0x1000>; + }; + + dcsr-tsgen-ctrl at 3a9000 { + compatible = "fsl,ls1021a-dcsr-tsgen-ctrl"; + reg = <0x3a9000 0x1000>; + }; + + dcsr-tsgen-read at 3aa000 { + compatible = "fsl,ls1021a-dcsr-tsgen-read"; + reg = <0x3aa000 0x1000>; + }; + }; +};
Signature · 1 line
1.8.0
PATCH 1/5 ARM: dts: Add SoC level device tree support for LS1021A
Hi,
As a general note, there seem to be many nodes for which bindings and drivers do not yet exist.
For those nodes which are unusable for reasons other than their status being "disabled", I would prefer that they were removed. They're useless now, and might not match the bindings that are eventually decided upon, which will result in annoying churn and possible breakage.
Quoted 24 lines · Jingchang Lu
From: Jingchang Lu <[email protected]>
Add Freescale LS1021A SoC device tree support
Signed-off-by Nikhil Badola <[email protected]>Signed-off-by Chenhui Zhao <[email protected]>Signed-off-by Suresh Gupta <[email protected]>Signed-off-by Shaveta Leekha <[email protected]>Signed-off-by Adrian Sendroiu <[email protected]>Signed-off-by Ruchika Gupta <[email protected]>Signed-off-by Bhupesh Sharma <[email protected]>Signed-off-by Chao Fu <[email protected]>Signed-off-by Xiubo Li <[email protected]>Signed-off-by Jingchang Lu <[email protected]>--- arch/arm/boot/dts/ls1021a.dtsi | 852 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 852 insertions(+) create mode 100644 arch/arm/boot/dts/ls1021a.dtsiarch/arm/boot/dts/ls1021a.dtsi new file +0
-0
[...]
arch/arm/boot/dts/ls1021a.dtsi line 37
Quoted 3 lines
arch/arm/boot/dts/ls1021a.dtsi new file +3
-0+ memory { + reg = <0x0 0x80000000 0x0 0x20000000>; + };
Missing device_type = "memory";
For unit-address and reg consistency, this should be memory at 0,80000000.
arch/arm/boot/dts/ls1021a.dtsi line 47
Quoted 10 lines
arch/arm/boot/dts/ls1021a.dtsi new file +10
-0+ + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu at 0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf00>; + };
That reg doesn't match the unit-address, which should be cpu at f00.
Why is MPIDR.Aff1 == 0xf?
arch/arm/boot/dts/ls1021a.dtsi line 53
Quoted 6 lines
arch/arm/boot/dts/ls1021a.dtsi new file +6
-0+ + cpu at 1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf01>; + };
Likewise.
[...]
arch/arm/boot/dts/ls1021a.dtsi line 73
Quoted 4 lines
arch/arm/boot/dts/ls1021a.dtsi new file +4
-0+ soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus";
Please put the compatible first out of all properties, it makes it far easier to read the DTS.
Please do that for other nodes too.
Quoted 10 lines
arch/arm/boot/dts/ls1021a.dtsi new file +10
-0+ interrupt-parent = <&gic>; + ranges; + + gic: interrupt-controller at 1400000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1401000 0x0 0x1000>, + <0x0 0x1402000 0x0 0x1000>, + <0x0 0x1404000 0x0 0x2000>,
arch/arm/boot/dts/ls1021a.dtsi line 93
Quoted 10 lines
arch/arm/boot/dts/ls1021a.dtsi new file +10
-0+ <0x0 0x1406000 0x0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + + }; + + tzasc: tzasc at 1500000 { + reg = <0x0 0x1500000 0x0 0x10000>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + };
There's no compatible string and "tzasc" doesn't appear to be handled magically anywhere, so this can't be probed even without the status property being "disabled".
Why is this here?
arch/arm/boot/dts/ls1021a.dtsi line 96
Quoted 3 lines
arch/arm/boot/dts/ls1021a.dtsi new file +3
-0+ + ifc: ifc at 1530000 { + compatible = "fsl,ls1021a-ifc", "fsl,ifc", "simple-bus";
This doesn't seem to have any children, ranges, #address-cells, or #size-cells. So why is "simple-bus" in the compatible list?
As far as I can see this is a flash controller, so "simple-bus" doesn't make any sense whatsoever (and existing uses, including that in the binding are a bug).
arch/arm/boot/dts/ls1021a.dtsi line 104
Quoted 8 lines
arch/arm/boot/dts/ls1021a.dtsi new file +8
-0+ reg = <0x0 0x1530000 0x0 0x10000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + }; + + dcfg: dcfg at 1ee0000 { + compatible = "fsl,ls1021a-dcfg"; + reg = <0x0 0x1ee0000 0x0 0x10000>; + };
Undocumented/unsupported binding.
What is this?
arch/arm/boot/dts/ls1021a.dtsi line 109
Quoted 4 lines
arch/arm/boot/dts/ls1021a.dtsi new file +4
-0+ qspi: quadspi at 1550000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-qspi";
Please put the compatible string first. It makes it easier to find.
Quoted 1 line
+ reg = <
0x00x15500000x00x10000>;
Missing the second reg entry? The binding didn't state it was optional.
arch/arm/boot/dts/ls1021a.dtsi line 113
Quoted 3 lines
arch/arm/boot/dts/ls1021a.dtsi new file +3
-0+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "qspi_en", "qspi"; + clocks = <&platform_clk 1>, <&platform_clk 1>;
Normally we put $X before $X-names properties.
I note that these clock-names are poorly documented. It would be nice to see that fixed up.
Quoted 1 line
+ big-endian;
The binding doesn't mention this. Does the driver support it?
Quoted 1 line
+ amba-base = <
0x40000000>;
The string "amba-base" shows up nowhere in mainline. What is this, and why is it here?
[...]
arch/arm/boot/dts/ls1021a.dtsi line 134
Quoted 4 lines
arch/arm/boot/dts/ls1021a.dtsi new file +4
-0+ scfg: scfg at 1570000 { + compatible = "fsl,ls1021a-scfg"; + reg = <0x0 0x1570000 0x0 0x10000>; + };
Undocumented/unsupported binding.
What is this?
[...]
arch/arm/boot/dts/ls1021a.dtsi line 234
Quoted 4 lines
arch/arm/boot/dts/ls1021a.dtsi new file +4
-0+ rcpm: rcpm at 1ee2000 { + compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1"; + reg = <0x0 0x1ee2000 0x0 0x10000>; + };
Undocumented/unsupported binding (both compatible strings).
What is this?
[...]
arch/arm/boot/dts/ls1021a.dtsi line 339
Quoted 9 lines
arch/arm/boot/dts/ls1021a.dtsi new file +9
-0+ gpio1: gpio at 2300000 { + compatible = "fsl,ls1021a-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + };
Undocumented/unsupported binding.
[...]
arch/arm/boot/dts/ls1021a.dtsi line 433
Quoted 8 lines
arch/arm/boot/dts/ls1021a.dtsi new file +8
-0+ lpuart1: serial at 2960000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2960000 0x0 0x1000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + };
Undocumented/unsupported binding.
[...]
arch/arm/boot/dts/ls1021a.dtsi line 488
Quoted 5 lines
arch/arm/boot/dts/ls1021a.dtsi new file +5
-0+ ftm2: ftm at 29f0000 { + reg = <0x0 0x29f0000 0x0 0x10000>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + };
Missing compatible strings.
[...]
arch/arm/boot/dts/ls1021a.dtsi line 513
Quoted 5 lines
arch/arm/boot/dts/ls1021a.dtsi new file +5
-0+ ftm5: ftm at 2a20000 { + reg = <0x0 0x2a20000 0x0 0x10000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + };
Missing compatible strings.
[...]
arch/arm/boot/dts/ls1021a.dtsi line 548
Quoted 8 lines
arch/arm/boot/dts/ls1021a.dtsi new file +8
-0+ wdog0: wdog at 2ad0000 { + compatible = "fsl,ls1021a-wdt", "fsl,imx21-wdt"; + reg = <0x0 0x2ad0000 0x0 0x10000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "wdog"; + big-endian; + };
That clock name looks aribitrary, and "fsl,imx21-wdt" isn't documented as taking a clock.
What is going on here?
[...]
arch/arm/boot/dts/ls1021a.dtsi line 710
Quoted 8 lines
arch/arm/boot/dts/ls1021a.dtsi new file +8
-0+ can0: can at 2a70000 { + compatible = "fsl,ls1021a-flexcan"; + reg = <0x0 0x2a70000 0x0 0x1000>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "per"; + status = "disabled"; + };
Undocumented/unsupported binding.
Was this mean to have an existing compatible string in the list?
Quoted 23 lines
arch/arm/boot/dts/ls1021a.dtsi new file +23
-0+ + can1: can at 2a80000 { + compatible = "fsl,ls1021a-flexcan"; + reg = <0x0 0x2a80000 0x0 0x1000>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "per"; + status = "disabled"; + }; + + can2: can at 2a90000 { + compatible = "fsl,ls1021a-flexcan"; + reg = <0x0 0x2a90000 0x0 0x1000>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "per"; + status = "disabled"; + }; + + can3: can at 2aa0000 { + compatible = "fsl,ls1021a-flexcan"; + reg = <0x0 0x2aa0000 0x0 0x1000>; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
arch/arm/boot/dts/ls1021a.dtsi line 743
Quoted 10 lines
arch/arm/boot/dts/ls1021a.dtsi new file +10
-0+ clocks = <&platform_clk 1>; + clock-names = "per"; + status = "disabled"; + }; + }; + + dcsr at 20000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ls1021a-dcsr", "simple-bus";
Missing a reg entry? Or is the unit-address arbitrary?
The "fsl,ls1021a-dcsr" string is undocumented/unsupported, as with the compatible strings of all the child nodes below.
Thanks,
Mark.
Quoted 117 lines
arch/arm/boot/dts/ls1021a.dtsi new file +109
-1+ + ranges = <0x0 0x0 0x20000000 0x1000000>; + + dcsr-epu at 0 { + compatible = "fsl,ls1021a-dcsr-epu"; + reg = <0x0 0x10000>; + }; + + dcsr-gdi at 100000 { + compatible = "fsl,ls1021a-dcsr-gdi"; + reg = <0x100000 0x10000>; + }; + + dcsr-dddi at 120000 { + compatible = "fsl,ls1021a-dcsr-dddi"; + reg = <0x120000 0x10000>; + }; + + dcsr-dcfg at 220000 { + compatible = "fsl,ls1021a-dcsr-dcfg"; + reg = <0x220000 0x1000>; + }; + + dcsr-clock at 221000 { + compatible = "fsl,ls1021a-dcsr-clock"; + reg = <0x221000 0x1000>; + }; + + dcsr-rcpm at 222000 { + compatible = "fsl,ls1021a-dcsr-rcpm"; + reg = <0x222000 0x1000 0x223000 0x1000>; + }; + + dcsr-ccp at 225000 { + compatible = "fsl,ls1021a-dcsr-ccp"; + reg = <0x225000 0x1000>; + }; + + dcsr-fusectrl at 226000 { + compatible = "fsl,ls1021a-dcsr-fusectrl"; + reg = <0x226000 0x1000>; + }; + + dcsr-dap at 300000 { + compatible = "fsl,ls1021a-dcsr-dap"; + reg = <0x300000 0x10000>; + }; + + dcsr-cstf at 350000 { + compatible = "fsl,ls1021a-dcsr-cstf"; + reg = <0x350000 0x1000 0x3a7000 0x1000>; + }; + + dcsr-a7rom at 360000 { + compatible = "fsl,ls1021a-dcsr-a7rom"; + reg = <0x360000 0x10000>; + }; + + dcsr-a7cpu at 370000 { + compatible = "fsl,ls1021a-dcsr-a7cpu"; + reg = <0x370000 0x8000>; + }; + + dcsr-a7cti at 378000 { + compatible = "fsl,ls1021a-dcsr-a7cti"; + reg = <0x378000 0x4000>; + }; + + dcsr-etm at 37c000 { + compatible = "fsl,ls1021a-dcsr-etm"; + reg = <0x37c000 0x1000 0x37d000 0x3000>; + }; + + dcsr-hugorom at 3a0000 { + compatible = "fsl,ls1021a-dcsr-hugorom"; + reg = <0x3a0000 0x1000>; + }; + + dcsr-etf at 3a1000 { + compatible = "fsl,ls1021a-dcsr-etf"; + reg = <0x3a1000 0x1000 0x3a2000 0x1000>; + }; + + dcsr-etr at 3a3000 { + compatible = "fsl,ls1021a-dcsr-etr"; + reg = <0x3a3000 0x1000>; + }; + + dcsr-cti at 3a4000 { + compatible = "fsl,ls1021a-dcsr-cti"; + reg = <0x3a4000 0x1000 0x3a5000 0x1000 0x3a6000 0x1000>; + }; + + dcsr-atbrepl at 3a8000 { + compatible = "fsl,ls1021a-dcsr-atbrepl"; + reg = <0x3a8000 0x1000>; + }; + + dcsr-tsgen-ctrl at 3a9000 { + compatible = "fsl,ls1021a-dcsr-tsgen-ctrl"; + reg = <0x3a9000 0x1000>; + }; + + dcsr-tsgen-read at 3aa000 { + compatible = "fsl,ls1021a-dcsr-tsgen-read"; + reg = <0x3aa000 0x1000>; + }; + }; +}; --1.8.0
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PATCH 1/5 ARM: dts: Add SoC level device tree support for LS1021A
Quoted 14 lines
-----Original Message-----
From: Mark Rutland [mailto:mark.rutland at arm.com]
Sent: Wednesday, July 02, 2014 7:15 PM
To: Lu Jingchang-B35083
Cc: shawn.guo at linaro.org; linux-arm-kernel at lists.infradead.org; devicetree at vger.kernel.org; Lu Jingchang-B35083; Badola Nikhil-B46172; Zhao Chenhui-B35336; Gupta Suresh-B42813; Leekha Shaveta-B20052; Sendroiu Adrian-B46904; Gupta Ruchika-R66431; Sharma Bhupesh-B45370; Fu Chao-B44548; Xiubo Li-B47053
Subject: Re: [PATCH 1/5] ARM: dts: Add SoC level device tree support for LS1021AHi,
Quoted 8 lines
As a general note, there seem to be many nodes for which bindings and drivers do not yet exist.
For those nodes which are unusable for reasons other than their status being "disabled", I would prefer that they were removed. They're useless now, and might not match the bindings that are eventually decided upon, which will result in annoying churn and possible breakage.
Thanks for help review these patches, I will revise the node as your comment. The LS1021A shares IP and driver with i.MX, Vybrid and PowerPC, some driver's behavior minor different between them, so patches is needed to make them work well between different platform and architecture. Thus some compatible include undocumented string, could it be added along with the driver support after the platform support is accepted? Thanks.
Quoted 29 lines · Jingchang Lu
Quoted 25 lines
From: Jingchang Lu <[email protected]>
Add Freescale LS1021A SoC device tree support
Signed-off-by Nikhil Badola <[email protected]>Signed-off-by Chenhui Zhao <[email protected]>Signed-off-by Suresh Gupta <[email protected]>Signed-off-by Shaveta Leekha <[email protected]>Signed-off-by Adrian Sendroiu <[email protected]>Signed-off-by Ruchika Gupta <[email protected]>Signed-off-by Bhupesh Sharma <[email protected]>Signed-off-by Chao Fu <[email protected]>Signed-off-by Xiubo Li <[email protected]>Signed-off-by Jingchang Lu <[email protected]>--- arch/arm/boot/dts/ls1021a.dtsi | 852 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 852 insertions(+) create mode 100644 arch/arm/boot/dts/ls1021a.dtsi(quoted diff) +0
-0
b/arch/arm/boot/dts/ls1021a.dtsinew file mode 100644 index 0000000..b06b320arch/arm/boot/dts/ls1021a.dtsi new file +0
-0[...]
Quoted 8 lines
arch/arm/boot/dts/ls1021a.dtsi line 37
Quoted 3 lines
arch/arm/boot/dts/ls1021a.dtsi new file +3
-0+ memory { + reg = <0x0 0x80000000 0x0 0x20000000>; + };Missing
device_type= "memory";For unit-address and reg consistency, this should be memory at 0,80000000.
I will add this, thanks.
Quoted 13 lines
arch/arm/boot/dts/ls1021a.dtsi line 47
Quoted 10 lines
arch/arm/boot/dts/ls1021a.dtsi new file +10
-0+ + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu at 0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf00>; + };That reg doesn't match the unit-address, which should be cpu at f00.
Quoted 1 line
Why is MPIDR.Aff1 ==
0xf?
The MPIDR value got from the SoC is 80000f00, so to match this the reg is set to x0f00. Thanks.
Quoted 11 lines
[...]
arch/arm/boot/dts/ls1021a.dtsi line 93
Quoted 6 lines
arch/arm/boot/dts/ls1021a.dtsi new file +6
-0+ + tzasc: tzasc at 1500000 { + reg = <0x0 0x1500000 0x0 0x10000>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + };There's no compatible string and "tzasc" doesn't appear to be handled magically anywhere, so this can't be probed even without the status property being "disabled".
I will remove this and all other unused node, it is not used currently. Thanks.
Quoted 7 lines
arch/arm/boot/dts/ls1021a.dtsi
Quoted 6 lines
arch/arm/boot/dts/ls1021a.dtsi new file +4
-0+ + ifc: ifc at 1530000 { + compatible = "fsl,ls1021a-ifc", "fsl,ifc", + "simple-bus";
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This doesn't seem to have any children, ranges, #address-cells, or #size- cells. So why is "simple-bus" in the compatible list?
As far as I can see this is a flash controller, so "simple-bus" doesn't make any sense whatsoever (and existing uses, including that in the binding are a bug).
Yes, it is a flash controller, the child nodes, ranges are in the <ls1021a-board>.dts. Here only describe the SoC level device and resource.
I will remove the "simple-bus" string, Thanks.
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arch/arm/boot/dts/ls1021a.dtsi line 104
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arch/arm/boot/dts/ls1021a.dtsi new file +8
-0+ reg = <0x0 0x1530000 0x0 0x10000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + }; + + dcfg: dcfg at 1ee0000 { + compatible = "fsl,ls1021a-dcfg"; + reg = <0x0 0x1ee0000 0x0 0x10000>; + };
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Undocumented/unsupported binding.
What is this?
It is the device configuration unit that provides general purpose configuration and status for the device, there isn't a dedicate driver for it, device that has configuration and status register located in this space could operate on it. Currently it is used to set the secondary core start address and release the secondary core from holdoff and startup. Thanks.
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arch/arm/boot/dts/ls1021a.dtsi line 109
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arch/arm/boot/dts/ls1021a.dtsi new file +4
-0+ qspi: quadspi at 1550000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-qspi";Please put the compatible string first. It makes it easier to find.
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+ reg = <
0x00x15500000x00x10000>;Missing the second reg entry? The binding didn't state it was optional.
I will check this, thanks.
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arch/arm/boot/dts/ls1021a.dtsi line 113
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arch/arm/boot/dts/ls1021a.dtsi new file +3
-0+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "qspi_en", "qspi"; + clocks = <&platform_clk 1>, <&platform_clk 1>;Normally we put $X before $X-names properties.
I note that these clock-names are poorly documented. It would be nice to see that fixed up.
We will check this subsequently. Thanks.
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+ big-endian;
The binding doesn't mention this. Does the driver support it?
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+ amba-base = <
0x40000000>;The string "amba-base" shows up nowhere in mainline. What is this, and why is it here?
[...]
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arch/arm/boot/dts/ls1021a.dtsi line 134
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arch/arm/boot/dts/ls1021a.dtsi new file +4
-0+ scfg: scfg at 1570000 { + compatible = "fsl,ls1021a-scfg"; + reg = <0x0 0x1570000 0x0 0x10000>; + };Undocumented/unsupported binding.
What is this?
It is the supplemental configuration unit, provides SoC specific configuration and status registers for the device. Some device driver need this space to configure or get status. If this is need document, which location is suitable for its document? Thanks.
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[...]
arch/arm/boot/dts/ls1021a.dtsi
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arch/arm/boot/dts/ls1021a.dtsi new file +2
-0+ rcpm: rcpm at 1ee2000 { + compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-
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rcpm-2.1";
arch/arm/boot/dts/ls1021a.dtsi
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arch/arm/boot/dts/ls1021a.dtsi new file +2
-0+ reg = <0x0 0x1ee2000 0x0 0x10000>; + };Undocumented/unsupported binding (both compatible strings).
What is this?
The Run Control and Power Management (RCPM) module performs all device-level tasks associated with device run control and power management. It will be used by the PM driver currently. Thanks.
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[...]
arch/arm/boot/dts/ls1021a.dtsi line 339
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arch/arm/boot/dts/ls1021a.dtsi new file +9
-0+ gpio1: gpio at 2300000 { + compatible = "fsl,ls1021a-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + };
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Undocumented/unsupported binding.
The bind document will be add along with the SoC platform support patch for it. Thanks.
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[...]
arch/arm/boot/dts/ls1021a.dtsi line 433
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arch/arm/boot/dts/ls1021a.dtsi new file +8
-0+ lpuart1: serial at 2960000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2960000 0x0 0x1000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + };
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Undocumented/unsupported binding.
I will add the bind document for this. Thanks.
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[...]
[...]
arch/arm/boot/dts/ls1021a.dtsi line 548
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arch/arm/boot/dts/ls1021a.dtsi new file +8
-0+ wdog0: wdog at 2ad0000 { + compatible = "fsl,ls1021a-wdt", "fsl,imx21-wdt"; + reg = <0x0 0x2ad0000 0x0 0x10000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "wdog"; + big-endian; + };
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That clock name looks aribitrary, and "fsl,imx21-wdt" isn't documented as taking a clock.
What is going on here?
The imx2_wdt driver need the clock, the clock name is not used, should it be removed? and maybe the document is omitted, we'll check and add it subsequently. Thanks.
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[...]
arch/arm/boot/dts/ls1021a.dtsi line 710
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arch/arm/boot/dts/ls1021a.dtsi new file +8
-0+ can0: can at 2a70000 { + compatible = "fsl,ls1021a-flexcan"; + reg = <0x0 0x2a70000 0x0 0x1000>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "per"; + status = "disabled"; + };
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Undocumented/unsupported binding.
Was this mean to have an existing compatible string in the list?
There will be fsl,ls1021a-flexcan support after the platform support is accepted, It is list here just for the SoC level device resource.
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arch/arm/boot/dts/ls1021a.dtsi new file +23
-0+ + can1: can at 2a80000 { + compatible = "fsl,ls1021a-flexcan"; + reg = <0x0 0x2a80000 0x0 0x1000>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "per"; + status = "disabled"; + }; + + can2: can at 2a90000 { + compatible = "fsl,ls1021a-flexcan"; + reg = <0x0 0x2a90000 0x0 0x1000>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "per"; + status = "disabled"; + }; + + can3: can at 2aa0000 { + compatible = "fsl,ls1021a-flexcan"; + reg = <0x0 0x2aa0000 0x0 0x1000>; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;arch/arm/boot/dts/ls1021a.dtsi line 743
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arch/arm/boot/dts/ls1021a.dtsi new file +10
-0+ clocks = <&platform_clk 1>; + clock-names = "per"; + status = "disabled"; + }; + }; + + dcsr at 20000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ls1021a-dcsr", "simple-bus";Missing a reg entry? Or is the unit-address arbitrary?
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The "fsl,ls1021a-dcsr" string is undocumented/unsupported, as with the compatible strings of all the child nodes below.
Thanks,
Mark.
It share the drive with PowerPC SoCs, the reg here is not used, only the child node's will be used. Thanks.
Best Regards,
Jingchang
PATCH 1/5 ARM: dts: Add SoC level device tree support for LS1021A
Quoted 22 lines · Jingchang Lu
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-----Original Message-----
From: Mark Rutland [mailto:mark.rutland at arm.com]
Sent: Wednesday, July 02, 2014 7:15 PM
To: Lu Jingchang-B35083
Cc: shawn.guo at linaro.org; linux-arm-kernel at lists.infradead.org; devicetree at vger.kernel.org; Lu Jingchang-B35083; Badola Nikhil-B46172; Zhao Chenhui-B35336; Gupta Suresh-B42813; Leekha Shaveta-B20052; Sendroiu Adrian-B46904; Gupta Ruchika-R66431; Sharma Bhupesh-B45370; Fu Chao-B44548; Xiubo Li-B47053
Subject: Re: [PATCH 1/5] ARM: dts: Add SoC level device tree support for LS1021AHi,
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As a general note, there seem to be many nodes for which bindings and drivers do not yet exist.
For those nodes which are unusable for reasons other than their status being "disabled", I would prefer that they were removed. They're useless now, and might not match the bindings that are eventually decided upon, which will result in annoying churn and possible breakage.
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Thanks for help review these patches, I will revise the node as your comment. The LS1021A shares IP and driver with i.MX, Vybrid and PowerPC, some driver's behavior minor different between them, so patches is needed to make them work well between different platform and architecture. Thus some compatible include undocumented string, could it be added along with the driver support after the platform support is accepted? Thanks.
Those nodes in the DT which are useless at the moment should be dropped. There's no point having them there.
We can add them when driver support is added, along with documentation.
[...]
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arch/arm/boot/dts/ls1021a.dtsi line 47
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arch/arm/boot/dts/ls1021a.dtsi new file +10
-0+ + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu at 0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf00>; + };That reg doesn't match the unit-address, which should be cpu at f00.
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Why is MPIDR.Aff1 ==
0xf?The MPIDR value got from the SoC is
80000f00, so to match this the reg is set to x0f00. Thanks.
Ok. Please update the unit-address on the nodes to match.
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[...]
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arch/arm/boot/dts/ls1021a.dtsi new file +6
-0+ + tzasc: tzasc at 1500000 { + reg = <0x0 0x1500000 0x0 0x10000>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + };
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There's no compatible string and "tzasc" doesn't appear to be handled magically anywhere, so this can't be probed even without the status property being "disabled".
I will remove this and all other unused node, it is not used currently. Thanks.
Thanks.
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arch/arm/boot/dts/ls1021a.dtsi
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arch/arm/boot/dts/ls1021a.dtsi new file +4
-0+ + ifc: ifc at 1530000 { + compatible = "fsl,ls1021a-ifc", "fsl,ifc", + "simple-bus";This doesn't seem to have any children, ranges, #address-cells, or #size- cells. So why is "simple-bus" in the compatible list?
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As far as I can see this is a flash controller, so "simple-bus" doesn't make any sense whatsoever (and existing uses, including that in the binding are a bug).
Yes, it is a flash controller, the child nodes, ranges are in the <ls1021a-board>.dts. Here only describe the SoC level device and resource.
I will remove the "simple-bus" string, Thanks.
Ok.
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arch/arm/boot/dts/ls1021a.dtsi new file +8
-0+ reg = <0x0 0x1530000 0x0 0x10000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + }; + + dcfg: dcfg at 1ee0000 { + compatible = "fsl,ls1021a-dcfg"; + reg = <0x0 0x1ee0000 0x0 0x10000>; + };
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Undocumented/unsupported binding.
What is this?
It is the device configuration unit that provides general purpose configuration and status for the device, there isn't a dedicate driver for it, device that has configuration and status register located in this space could operate on it. Currently it is used to set the secondary core start address and release the secondary core from holdoff and startup. Thanks.
Then we should document it.
[...]
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+ big-endian;
The binding doesn't mention this. Does the driver support it?
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+ amba-base = <
0x40000000>;The string "amba-base" shows up nowhere in mainline. What is this, and why is it here?
[...]
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arch/arm/boot/dts/ls1021a.dtsi new file +4
-0+ scfg: scfg at 1570000 { + compatible = "fsl,ls1021a-scfg"; + reg = <0x0 0x1570000 0x0 0x10000>; + };
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Undocumented/unsupported binding.
What is this?
It is the supplemental configuration unit, provides SoC specific configuration and status registers for the device. Some device driver need this space to configure or get status. If this is need document, which location is suitable for its document? Thanks.
Documentation/devicetree/bindings/soc/ ?
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[...]
Review
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(quoted diff) +2
-0+ rcpm: rcpm at 1ee2000 { + compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1";
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Review
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(quoted diff) +2
-0+ reg = <0x0 0x1ee2000 0x0 0x10000>; + };Undocumented/unsupported binding (both compatible strings).
What is this?
The Run Control and Power Management (RCPM) module performs all device-level tasks associated with device run control and power management. It will be used by the PM driver currently. Thanks.
As far as I can see this is _not_ used currently; both strings appear nowhere in mainline.
Drop the node for now. It can be added alongside the driver and binding.
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[...]
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arch/arm/boot/dts/ls1021a.dtsi new file +9
-0+ gpio1: gpio at 2300000 { + compatible = "fsl,ls1021a-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + };
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Undocumented/unsupported binding.
The bind document will be add along with the SoC platform support patch for it. Thanks.
Drop the node for now.
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[...]
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arch/arm/boot/dts/ls1021a.dtsi new file +8
-0+ lpuart1: serial at 2960000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2960000 0x0 0x1000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + };
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Undocumented/unsupported binding.
I will add the bind document for this. Thanks.
Ok.
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[...]
[...]
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arch/arm/boot/dts/ls1021a.dtsi new file +8
-0+ wdog0: wdog at 2ad0000 { + compatible = "fsl,ls1021a-wdt", "fsl,imx21-wdt"; + reg = <0x0 0x2ad0000 0x0 0x10000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "wdog"; + big-endian; + };
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That clock name looks aribitrary, and "fsl,imx21-wdt" isn't documented as taking a clock.
What is going on here?
The
imx2_wdtdriver need the clock, the clock name is not used, should it be removed? and maybe the document is omitted, we'll check and add it subsequently. Thanks.
Either document the clock name and make sure it's used consistently, or drop it. The latter seems like the easiest approach.
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[...]
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arch/arm/boot/dts/ls1021a.dtsi new file +8
-0+ can0: can at 2a70000 { + compatible = "fsl,ls1021a-flexcan"; + reg = <0x0 0x2a70000 0x0 0x1000>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "per"; + status = "disabled"; + };
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Undocumented/unsupported binding.
Was this mean to have an existing compatible string in the list?
There will be fsl,ls1021a-flexcan support after the platform support is accepted, It is list here just for the SoC level device resource.
Add the node when you add support. Drop it for now.
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arch/arm/boot/dts/ls1021a.dtsi new file +23
-0+ + can1: can at 2a80000 { + compatible = "fsl,ls1021a-flexcan"; + reg = <0x0 0x2a80000 0x0 0x1000>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "per"; + status = "disabled"; + }; + + can2: can at 2a90000 { + compatible = "fsl,ls1021a-flexcan"; + reg = <0x0 0x2a90000 0x0 0x1000>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "per"; + status = "disabled"; + }; + + can3: can at 2aa0000 { + compatible = "fsl,ls1021a-flexcan"; + reg = <0x0 0x2aa0000 0x0 0x1000>; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;arch/arm/boot/dts/ls1021a.dtsi line 743
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arch/arm/boot/dts/ls1021a.dtsi new file +10
-0+ clocks = <&platform_clk 1>; + clock-names = "per"; + status = "disabled"; + }; + }; + + dcsr at 20000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ls1021a-dcsr", "simple-bus";Missing a reg entry? Or is the unit-address arbitrary?
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The "fsl,ls1021a-dcsr" string is undocumented/unsupported, as with the compatible strings of all the child nodes below.
Thanks,
Mark.It share the drive with PowerPC SoCs, the reg here is not used, only the child node's will be used. Thanks.
Ok. So drop the unit-address.
Thanks,
Mark.
PATCH 2/5 ARM: dts: Add initial LS1021A QDS board dts support
In reply to Jingchang LuFrom: Jingchang Lu <[email protected]>
--- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/ls1021a-qds.dts | 380 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 382 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/ls1021a-qds.dts
arch/arm/boot/dts/Makefile +2 -1
@@ -235,7 +235,8 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6sx-sdb.dtb \ vf610-colibri.dtb \ vf610-cosmic.dtb \ - vf610-twr.dtb + vf610-twr.dtb \ + ls1021a-qds.dtb dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ imx23-olinuxino.dtb \ imx23-stmp378x_devb.dtb \
arch/arm/boot/dts/ls1021a-qds.dts new file +380 -0
380 lines not on this page · raw message
Signature · 1 line
1.8.0
PATCH 3/5 ARM: dts: Add initial LS1021A TWR board dts support
In reply to Jingchang Lu--- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/ls1021a-twr.dts | 236 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 238 insertions(+), 1 deletion(-) create mode 100755 arch/arm/boot/dts/ls1021a-twr.dts
arch/arm/boot/dts/Makefile +2 -1
@@ -236,7 +236,8 @@ dtb-$(CONFIG_ARCH_MXC) += \ vf610-colibri.dtb \ vf610-cosmic.dtb \ vf610-twr.dtb \ - ls1021a-qds.dtb + ls1021a-qds.dtb \ + ls1021a-twr.dtb dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ imx23-olinuxino.dtb \ imx23-stmp378x_devb.dtb \
arch/arm/boot/dts/ls1021a-twr.dts new file +236 -0
236 lines not on this page · raw message
Signature · 1 line
1.8.0
PATCH 4/5 ARM: imx: Add initial support for Freescale LS1021A
In reply to Jingchang LuFrom: Jingchang Lu <[email protected]>
The LS1021A SoC is a dual-core Cortex-A7 based processor, this add the initial support for it.
--- arch/arm/mach-imx/Kconfig | 17 ++++++++++++++ arch/arm/mach-imx/Makefile | 2 ++ arch/arm/mach-imx/mach-ls1021a.c | 49 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 68 insertions(+) create mode 100644 arch/arm/mach-imx/mach-ls1021a.c
arch/arm/mach-imx/Kconfig +17 -0
@@ -762,6 +762,23 @@ config SOC_VF610 help This enable support for Freescale Vybrid VF610 processor. +config FSL_SOC + bool + +config SOC_LS1021A + bool "Freescale LS1021A support" + select CPU_V7 + select ARM_GIC + select CLKSRC_OF + select HAVE_ARM_ARCH_TIMER + select HAVE_SMP + select FSL_SOC + select MIGHT_HAVE_PCI + select PCI_DOMAINS if PCI + + help + This enable support for Freescale LS1021A processor. + endif source "arch/arm/mach-imx/devices/Kconfig"
arch/arm/mach-imx/Makefile +2 -0
@@ -114,4 +114,6 @@ obj-$(CONFIG_SOC_IMX53) += mach-imx53.o obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o +obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o + obj-y += devices/
arch/arm/mach-imx/mach-ls1021a.c new file +49 -0
49 lines not on this page · raw message
Signature · 1 line
1.8.0
PATCH 4/5 ARM: imx: Add initial support for Freescale LS1021A
Quoted 77 lines · Jingchang Lu
From: Jingchang Lu <[email protected]>
The LS1021A SoC is a dual-core Cortex-A7 based processor, this add the initial support for it.
Signed-off-by Jingchang Lu <[email protected]>--- arch/arm/mach-imx/Kconfig | 17 ++++++++++++++ arch/arm/mach-imx/Makefile | 2 ++ arch/arm/mach-imx/mach-ls1021a.c | 49 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 68 insertions(+) create mode 100644 arch/arm/mach-imx/mach-ls1021a.carch/arm/mach-imx/Kconfig +17
-0@@ -762,6 +762,23 @@ config SOC_VF610 help This enable support for Freescale Vybrid VF610 processor. +config FSL_SOC + bool + +config SOC_LS1021A + bool "Freescale LS1021A support" + select CPU_V7 + select ARM_GIC + select CLKSRC_OF + select HAVE_ARM_ARCH_TIMER + select HAVE_SMP + select FSL_SOC + select MIGHT_HAVE_PCI + select PCI_DOMAINS if PCI + + help + This enable support for Freescale LS1021A processor. + endif source "arch/arm/mach-imx/devices/Kconfig"arch/arm/mach-imx/Makefile +2
-0@@ -114,4 +114,6 @@ obj-$(CONFIG_SOC_IMX53) += mach-imx53.o obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o +obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o + obj-y += devices/arch/arm/mach-imx/mach-ls1021a.c new file +19
-0@@ -0,0 +1,49 @@ +/* +* Copyright 2013-2014 Freescale Semiconductor, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +*/ + +#include <linux/of_platform.h> +#include <asm/mach/arch.h> + +#include "common.h" + +static const struct of_device_id of_ls1021a_match_table[] = { + { + .compatible ="simple-bus" , + }, + {
arch/arm/mach-imx/mach-ls1021a.c line 29
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arch/arm/mach-imx/mach-ls1021a.c new file +10
-0+ .compatible = "fsl,ifc", + }, + { + .compatible = "fsl,fpga-qixis", + }, + { + .compatible = "fsl,qe", + }, + {} +};
Are any of thse not always-on (or default-on) MMIO busses?
Is there any reason for not giving them their own drivers?
arch/arm/mach-imx/mach-ls1021a.c line 33
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arch/arm/mach-imx/mach-ls1021a.c new file +4
-0+ +static void __init ls1021a_init_machine (void ) +{ +mxc_arch_reset_init_dt ();
This looks to only be used to set up a watchdog timer. Is there any reason this logic can't be moved to the watchdog timer driver?
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arch/arm/mach-imx/mach-ls1021a.c new file +5
-0+of_platform_populate (NULL , of_ls1021a_match_table,NULL ,NULL ); +} + +static const char *ls1021a_dt_compat[]__initdata = { +"fsl,ls1021a" ,
arch/arm/mach-imx/mach-ls1021a.c line 48
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arch/arm/mach-imx/mach-ls1021a.c new file +10
-0+NULL , +}; + +DT_MACHINE_START(LS1021A, "Freescale LS1021A") +#ifdef CONFIG_ZONE_DMA + .dma_zone_size = SZ_128M, +#endif + .init_machine = ls1021a_init_machine, + .dt_compat = ls1021a_dt_compat, + .restart = mxc_restart,
AFAICT, that jsut uses the WDT for restart. Why can't the watchdog driver register itself as a restart device?
That would bring us close to an empty machine descriptor, and enable reuse of the WDT and those busses.
Thanks,
Mark.
PATCH 4/5 ARM: imx: Add initial support for Freescale LS1021A
Quoted 53 lines
-----Original Message-----
From: Mark Rutland [mailto:mark.rutland at arm.com]
Sent: Wednesday, July 02, 2014 7:21 PM
To: Lu Jingchang-B35083
Cc: shawn.guo at linaro.org; linux-arm-kernel at lists.infradead.org; devicetree at vger.kernel.org; Lu Jingchang-B35083
Subject: Re: [PATCH 4/5] ARM: imx: Add initial support for Freescale LS1021AQuoted 30 lines · Jingchang Lu
From: Jingchang Lu <[email protected]>
arch/arm/mach-imx/mach-ls1021a.c new file +21
-0@@ -0,0 +1,49 @@ +/* +* Copyright 2013-2014 Freescale Semiconductor, Inc. +* +* This program is free software; you can redistribute it and/or +modify +* it under the terms of the GNU General Public License as published +by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +*/ + +#include <linux/of_platform.h> +#include <asm/mach/arch.h> + +#include "common.h" + +static const struct of_device_id of_ls1021a_match_table[] = { + { + .compatible ="simple-bus" , + }, + {arch/arm/mach-imx/mach-ls1021a.c line 31
Quoted 10 lines
arch/arm/mach-imx/mach-ls1021a.c new file +10
-0+ .compatible = "fsl,ifc", + }, + { + .compatible = "fsl,fpga-qixis", + }, + { + .compatible = "fsl,qe", + }, + {} +};Are any of thse not always-on (or default-on) MMIO busses?
Quoted 2 lines
Is there any reason for not giving them their own drivers?
Normally these are always-on. The child nodes are handled by different drivers, so to make the devices being added by the of system, they are claimed here. Thanks.
Quoted 18 lines
arch/arm/mach-imx/mach-ls1021a.c line 33
Quoted 3 lines
arch/arm/mach-imx/mach-ls1021a.c new file +3
-0+ +static void __init ls1021a_init_machine (void ) { +mxc_arch_reset_init_dt ();This looks to only be used to set up a watchdog timer. Is there any reason this logic can't be moved to the watchdog timer driver?
arch/arm/mach-imx/mach-ls1021a.c line 48
Quoted 7 lines
arch/arm/mach-imx/mach-ls1021a.c new file +7
-0+ +DT_MACHINE_START(LS1021A, "Freescale LS1021A") #ifdef CONFIG_ZONE_DMA + .dma_zone_size = SZ_128M, +#endif + .init_machine = ls1021a_init_machine, + .dt_compat = ls1021a_dt_compat, + .restart = mxc_restart,AFAICT, that jsut uses the WDT for restart. Why can't the watchdog driver register itself as a restart device?
Quoted 5 lines
That would bring us close to an empty machine descriptor, and enable reuse of the WDT and those busses.
Thanks,
Mark.
Yes, we use the watchdog timer for restart, just as i.MX and Vybrid, the WDT as a common driver it is still work for watchdog. Thanks.
PATCH 4/5 ARM: imx: Add initial support for Freescale LS1021A
Quoted 53 lines · Jingchang Lu
Quoted 53 lines
-----Original Message-----
From: Mark Rutland [mailto:mark.rutland at arm.com]
Sent: Wednesday, July 02, 2014 7:21 PM
To: Lu Jingchang-B35083
Cc: shawn.guo at linaro.org; linux-arm-kernel at lists.infradead.org; devicetree at vger.kernel.org; Lu Jingchang-B35083
Subject: Re: [PATCH 4/5] ARM: imx: Add initial support for Freescale LS1021AQuoted 30 lines · Jingchang Lu
From: Jingchang Lu <[email protected]>
arch/arm/mach-imx/mach-ls1021a.c new file +21
-0@@ -0,0 +1,49 @@ +/* +* Copyright 2013-2014 Freescale Semiconductor, Inc. +* +* This program is free software; you can redistribute it and/or +modify +* it under the terms of the GNU General Public License as published +by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +*/ + +#include <linux/of_platform.h> +#include <asm/mach/arch.h> + +#include "common.h" + +static const struct of_device_id of_ls1021a_match_table[] = { + { + .compatible ="simple-bus" , + }, + {arch/arm/mach-imx/mach-ls1021a.c line 31
Quoted 10 lines
arch/arm/mach-imx/mach-ls1021a.c new file +10
-0+ .compatible = "fsl,ifc", + }, + { + .compatible = "fsl,fpga-qixis", + }, + { + .compatible = "fsl,qe", + }, + {} +};Are any of thse not always-on (or default-on) MMIO busses?
Quoted 5 lines
Quoted 2 lines
Is there any reason for not giving them their own drivers?
Normally these are always-on. The child nodes are handled by different drivers, so to make the devices being added by the of system, they are claimed here. Thanks.
If these are always-on MMIO busses, is there any reason these can't have "simple-bus" as a fallback in their compatible lists in the DT? They would seemd to be compatible with it given they are in the table above...
That way we don't need the table at all, and we can always add drivers for them later if we need them...
Quoted 18 lines
Quoted 18 lines
arch/arm/mach-imx/mach-ls1021a.c line 33
Quoted 3 lines
arch/arm/mach-imx/mach-ls1021a.c new file +3
-0+ +static void __init ls1021a_init_machine (void ) { +mxc_arch_reset_init_dt ();This looks to only be used to set up a watchdog timer. Is there any reason this logic can't be moved to the watchdog timer driver?
arch/arm/mach-imx/mach-ls1021a.c line 48
Quoted 7 lines
arch/arm/mach-imx/mach-ls1021a.c new file +7
-0+ +DT_MACHINE_START(LS1021A, "Freescale LS1021A") #ifdef CONFIG_ZONE_DMA + .dma_zone_size = SZ_128M, +#endif + .init_machine = ls1021a_init_machine, + .dt_compat = ls1021a_dt_compat, + .restart = mxc_restart,AFAICT, that jsut uses the WDT for restart. Why can't the watchdog driver register itself as a restart device?
Quoted 7 lines
Quoted 5 lines
That would bring us close to an empty machine descriptor, and enable reuse of the WDT and those busses.
Thanks,
Mark.Yes, we use the watchdog timer for restart, just as i.MX and Vybrid, the WDT as a common driver it is still work for watchdog. Thanks.
That doesn't answer the question of why the restart code (and registration thereof) can't live in the WDT driver.
Thanks,
Mark.
PATCH 4/5 ARM: imx: Add initial support for Freescale LS1021A
Quoted 69 lines
-----Original Message-----
From: Mark Rutland [mailto:mark.rutland at arm.com]
Sent: Thursday, July 03, 2014 11:12 PM
To: Lu Jingchang-B35083
Cc: Guo Shawn-R65073; shawn.guo at linaro.org; linux-arm- kernel at lists.infradead.org; devicetree at vger.kernel.org
Subject: Re: [PATCH 4/5] ARM: imx: Add initial support for Freescale LS1021AQuoted 54 lines · Jingchang Lu
Quoted 54 lines
-----Original Message-----
From: Mark Rutland [mailto:mark.rutland at arm.com]
Sent: Wednesday, July 02, 2014 7:21 PM
To: Lu Jingchang-B35083
Cc: shawn.guo at linaro.org; linux-arm-kernel at lists.infradead.org; devicetree at vger.kernel.org; Lu Jingchang-B35083
Subject: Re: [PATCH 4/5] ARM: imx: Add initial support for Freescale LS1021AQuoted 31 lines · Jingchang Lu
From: Jingchang Lu <[email protected]>
arch/arm/mach-imx/mach-ls1021a.c new file +22
-0@@ -0,0 +1,49 @@ +/* +* Copyright 2013-2014 Freescale Semiconductor, Inc. +* +* This program is free software; you can redistribute it and/or +modify +* it under the terms of the GNU General Public License as +published by +* the Free Software Foundation; either version 2 of the License, +or +* (at your option) any later version. +*/ + +#include <linux/of_platform.h> +#include <asm/mach/arch.h> + +#include "common.h" + +static const struct of_device_id of_ls1021a_match_table[] = { + { + .compatible ="simple-bus" , + }, + {arch/arm/mach-imx/mach-ls1021a.c line 32
Quoted 10 lines
arch/arm/mach-imx/mach-ls1021a.c new file +10
-0+ .compatible = "fsl,ifc", + }, + { + .compatible = "fsl,fpga-qixis", + }, + { + .compatible = "fsl,qe", + }, + {} +};Are any of thse not always-on (or default-on) MMIO busses?
Quoted 4 lines
Quoted 2 lines
Is there any reason for not giving them their own drivers?
Normally these are always-on. The child nodes are handled by different drivers, so to make the devices being added by the of system, they are
claimed here.
Quoted 8 lines
Quoted 1 line
Thanks.
If these are always-on MMIO busses, is there any reason these can't have "simple-bus" as a fallback in their compatible lists in the DT? They would seemd to be compatible with it given they are in the table above...
That way we don't need the table at all, and we can always add drivers for them later if we need them...
Yes, if they can work well with the default "simple-bus", I will change to it, I will try this. Thanks.
Quoted 25 lines
Quoted 10 lines
Quoted 10 lines
arch/arm/mach-imx/mach-ls1021a.c line 33
Quoted 4 lines
arch/arm/mach-imx/mach-ls1021a.c new file +3
-0+ +static void __init ls1021a_init_machine (void ) { +mxc_arch_reset_init_dt ();This looks to only be used to set up a watchdog timer. Is there any reason this logic can't be moved to the watchdog timer driver?
arch/arm/mach-imx/mach-ls1021a.c line 37
Quoted 2 lines
arch/arm/mach-imx/mach-ls1021a.c new file +2
-0+ +DT_MACHINE_START(LS1021A, "Freescale LS1021A") #ifdef
CONFIG_ZONE_DMAQuoted 14 lines
Quoted 14 lines
arch/arm/mach-imx/mach-ls1021a.c line 48
Quoted 5 lines
arch/arm/mach-imx/mach-ls1021a.c new file +5
-0+ .dma_zone_size = SZ_128M, +#endif + .init_machine = ls1021a_init_machine, + .dt_compat = ls1021a_dt_compat, + .restart = mxc_restart,AFAICT, that jsut uses the WDT for restart. Why can't the watchdog driver register itself as a restart device?
That would bring us close to an empty machine descriptor, and enable reuse of the WDT and those busses.
Thanks,
Mark.
Quoted 8 lines
Quoted 2 lines
Yes, we use the watchdog timer for restart, just as i.MX and Vybrid, the WDT as a common driver it is still work for watchdog. Thanks.
That doesn't answer the question of why the restart code (and registration thereof) can't live in the WDT driver.
Thanks,
Mark.
Several i.MX SoCs have used this mxc_restart currently, and the watchdog driver is shared between them, if here move it to the driver layer, all others needs changes accordingly. So I think if that is preferred, we can move it together some times later. And BTW, what's the preferred restart register manner in the driver, just assign to the arm_pm_restart? Thanks.
Best Regards,
Jingchang
PATCH 5/5 ARM: imx: Add Freescale LS1021A SMP support
In reply to Jingchang LuFrom: Jingchang Lu <[email protected]>
Freescale LS1021A SoC deploys two cortex-A7 processors, this adds bring-up support for the secondary core.
--- arch/arm/mach-imx/common.h | 2 ++ arch/arm/mach-imx/headsmp.S | 11 ++++++++++ arch/arm/mach-imx/mach-ls1021a.c | 1 + arch/arm/mach-imx/platsmp.c | 44 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 58 insertions(+)
arch/arm/mach-imx/common.h +2 -0
@@ -98,6 +98,7 @@ void v7_secondary_startup(void);void imx_scu_map_io (void );void imx_smp_prepare (void );void imx_scu_standby_enable (void ); +void ls1021a_secondary_startup (void );#else static inline void imx_scu_map_io (void ) {}static inline void imx_smp_prepare (void ) {}
@@ -158,5 +159,6 @@ static inline void imx_init_l2cache(void) {}#endif extern struct smp_operations imx_smp_ops; +extern struct smp_operations ls1021a_smp_ops;#endif
arch/arm/mach-imx/headsmp.S +11 -0
@@ -29,3 +29,14 @@ ENTRY(v7_secondary_startup) set_diag_reg b secondary_startup ENDPROC(v7_secondary_startup) + +ENTRY(ls1021a_secondary_startup) + /* set CNTFREQ of secondary core */ + ldr r0, =12500000 + mcr p15, 0, r0, c14, c0, 0 + /* disable Physical and Virtural Timer */ + mov r0, #0x0 + mcr p15, 0, r0, c14, c2, 1 + mcr p15, 0, r0, c14, c3, 1 + b secondary_startup +ENDPROC(ls1021a_secondary_startup)
arch/arm/mach-imx/mach-ls1021a.c +1 -0
@@ -43,6 +43,7 @@ DT_MACHINE_START(LS1021A, "Freescale LS1021A")#ifdef CONFIG_ZONE_DMA .dma_zone_size = SZ_128M, #endif + .smp = smp_ops(ls1021a_smp_ops), .init_machine = ls1021a_init_machine, .dt_compat = ls1021a_dt_compat, .restart = mxc_restart,
arch/arm/mach-imx/platsmp.c +44 -0
53 lines not on this page · raw message
Signature · 1 line
1.8.0
Mark Rutland
NAKPATCH 5/5 ARM: imx: Add Freescale LS1021A SMP support
Quoted 12 lines · Jingchang Lu
From: Jingchang Lu <[email protected]>
Freescale LS1021A SoC deploys two cortex-A7 processors, this adds bring-up support for the secondary core.
Signed-off-by Jingchang Lu <[email protected]>--- arch/arm/mach-imx/common.h | 2 ++ arch/arm/mach-imx/headsmp.S | 11 ++++++++++ arch/arm/mach-imx/mach-ls1021a.c | 1 + arch/arm/mach-imx/platsmp.c | 44 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 58 insertions(+)
[...]
Quoted 8 lines
arch/arm/mach-imx/headsmp.S +0
-0@@ -29,3 +29,14 @@ ENTRY(v7_secondary_startup) set_diag_reg b secondary_startup ENDPROC(v7_secondary_startup)
arch/arm/mach-imx/headsmp.S ENTRY(v7_secondary_startup) · line 41
Quoted 10 lines
arch/arm/mach-imx/headsmp.S +10
-0+ +ENTRY(ls1021a_secondary_startup) + /* set CNTFREQ of secondary core */ + ldr r0, =12500000 + mcr p15, 0, r0, c14, c0, 0 + /* disable Physical and Virtural Timer */ + mov r0, #0x0 + mcr p15, 0, r0, c14, c2, 1 + mcr p15, 0, r0, c14, c3, 1 + b secondary_startup
Urrgh...
What about CNTVOFF? That's been a source of problems elsewhere.
Is the boot CPU set up correctly?
Is that frequency always going to be correct?
[...]
arch/arm/mach-imx/headsmp.S ENTRY(v7_secondary_startup)
Quoted 10 lines
arch/arm/mach-imx/headsmp.S +10
-0+static void __init ls1021a_smp_init_cpus(void) +{ + int i, ncores; + /* get number of cores from CP15 L2 controller register(L2CTLR)*/ + asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (ncores)); + + ncores = ((ncores >> 24) & 0x3) + 1; + for (i = ncores; i < NR_CPUS; i++) + set_cpu_possible(i, false); +}
NAK.
This information is _already_ in the DT. This adds more code to do redundant work, and it's broken.
The physical<->logical CPU ID mapping is arbitrary, so you set arbitrary CPUs as being online despite this not necessarily being the case.
Get rid of this, and rely on the DT being correct. There;s no reason it shouldn't be for a new platform.
Thanks,
Mark.
PATCH 5/5 ARM: imx: Add Freescale LS1021A SMP support
Quoted 48 lines
-----Original Message-----
From: Mark Rutland [mailto:mark.rutland at arm.com]
Sent: Wednesday, July 02, 2014 7:31 PM
To: Lu Jingchang-B35083
Cc: shawn.guo at linaro.org; linux-arm-kernel at lists.infradead.org; devicetree at vger.kernel.org; Lu Jingchang-B35083
Subject: Re: [PATCH 5/5] ARM: imx: Add Freescale LS1021A SMP supportQuoted 11 lines · Jingchang Lu
From: Jingchang Lu <[email protected]>
Freescale LS1021A SoC deploys two cortex-A7 processors, this adds bring-up support for the secondary core.
Signed-off-by Jingchang Lu <[email protected]>--- arch/arm/mach-imx/common.h | 2 ++ arch/arm/mach-imx/headsmp.S | 11 ++++++++++ arch/arm/mach-imx/mach-ls1021a.c | 1 + arch/arm/mach-imx/platsmp.c | 44++++++++++++++++++++++++++++++++++++++++
Quoted 1 line
4 files changed, 58 insertions(+)[...]
Quoted 8 lines
arch/arm/mach-imx/headsmp.S +0
-0@@ -29,3 +29,14 @@ ENTRY(v7_secondary_startup) set_diag_reg b secondary_startup ENDPROC(v7_secondary_startup)arch/arm/mach-imx/headsmp.S ENTRY(v7_secondary_startup) · line 41
Quoted 10 lines
arch/arm/mach-imx/headsmp.S +10
-0+ +ENTRY(ls1021a_secondary_startup) + /* set CNTFREQ of secondary core */ + ldr r0, =12500000 + mcr p15, 0, r0, c14, c0, 0 + /* disable Physical and Virtural Timer */ + mov r0, #0x0 + mcr p15, 0, r0, c14, c2, 1 + mcr p15, 0, r0, c14, c3, 1 + b secondary_startupUrrgh...
Quoted 6 lines
What about CNTVOFF? That's been a source of problems elsewhere.
Is the boot CPU set up correctly?
Is that frequency always going to be correct?
We use 12.5Mhz as the counter clock, and We have found the virtual counter offset issue. We currently use the physical counter as a workaround for this, we are also working on to clear the CNTVOFF in u-boot, when it is finished, the virtual counter would be sync and work well.
Thanks.
Quoted 17 lines
[...]
arch/arm/mach-imx/headsmp.S
Quoted 9 lines
arch/arm/mach-imx/headsmp.S +9
-0+static void __init ls1021a_smp_init_cpus(void) { + int i, ncores; + /* get number of cores from CP15 L2 controller register(L2CTLR)*/ + asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (ncores)); + + ncores = ((ncores >> 24) & 0x3) + 1; + for (i = ncores; i < NR_CPUS; i++) + set_cpu_possible(i, false); +}NAK.
This information is _already_ in the DT. This adds more code to do redundant work, and it's broken.
Quoted 8 lines
The physical<->logical CPU ID mapping is arbitrary, so you set arbitrary CPUs as being online despite this not necessarily being the case.
Get rid of this, and rely on the DT being correct. There;s no reason it shouldn't be for a new platform.
Thanks,
Mark.
I will remove this. Thanks.
Best Regards,
Jingchang