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ARM: i.MX27 clk: Introduce DT include for clock provider

PATCH New Alexander Shiyan 2 participants 5 messages Jul 5, 2014 – Jul 7, 2014

Subsystems (6)
Device tree bindings Arm (32-bit) Arm sub-architectures Arm i.MX and Layerscape +2 more subsystems
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Alexander Shiyan

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#0 lore raw

PATCH 1/4 ARM: i.MX27 clk: Introduce DT include for clock provider

Use clock defines in order to make devicetrees more human readable.

Signed-off-by Alexander Shiyan <[email protected]>
---
 .../devicetree/bindings/clock/imx27-clock.txt      | 127 +-------
 arch/arm/mach-imx/clk-imx27.c                      | 347 ++++++++++-----------
 include/dt-bindings/clock/imx27-clock.h            | 107 +++++++
 3 files changed, 285 insertions(+), 296 deletions(-)
 create mode 100644 include/dt-bindings/clock/imx27-clock.h
Documentation/devicetree/bindings/clock/imx27-clock.txt +16 -111
index 6bc9fd2..cc05de9 100644
@@ -7,117 +7,22 @@ Required properties:
 - #clock-cells: Should be <1>
 
 The clock consumer should specify the desired clock by having the clock
-ID in its "clocks" phandle cell.  The following is a full list of i.MX27
-clocks and IDs.
-
-	Clock		    ID
-	-----------------------
-	dummy                0
-	ckih                 1
-	ckil                 2
-	mpll                 3
-	spll                 4
-	mpll_main2           5
-	ahb                  6
-	ipg                  7
-	nfc_div              8
-	per1_div             9
-	per2_div             10
-	per3_div             11
-	per4_div             12
-	vpu_sel              13
-	vpu_div              14
-	usb_div              15
-	cpu_sel              16
-	clko_sel             17
-	cpu_div              18
-	clko_div             19
-	ssi1_sel             20
-	ssi2_sel             21
-	ssi1_div             22
-	ssi2_div             23
-	clko_en              24
-	ssi2_ipg_gate        25
-	ssi1_ipg_gate        26
-	slcdc_ipg_gate       27
-	sdhc3_ipg_gate       28
-	sdhc2_ipg_gate       29
-	sdhc1_ipg_gate       30
-	scc_ipg_gate         31
-	sahara_ipg_gate      32
-	rtc_ipg_gate         33
-	pwm_ipg_gate         34
-	owire_ipg_gate       35
-	lcdc_ipg_gate        36
-	kpp_ipg_gate         37
-	iim_ipg_gate         38
-	i2c2_ipg_gate        39
-	i2c1_ipg_gate        40
-	gpt6_ipg_gate        41
-	gpt5_ipg_gate        42
-	gpt4_ipg_gate        43
-	gpt3_ipg_gate        44
-	gpt2_ipg_gate        45
-	gpt1_ipg_gate        46
-	gpio_ipg_gate        47
-	fec_ipg_gate         48
-	emma_ipg_gate        49
-	dma_ipg_gate         50
-	cspi3_ipg_gate       51
-	cspi2_ipg_gate       52
-	cspi1_ipg_gate       53
-	nfc_baud_gate        54
-	ssi2_baud_gate       55
-	ssi1_baud_gate       56
-	vpu_baud_gate        57
-	per4_gate            58
-	per3_gate            59
-	per2_gate            60
-	per1_gate            61
-	usb_ahb_gate         62
-	slcdc_ahb_gate       63
-	sahara_ahb_gate      64
-	lcdc_ahb_gate        65
-	vpu_ahb_gate         66
-	fec_ahb_gate         67
-	emma_ahb_gate        68
-	emi_ahb_gate         69
-	dma_ahb_gate         70
-	csi_ahb_gate         71
-	brom_ahb_gate        72
-	ata_ahb_gate         73
-	wdog_ipg_gate        74
-	usb_ipg_gate         75
-	uart6_ipg_gate       76
-	uart5_ipg_gate       77
-	uart4_ipg_gate       78
-	uart3_ipg_gate       79
-	uart2_ipg_gate       80
-	uart1_ipg_gate       81
-	ckih_div1p5          82
-	fpm                  83
-	mpll_osc_sel         84
-	mpll_sel             85
-	spll_gate            86
-	mshc_div             87
-	rtic_ipg_gate        88
-	mshc_ipg_gate        89
-	rtic_ahb_gate        90
-	mshc_baud_gate       91
+ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h
+for the full list of i.MX27 clock IDs.
 
 Examples:
+	clks: ccm at 10027000{
+		compatible = "fsl,imx27-ccm";
+		reg = <0x10027000 0x1000>;
+		#clock-cells = <1>;
+	};
 
-clks: ccm at 10027000{
-	compatible = "fsl,imx27-ccm";
-	reg = <0x10027000 0x1000>;
-	#clock-cells = <1>;
-};
-
-uart1: serial at 1000a000 {
-	compatible = "fsl,imx27-uart", "fsl,imx21-uart";
-	reg = <0x1000a000 0x1000>;
-	interrupts = <20>;
-	clocks = <&clks 81>, <&clks 61>;
-	clock-names = "ipg", "per";
-	status = "disabled";
-};
+	uart1: serial at 1000a000 {
+		compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+		reg = <0x1000a000 0x1000>;
+		interrupts = <20>;
+		clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
+			 <&clks IMX27_CLK_PER1_GATE>;
+		clock-names = "ipg", "per";
+		status = "disabled";
+	};
arch/arm/mach-imx/clk-imx27.c +162 -185

382 lines not on this page · raw message

include/dt-bindings/clock/imx27-clock.h new file +107 -0

107 lines not on this page · raw message

Signature · 1 line
1.8.5.5
author
#1 lore raw

PATCH 2/4 ARM: i.MX27 clk: dts: Use clock defines in DTS files

Use clock definitions in i.MX27 DTS files.
Additional changes included in this patch (imx27.dtsi):
- Fix IPG clock for UART6.
- Use EMI_AHB_GATE clock for WEIM.
- Added GPIO_IPG_GATE clock for GPIO nodes. Currently this clock is not used by the driver, but it can be added in the future.

Signed-off-by Alexander Shiyan <[email protected]>
---
 arch/arm/boot/dts/imx27-pdk.dts                 |   2 +-
 arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts  |   2 +-
 arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi |   2 +-
 arch/arm/boot/dts/imx27.dtsi                    | 115 +++++++++++++++---------
 4 files changed, 77 insertions(+), 44 deletions(-)
arch/arm/boot/dts/imx27-pdk.dts +1 -1
index 4c31771..49450db 100644
@@ -28,7 +28,7 @@
 		usbphy0: usbphy at 0 {
 			compatible = "usb-nop-xceiv";
 			reg = <0>;
-			clocks = <&clks 0>;
+			clocks = <&clks IMX27_CLK_DUMMY>;
 			clock-names = "main_clk";
 		};
 	};
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +1 -1
index fe02bc7..538568b 100644
@@ -61,7 +61,7 @@
 			compatible = "usb-nop-xceiv";
 			reg = <2>;
 			vcc-supply = <&reg_5v0>;
-			clocks = <&clks 0>;
+			clocks = <&clks IMX27_CLK_DUMMY>;
 			clock-names = "main_clk";
 		};
 	};
arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +1 -1
index 2e376ed..b4e955e 100644
@@ -51,7 +51,7 @@
 			compatible = "usb-nop-xceiv";
 			reg = <0>;
 			vcc-supply = <&sw3_reg>;
-			clocks = <&clks 0>;
+			clocks = <&clks IMX27_CLK_DUMMY>;
 			clock-names = "main_clk";
 		};
 	};
arch/arm/boot/dts/imx27.dtsi +74 -41

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Signature · 1 line
1.8.5.5
author
#2 lore raw

PATCH 3/4 ARM: i.MX27 clk: Remove unused definitions

In reply to Alexander Shiyan

This patch removes definitions which not used anywhere in the driver.

Signed-off-by Alexander Shiyan <[email protected]>
---
 arch/arm/mach-imx/clk-imx27.c | 25 -------------------------
 1 file changed, 25 deletions(-)
arch/arm/mach-imx/clk-imx27.c +0 -25
index ef7001c..fcfb81b 100644
@@ -18,36 +18,11 @@ static void __iomem *ccm __initdata;
 #define CCM_MPCTL1		(ccm + 0x08)
 #define CCM_SPCTL0		(ccm + 0x0c)
 #define CCM_SPCTL1		(ccm + 0x10)
-#define CCM_OSC26MCTL		(ccm + 0x14)
 #define CCM_PCDR0		(ccm + 0x18)
 #define CCM_PCDR1		(ccm + 0x1c)
 #define CCM_PCCR0		(ccm + 0x20)
 #define CCM_PCCR1		(ccm + 0x24)
 #define CCM_CCSR		(ccm + 0x28)
-#define CCM_PMCTL		(ccm + 0x2c)
-#define CCM_PMCOUNT		(ccm + 0x30)
-#define CCM_WKGDCTL		(ccm + 0x34)
-
-#define CCM_CSCR_UPDATE_DIS	(1 << 31)
-#define CCM_CSCR_SSI2		(1 << 23)
-#define CCM_CSCR_SSI1		(1 << 22)
-#define CCM_CSCR_VPU		(1 << 21)
-#define CCM_CSCR_MSHC           (1 << 20)
-#define CCM_CSCR_SPLLRES        (1 << 19)
-#define CCM_CSCR_MPLLRES        (1 << 18)
-#define CCM_CSCR_SP             (1 << 17)
-#define CCM_CSCR_MCU            (1 << 16)
-#define CCM_CSCR_OSC26MDIV      (1 << 4)
-#define CCM_CSCR_OSC26M         (1 << 3)
-#define CCM_CSCR_FPM            (1 << 2)
-#define CCM_CSCR_SPEN           (1 << 1)
-#define CCM_CSCR_MPEN           (1 << 0)
-
-/* i.MX27 TO 2+ */
-#define CCM_CSCR_ARM_SRC        (1 << 15)
-
-#define CCM_SPCTL1_LF           (1 << 15)
-#define CCM_SPCTL1_BRMO         (1 << 6)
 
 static const char *vpu_sel_clks[] = { "spll", "mpll_main2", };
 static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
Signature · 1 line
1.8.5.5
author
#3 lore raw

PATCH 4/4 ARM: i.MX27 clk: Add 26 MHz oscillator circuit clock gate

In reply to Alexander Shiyan

This patch adds missing 26 MHz oscillator circuit clock gate support.

Signed-off-by Alexander Shiyan <[email protected]>
---
 arch/arm/mach-imx/clk-imx27.c           | 11 ++++++-----
 include/dt-bindings/clock/imx27-clock.h |  3 ++-
 2 files changed, 8 insertions(+), 6 deletions(-)
arch/arm/mach-imx/clk-imx27.c +6 -5
index fcfb81b..07bc32c 100644
@@ -27,10 +27,10 @@ static void __iomem *ccm __initdata;
 static const char *vpu_sel_clks[] = { "spll", "mpll_main2", };
 static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
 static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", };
-static const char *mpll_osc_sel_clks[] = { "ckih", "ckih_div1p5", };
+static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", };
 static const char *clko_sel_clks[] = {
-	"ckil", "fpm", "ckih", "ckih",
-	"ckih", "mpll", "spll", "cpu_div",
+	"ckil", "fpm", "ckih_gate", "ckih_gate",
+	"ckih_gate", "mpll", "spll", "cpu_div",
 	"ahb", "ipg", "per1_div", "per2_div",
 	"per3_div", "per4_div", "ssi1_div", "ssi2_div",
 	"nfc_div", "mshc_div", "vpu_div", "60m",

@@ -50,11 +50,12 @@ static void __init _mx27_clocks_init(unsigned long fref)
 	clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref);
 	clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768);
 	clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
-	clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3);
+	clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3);
+	clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3);
 	clk[IMX27_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks));
 	clk[IMX27_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));
 	clk[IMX27_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
-	clk[IMX27_CLK_SPLL] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
+	clk[IMX27_CLK_SPLL] = imx_clk_pllv1("spll", "ckih_gate", CCM_SPCTL0);
 	clk[IMX27_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
 	clk[IMX27_CLK_MPLL_MAIN2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
include/dt-bindings/clock/imx27-clock.h +2 -1
index 6b642d4..148b053 100644
@@ -102,6 +102,7 @@
 #define IMX27_CLK_MSHC_IPG_GATE		89
 #define IMX27_CLK_RTIC_AHB_GATE		90
 #define IMX27_CLK_MSHC_BAUD_GATE	91
-#define IMX27_CLK_MAX			92
+#define IMX27_CLK_CKIH_GATE		92
+#define IMX27_CLK_MAX			93
 
 #endif
Signature · 1 line
1.8.5.5