ARM: sun8i: Support A23 PRCM clock and reset controllers

Hi everyone,

This is the PRCM subset of v3 of the sun8i A23 bring-up series. This subset includes clock and reset controller support for the PRCM (power, reset and clock module) on the A23 SoC. It is based on my previous series for basic sun8i A23 clocks [1].

The first 3 patches add or fix the prcm clock drivers to support the A23's PRCM variant.

The fourth patch adds support for A23's PRCM to the sun6i-prcm driver. The difference between the A23 and the A31 regarding the PRCM block is 2 clock muxes were removed, a divider clock has slightly difference dividers, and some clock gates are gone. The resources used are unchanged. Drivers for the 2 clock muxes are replaced with fixed-factor clocks in the DT. So the A23 variant is supported with the sun6i-prcm driver with a slightly different sub-device list.

Patch 5 adds optional reset control support to the 8250_dw, which is used by sun6i and sun8i platforms. Till now, this wasn't needed from a working standpoint, as the bootloader de-asserts the reset control on the console UART for us. However, during the development of the sun8i patches, I noticed other UARTs wouldn't work. Also the new sun6i A31 Hummingbird has multiple UARTs available, which would require this patch.

Patch 6 adds deferred probing to 8250_dw. In my case, even though the clocks and reset controller "devices" were registered before the UART, the 8250_dw driver binded with the UART devices before the clocks and resets were available. This resulted in the 8250_dw driver failing. I only tested the R_UART device.

Strictly speaking it won't be needed once pinctrl support is added, as the driver core handles deferred probing for pinctrl phandles, and the pinctrl device for the R_UART is probed after it. However it may be required for the A31 Hummingbird development board. Suggestions welcome.

Patch 7 selects the sun6i-prcm driver when we're building for sun8i, so we don't end up with essential drivers missing.

Patch 8 adds the PRCM nodes, and the associated clock/reset phandles, to the sun8i DTSI.

Patch 9 adds the reset controller nodes to the sun8i DTSI, using drivers from sun6i, as an extra. I thought I'd do all the reset controllers in the same series.

These patches can go through their separate trees. There are no compile time dependencies between them.

Related changes since v2:

- Add separate driver for sun8i-a23-apb0-clk
- Use sun6i-a31-clock-reset for ahb1_rst

Related changes since v1:

- Add sun8i-a23-apb0-gates-clk compatible to sun6i-a31-apb0-gates-clk

Cheers
ChenYu

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/266990.html

Chen-Yu Tsai (9):
clk: sunxi: Add A23 APB0 divider clock support
clk: sunxi: Fix gate indexing for sun6i-a31-apb0-gates
clk: sunxi: Add A23 specific compatible to sun6i-a31-apb0-gates-clk
mfd: sun6i-prcm: Add support for Allwinner A23 PRCM
serial: 8250_dw: Add optional reset control support
serial: 8250_dw: Add support for deferred probing
ARM: sunxi: select MFD_SUN6I_PRCM when sun8i arch support is enabled
ARM: sun8i: Add PRCM clock and reset controller nodes to the DTSI
ARM: sun8i: Add reset controller nodes to the DTSI

 Documentation/devicetree/bindings/clock/sunxi.txt  |  2 +
 .../devicetree/bindings/mfd/sun6i-prcm.txt         |  2 +-
 .../bindings/serial/snps-dw-apb-uart.txt           |  1 +
 arch/arm/boot/dts/sun8i-a23.dtsi                   | 71 +++++++++++++++++++++-
 arch/arm/mach-sunxi/Kconfig                        |  3 +
 drivers/clk/sunxi/Makefile                         |  4 +-
 drivers/clk/sunxi/clk-sun6i-apb0-gates.c           |  7 ++-
 drivers/clk/sunxi/clk-sun8i-apb0.c                 | 68 +++++++++++++++++++++
 drivers/mfd/sun6i-prcm.c                           | 30 +++++++++
 drivers/tty/serial/8250/8250_dw.c                  | 13 ++++
 10 files changed, 197 insertions(+), 4 deletions(-)
 create mode 100644 drivers/clk/sunxi/clk-sun8i-apb0.c

2.0.1

The A23 has an almost identical PRCM clock tree. The difference in the APB0 clock is the smallest divisor is 1, instead of 2.

This patch adds a separate sun8i-a23-apb0-clk driver to support it.

---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/Makefile                        |  4 +-
 drivers/clk/sunxi/clk-sun8i-apb0.c                | 68 +++++++++++++++++++++++
 3 files changed, 72 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/sunxi/clk-sun8i-apb0.c

index 18030ce..68dbd3d 100644
@@ -28,6 +28,7 @@ Required properties:
 	"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
 	"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
 	"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
+	"allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
 	"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
 	"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
 	"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s

index 762fd64..6850cba 100644
@@ -6,4 +6,6 @@ obj-y += clk-sunxi.o clk-factors.o
 obj-y += clk-a10-hosc.o
 obj-y += clk-a20-gmac.o
 
-obj-$(CONFIG_MFD_SUN6I_PRCM) += clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o
+obj-$(CONFIG_MFD_SUN6I_PRCM) += \
+	clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
+	clk-sun8i-apb0.o

2.0.1

Just applied, thanks!

Maxime

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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sun6i-a31-apb0-gates supports using clock-indices for holes between individual gates. However, the driver passes the number of gates registered in clk_data->clk_num, which of_clk_src_onecell_get uses to recognize the range of valid indices a consumer can use.

This patch makes the driver pass the maximum gate index + 1, so of_clk_src_onecell_get does not complain about indices greater than gates registered.

This was tested on the A23 SoC, which has a similar APB0 clock, but has holes for gates to removed IP blocks.

---
 drivers/clk/sunxi/clk-sun6i-apb0-gates.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

index 44cd27c..b342f2a 100644
@@ -25,6 +25,7 @@ static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
 	void __iomem *reg;
 	int gate_id;
 	int ngates;
+	int gate_max = 0;
 	int i;
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);

@@ -72,9 +73,12 @@ static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
 							    reg, gate_id,
 							    0, NULL);
 		WARN_ON(IS_ERR(clk_data->clks[gate_id]));
+
+		if (gate_id > gate_max)
+			gate_max = gate_id;
 	}
 
-	clk_data->clk_num = ngates;
+	clk_data->clk_num = gate_max + 1;
 
 	return of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
 }

2.0.1

Applied, thanks!

Maxime

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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The sun6i-a31-apb0-gates-clk driver is generic in that it supports the "clock-indicies" DT property with "clock-output-names" to list the valid clock gate bits.

However this might lead one to assume that the clock in the A23 is the same as the A31. To make it clear, we add a new compatible for the A23, "allwinner,sun8i-a23-apb0-gates-clk".

---
 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
 drivers/clk/sunxi/clk-sun6i-apb0-gates.c          | 1 +
 2 files changed, 2 insertions(+)

index 68dbd3d..d3a5c3c 100644
@@ -34,6 +34,7 @@ Required properties:
 	"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
 	"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
 	"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
+	"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
 	"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
 	"allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
 	"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10

index b342f2a..f147fee 100644
@@ -85,6 +85,7 @@ static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
 
 const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
 	{ .compatible = "allwinner,sun6i-a31-apb0-gates-clk" },
+	{ .compatible = "allwinner,sun8i-a23-apb0-gates-clk" },
 	{ /* sentinel */ }
 };
 

2.0.1

The Allwinner A23 SoC has a PRCM unit like the previous A31 SoC. The differences are the AR100 clock can no longer be modified, the APB0 clock has different divisors, and some clock gates are gone.

This patch adds a compatible with a modified subdevice list for the A23.

---
 .../devicetree/bindings/mfd/sun6i-prcm.txt         |  2 +-
 drivers/mfd/sun6i-prcm.c                           | 30 ++++++++++++++++++++++
 2 files changed, 31 insertions(+), 1 deletion(-)

index 1f5a31f..03c5a55 100644
@@ -4,7 +4,7 @@ PRCM is an MFD device exposing several Power Management related devices
 (like clks and reset controllers).
 
 Required properties:
- - compatible: "allwinner,sun6i-a31-prcm"
+ - compatible: "allwinner,sun6i-a31-prcm" or "allwinner,sun8i-a23-prcm"
  - reg: The PRCM registers range
 
 The prcm node may contain several subdevices definitions:

index 718fc4d..283ab8d 100644
@@ -76,16 +76,46 @@ static const struct mfd_cell sun6i_a31_prcm_subdevs[] = {
 	},
 };
 
+static const struct mfd_cell sun8i_a23_prcm_subdevs[] = {
+	{
+		.name = "sun8i-a23-apb0-clk",
+		.of_compatible = "allwinner,sun8i-a23-apb0-clk",
+		.num_resources = ARRAY_SIZE(sun6i_a31_apb0_clk_res),
+		.resources = sun6i_a31_apb0_clk_res,
+	},
+	{
+		.name = "sun6i-a31-apb0-gates-clk",
+		.of_compatible = "allwinner,sun8i-a23-apb0-gates-clk",
+		.num_resources = ARRAY_SIZE(sun6i_a31_apb0_gates_clk_res),
+		.resources = sun6i_a31_apb0_gates_clk_res,
+	},
+	{
+		.name = "sun6i-a31-apb0-clock-reset",
+		.of_compatible = "allwinner,sun6i-a31-clock-reset",
+		.num_resources = ARRAY_SIZE(sun6i_a31_apb0_rstc_res),
+		.resources = sun6i_a31_apb0_rstc_res,
+	},
+};
+
 static const struct prcm_data sun6i_a31_prcm_data = {
 	.nsubdevs = ARRAY_SIZE(sun6i_a31_prcm_subdevs),
 	.subdevs = sun6i_a31_prcm_subdevs,
 };
 
+static const struct prcm_data sun8i_a23_prcm_data = {
+	.nsubdevs = ARRAY_SIZE(sun8i_a23_prcm_subdevs),
+	.subdevs = sun8i_a23_prcm_subdevs,
+};
+
 static const struct of_device_id sun6i_prcm_dt_ids[] = {
 	{
 		.compatible = "allwinner,sun6i-a31-prcm",
 		.data = &sun6i_a31_prcm_data,
 	},
+	{
+		.compatible = "allwinner,sun8i-a23-prcm",
+		.data = &sun8i_a23_prcm_data,
+	},
 	{ /* sentinel */ },
 };
 

2.0.1

Maxime

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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The Allwinner A31 and A23 SoCs have a reset controller maintaining the UART in reset by default.

This patch adds optional reset support to the driver.

---
 Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt | 1 +
 drivers/tty/serial/8250/8250_dw.c                             | 9 +++++++++
 2 files changed, 10 insertions(+)

index f13f1c5..cb9af84 100644
@@ -7,6 +7,7 @@ Required properties:
 - clock-frequency : the input clock frequency for the UART.
 
 Optional properties:
+- resets : phandle to the parent reset controller.
 - reg-shift : quantity to shift the register offsets by.  If this property is
   not present then the register offsets are not shifted.
 - reg-io-width : the size (in bytes) of the IO accesses that should be

index 51b307a..cb1b3dc 100644
@@ -26,6 +26,7 @@
 #include <linux/slab.h>
 #include <linux/acpi.h>
 #include <linux/clk.h>
+#include <linux/reset.h>
 #include <linux/pm_runtime.h>
 
 #include <asm/byteorder.h>

@@ -59,6 +60,7 @@ struct dw8250_data {
 	int			last_mcr;
 	int			line;
 	struct clk		*clk;
+	struct reset_control	*rst;
 	struct uart_8250_dma	dma;
 };
 

@@ -408,6 +410,10 @@ static int dw8250_probe(struct platform_device *pdev)
 		uart.port.uartclk = clk_get_rate(data->clk);
 	}
 
+	data->rst = devm_reset_control_get_optional(&pdev->dev, NULL);
+	if (!IS_ERR(data->rst))
+		reset_control_deassert(data->rst);
+
 	data->dma.rx_chan_id = -1;
 	data->dma.tx_chan_id = -1;
 	data->dma.rx_param = data;

@@ -451,6 +457,9 @@ static int dw8250_remove(struct platform_device *pdev)
 
 	serial8250_unregister_port(data->line);
 
+	if (!IS_ERR(data->rst))
+		reset_control_assert(data->rst);
+
 	if (!IS_ERR(data->clk))
 		clk_disable_unprepare(data->clk);
 

2.0.1

The 8250_dw driver fails to probe if the specified clock isn't registered at probe time. Even if a clock frequency is given, the required clock might be gated because it wasn't properly enabled.

This happened to me when the device is registered through DT, and the clock was part of an MFD, the PRCM found on A31 and A23 SoCs. Unlike core clocks that are registered with OF_CLK_DECLARE, which happen almost immediately after the kernel starts, the clocks are registered as sub-devices of the PRCM MFD platform device. Even though devices are registered in the order they are found in the DT, the drivers are registered in a different, arbitrary order. It is possible that the 8250_dw driver is registered, and thus associated with the device and probed, before the clock driver is registered and probed.

8250_dw then reports unable to get the clock, and fails. Without a working console, the kernel panics.

This patch adds support for deferred probe handling for the clock and reset controller.

---
 drivers/tty/serial/8250/8250_dw.c | 4 ++++
 1 file changed, 4 insertions(+)

index cb1b3dc..d9eeed7 100644
@@ -405,12 +405,16 @@ static int dw8250_probe(struct platform_device *pdev)
 
 	data->usr_reg = DW_UART_USR;
 	data->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
+		return -EPROBE_DEFER;
 	if (!IS_ERR(data->clk)) {
 		clk_prepare_enable(data->clk);
 		uart.port.uartclk = clk_get_rate(data->clk);
 	}
 
 	data->rst = devm_reset_control_get_optional(&pdev->dev, NULL);
+	if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER)
+		return -EPROBE_DEFER;
 	if (!IS_ERR(data->rst))
 		reset_control_deassert(data->rst);
 

2.0.1

Select the MFD_SUN6I_PRCM option when sun8i arch is enabled in order to get the PRCM (Power/Reset/Clock Management) related drivers compiled.

Also select ARCH_HAS_RESET_CONTROLLER and RESET_CONTROLLER to make sure the reset controller drivers are compiled.

---
 arch/arm/mach-sunxi/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

index f776c5f..6434e3b 100644
@@ -38,6 +38,9 @@ config MACH_SUN7I
 config MACH_SUN8I
 	bool "Allwinner A23 (sun8i) SoCs support"
 	default ARCH_SUNXI
+	select ARCH_HAS_RESET_CONTROLLER
 	select ARM_GIC
+	select MFD_SUN6I_PRCM
+	select RESET_CONTROLLER
 
 endif

2.0.1

Applied, thanks!
Maxime

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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With sun8i PRCM support available, we can add the PRCM clock and reset controller nodes to the DTSI. Also update R_UART's clock phandle and add it's reset control phandle.

---
 arch/arm/boot/dts/sun8i-a23.dtsi | 48 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 47 insertions(+), 1 deletion(-)

index 79c4083..e10c708 100644
@@ -262,13 +262,59 @@
 			interrupts = <1 9 0xf04>;
 		};
 
+		prcm at 01f01400 {
+			compatible = "allwinner,sun8i-a23-prcm";
+			reg = <0x01f01400 0x200>;
+
+			ar100: ar100_clk {
+				compatible = "fixed-factor-clock";
+				#clock-cells = <0>;
+				clock-div = <1>;
+				clock-mult = <1>;
+				clocks = <&osc24M>;
+				clock-output-names = "ar100";
+			};
+
+			ahb0: ahb0_clk {
+				compatible = "fixed-factor-clock";
+				#clock-cells = <0>;
+				clock-div = <1>;
+				clock-mult = <1>;
+				clocks = <&ar100>;
+				clock-output-names = "ahb0";
+			};
+
+			apb0: apb0_clk {
+				compatible = "allwinner,sun8i-a23-apb0-clk";
+				#clock-cells = <0>;
+				clocks = <&ahb0>;
+				clock-output-names = "apb0";
+			};
+
+			apb0_gates: apb0_gates_clk {
+				compatible = "allwinner,sun8i-a23-apb0-gates-clk";
+				#clock-cells = <1>;
+				clocks = <&apb0>;
+				clock-indices = <0>, <2>, <3>, <4>, <6>;
+				clock-output-names = "apb0_pio", "apb0_timer",
+						"apb0_rsb", "apb0_uart",
+						"apb0_i2c";
+			};
+
+			apb0_rst: apb0_rst {
+				compatible = "allwinner,sun6i-a31-clock-reset";
+				#reset-cells = <1>;
+			};
+		};
+
 		r_uart: serial at 01f02800 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01f02800 0x400>;
 			interrupts = <0 38 4>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&osc24M>;
+			clocks = <&apb0_gates 4>;
+			resets = <&apb0_rst 4>;
 			status = "disabled";
 		};
 	};

2.0.1

Hi Chen-Yu,

It looks mostly fine but...

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Hi,

Sure. Do you prefer a separate driver for sun8i-a23-apb0-gates as well? If so, then the mfd driver needs to be updated with the new driver name as well. I'll then do a separate patch to remove the cllock-indices code from the A31 driver.

Cheers
ChenYu

The A23 has the same MMIO reset controllers matching the clocks gates, just like in the A31. This patch adds the reset controller nodes and the reset control phandles for the peripherals needing them to the DTSI.

Unlike the sun6i DTSI, this patch uses sun6i-a31-clock-reset for ahb1_rst. sun6i-a31-ahb-reset is for early init, and requires some additions to the machine code. It is used to support the hstimer. However the hstimer on sun8i only has 1 timer, which is somewhat useless. Support for it will probably not be added. Hence the decision to use sun6i-a31-clock-reset here to avoid the changes to sun8i machine code.

---
 arch/arm/boot/dts/sun8i-a23.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

index e10c708..7d47933 100644
@@ -187,6 +187,24 @@
 		#size-cells = <1>;
 		ranges;
 
+		ahb1_rst: reset at 01c202c0 {
+			#reset-cells = <1>;
+			compatible = "allwinner,sun6i-a31-clock-reset";
+			reg = <0x01c202c0 0xc>;
+		};
+
+		apb1_rst: reset at 01c202d0 {
+			#reset-cells = <1>;
+			compatible = "allwinner,sun6i-a31-clock-reset";
+			reg = <0x01c202d0 0x4>;
+		};
+
+		apb2_rst: reset at 01c202d8 {
+			#reset-cells = <1>;
+			compatible = "allwinner,sun6i-a31-clock-reset";
+			reg = <0x01c202d8 0x4>;
+		};
+
 		timer at 01c20c00 {
 			compatible = "allwinner,sun4i-a10-timer";
 			reg = <0x01c20c00 0xa0>;

@@ -208,6 +226,7 @@
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			clocks = <&apb2_gates 16>;
+			resets = <&apb2_rst 16>;
 			status = "disabled";
 		};
 

@@ -218,6 +237,7 @@
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			clocks = <&apb2_gates 17>;
+			resets = <&apb2_rst 17>;
 			status = "disabled";
 		};
 

@@ -228,6 +248,7 @@
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			clocks = <&apb2_gates 18>;
+			resets = <&apb2_rst 18>;
 			status = "disabled";
 		};
 

@@ -238,6 +259,7 @@
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			clocks = <&apb2_gates 19>;
+			resets = <&apb2_rst 19>;
 			status = "disabled";
 		};
 

@@ -248,6 +270,7 @@
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			clocks = <&apb2_gates 20>;
+			resets = <&apb2_rst 20>;
 			status = "disabled";
 		};
 

2.0.1

Applied, thanks!

Maxime

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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