Add support for Panasonic UniPhier SoCs/boards
Subsystems (5)
cover Add support for Panasonic UniPhier SoCs/boards
UniPhier is the SoC family developed by Panasonic Corporation, based on ARM Cortex-A9.
This patch set adds its SoC/board support code with some drivers.
This series depends on the Denali NAND driver patch:
http://patchwork.ozlabs.org/patch/357717/
It must be applied first.
Masahiro Yamada (6):
nand: denali: add Denali NAND driver for SPL
serial: add UniPhier serial driver
arm: uniphier: add UniPhier SoC suppurt code
arm: uniphier: add UniPhier config headers
arm: uniphier: add board entries to boards.cfg
git-mailrc: add me as the maintainer of UniPhier SoCs
arch/arm/cpu/armv7/uniphier/Makefile | 23 + arch/arm/cpu/armv7/uniphier/board_common.c | 32 + arch/arm/cpu/armv7/uniphier/board_late_init.c | 37 + arch/arm/cpu/armv7/uniphier/cache_uniphier.c | 154 +++ arch/arm/cpu/armv7/uniphier/cmd_pinmon.c | 33 + arch/arm/cpu/armv7/uniphier/cpu_info.c | 59 ++ arch/arm/cpu/armv7/uniphier/dram_init.c | 37 + arch/arm/cpu/armv7/uniphier/init_page_table.c | 1068 ++++++++++++++++++++ arch/arm/cpu/armv7/uniphier/lowlevel_init.S | 159 +++ arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile | 10 + arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c | 33 + arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c | 16 + .../armv7/uniphier/ph1-ld4/board_postclk_init.c | 42 + arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c | 29 + arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c | 63 ++ arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c | 189 ++++ arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c | 44 + arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c | 28 + arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c | 10 + arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile | 10 + arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c | 16 + .../armv7/uniphier/ph1-pro4/board_postclk_init.c | 39 + arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c | 66 ++ arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c | 29 + arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c | 45 + arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c | 168 +++ .../arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c | 18 + arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c | 75 ++ arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c | 28 + arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c | 10 + arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile | 10 + arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c | 16 + .../armv7/uniphier/ph1-sld8/board_postclk_init.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c | 29 + arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c | 57 ++ arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c | 201 ++++ .../arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c | 51 + arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c | 10 + arch/arm/cpu/armv7/uniphier/reset.c | 29 + arch/arm/cpu/armv7/uniphier/smp.S | 54 + arch/arm/cpu/armv7/uniphier/spl.c | 17 + arch/arm/cpu/armv7/uniphier/support_card.c | 180 ++++ arch/arm/cpu/armv7/uniphier/timer.c | 39 + arch/arm/include/asm/arch-uniphier/arm-mpcore.h | 46 + arch/arm/include/asm/arch-uniphier/bcu-regs.h | 29 + arch/arm/include/asm/arch-uniphier/board.h | 35 + arch/arm/include/asm/arch-uniphier/boot-device.h | 20 + arch/arm/include/asm/arch-uniphier/led.h | 101 ++ arch/arm/include/asm/arch-uniphier/sbc-regs.h | 107 ++ arch/arm/include/asm/arch-uniphier/sc-regs.h | 62 ++ arch/arm/include/asm/arch-uniphier/sg-regs.h | 182 ++++ arch/arm/include/asm/arch-uniphier/ssc-regs.h | 65 ++ boards.cfg | 3 + doc/git-mailrc | 2 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/denali_spl.c | 201 ++++ drivers/serial/Makefile | 1 + drivers/serial/serial.c | 2 + drivers/serial/serial_uniphier.c | 206 ++++ include/configs/ph1_ld4.h | 64 ++ include/configs/ph1_pro4.h | 66 ++ include/configs/ph1_sld8.h | 64 ++ include/configs/uniphier-common.h | 275 +++++ 69 files changed, 4802 insertions(+) create mode 100644 arch/arm/cpu/armv7/uniphier/Makefile create mode 100644 arch/arm/cpu/armv7/uniphier/board_common.c create mode 100644 arch/arm/cpu/armv7/uniphier/board_late_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/cache_uniphier.c create mode 100644 arch/arm/cpu/armv7/uniphier/cmd_pinmon.c create mode 100644 arch/arm/cpu/armv7/uniphier/cpu_info.c create mode 100644 arch/arm/cpu/armv7/uniphier/dram_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/init_page_table.c create mode 100644 arch/arm/cpu/armv7/uniphier/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/reset.c create mode 100644 arch/arm/cpu/armv7/uniphier/smp.S create mode 100644 arch/arm/cpu/armv7/uniphier/spl.c create mode 100644 arch/arm/cpu/armv7/uniphier/support_card.c create mode 100644 arch/arm/cpu/armv7/uniphier/timer.c create mode 100644 arch/arm/include/asm/arch-uniphier/arm-mpcore.h create mode 100644 arch/arm/include/asm/arch-uniphier/bcu-regs.h create mode 100644 arch/arm/include/asm/arch-uniphier/board.h create mode 100644 arch/arm/include/asm/arch-uniphier/boot-device.h create mode 100644 arch/arm/include/asm/arch-uniphier/led.h create mode 100644 arch/arm/include/asm/arch-uniphier/sbc-regs.h create mode 100644 arch/arm/include/asm/arch-uniphier/sc-regs.h create mode 100644 arch/arm/include/asm/arch-uniphier/sg-regs.h create mode 100644 arch/arm/include/asm/arch-uniphier/ssc-regs.h create mode 100644 drivers/mtd/nand/denali_spl.c create mode 100644 drivers/serial/serial_uniphier.c create mode 100644 include/configs/ph1_ld4.h create mode 100644 include/configs/ph1_pro4.h create mode 100644 include/configs/ph1_sld8.h create mode 100644 include/configs/uniphier-common.h
Signature · 1 line
1.9.1
PATCH 1/6 nand: denali: add Denali NAND driver for SPL
The SPL-mode driver for Denali(Cadence) NAND Flash Memory Controller IP.
This driver requires two CONFIG macros:
- CONFIG_NAND_DENALI
Define to enable this driver.
- CONFIG_SYS_NAND_BAD_BLOCK_POS
Specify bad block mark position in the oob space. Typically 0.
---
drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/denali_spl.c | 201 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 202 insertions(+) create mode 100644 drivers/mtd/nand/denali_spl.c
drivers/mtd/nand/Makefile +1 -0
@@ -66,6 +66,7 @@ obj-$(CONFIG_NAND_DOCG4) += docg4.o else # minimal SPL drivers +obj-$(CONFIG_NAND_DENALI) += denali_spl.o obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
drivers/mtd/nand/denali_spl.c new file +201 -0
201 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH 1/6 nand: denali: add Denali NAND driver for SPL
Quoted 11 lines · Masahiro Yamada
The SPL-mode driver for Denali(Cadence) NAND Flash Memory Controller IP.
This driver requires two CONFIG macros:
-CONFIG_NAND_DENALI
Define to enable this driver.
-CONFIG_SYS_NAND_BAD_BLOCK_POS
Specify bad block mark position in the oob space. Typically 0.Signed-off-by Masahiro Yamada <[email protected]>Cc Chin Liang See <[email protected]>Cc Scott Wood <[email protected]>
[...]
drivers/mtd/nand/denali_spl.c line 67
Quoted 9 lines
drivers/mtd/nand/denali_spl.c new file +9
-0+static void read_data_from_flash_mem (uint8_t *buf,int len) +{ +int i; +uint32_t *buf32; + +/* transfer the data from the flash */ + buf32 = (uint32_t *)buf; +for (i =0 ; i < len /4 ; i++) + *buf32++ =readl (denali_flash_mem +INDEX_DATA_REG );
Won't this trigger unaligned access if $buf is not aligned to 4-byte boundary ?
Quoted 10 lines
drivers/mtd/nand/denali_spl.c new file +10
-0+} + +int denali_send_pipeline_cmd (int page,int ecc_en,int access_type) +{ +uint32_t addr, cmd; +static uint32_t page_count =1 ; + +writel (ecc_en, denali_flash_reg +ECC_ENABLE ); + +/* clear all bits of intr_status. */
drivers/mtd/nand/denali_spl.c line 87
Quoted 10 lines
drivers/mtd/nand/denali_spl.c new file +10
-0+writel (0xffff , denali_flash_reg +INTR_STATUS (flash_bank)); + + addr =BANK (flash_bank) | page; + +/* setup the acccess type */ + cmd =MODE_10 | addr; +index_addr (cmd, access_type); + +/* setup the pipeline command */ +index_addr (cmd,0x2000 | page_count);
Magic value 0x2000 should be fixed here.
drivers/mtd/nand/denali_spl.c line 90
Quoted 2 lines
drivers/mtd/nand/denali_spl.c new file +2
-0+ cmd =MODE_01 | addr; +writel (cmd, denali_flash_mem +INDEX_CTRL_REG );
Somehow, eventually, this should be migrated to "struct" based register access instead of such offset computation. If you feel like doing it, that'd be nice ;-)
Review
Quoted 2 lines
(quoted diff) +2
-0+ return wait_for_irq(INTR_STATUS__LOAD_COMP); +}
[...]
Thanks!
PATCH 1/6 nand: denali: add Denali NAND driver for SPL
Hi Marek,
Quoted 12 lines · On Fri, 4 Jul 2014 16:34:11 +0200 Marek Vasut <[email protected]> wrote:
drivers/mtd/nand/denali_spl.c line 67
Quoted 10 lines
drivers/mtd/nand/denali_spl.c new file +9
-0+static void read_data_from_flash_mem (uint8_t *buf,int len) +{ +int i; +uint32_t *buf32; + +/* transfer the data from the flash */ + buf32 = (uint32_t *)buf; +for (i =0 ; i < len /4 ; i++) + *buf32++ =readl (denali_flash_mem +INDEX_DATA_REG );Won't this trigger unaligned access if $buf is not aligned to 4-byte boundary ?
Thanks for catching this.
Actually, it would seldom happen because the aligned load address is generally given.
But I will add a sanity check here in v2, just in case.
Quoted 5 lines
drivers/mtd/nand/denali_spl.c line 87
Quoted 3 lines
drivers/mtd/nand/denali_spl.c new file +3
-0+ +/* setup the pipeline command */ +index_addr (cmd,0x2000 | page_count);Magic value
0x2000should be fixed here.
Actually, this part is the same as that of the normal Denali driver by Chin Liang See
http://patchwork.ozlabs.org/patch/357717/
Moreover, it is the same as in Linux Kernel.
I understand what you mean, but I guess we can excuse here.
Quoted 6 lines
drivers/mtd/nand/denali_spl.c line 90
Quoted 2 lines
drivers/mtd/nand/denali_spl.c new file +2
-0+ cmd =MODE_01 | addr; +writel (cmd, denali_flash_mem +INDEX_CTRL_REG );Somehow, eventually, this should be migrated to "struct" based register access instead of such offset computation. If you feel like doing it, that'd be nice ;-)
Dito.
I am following the coding style of the normal Denali driver and the Linux one.
We might perhaps do that migration as the separated task in future, but not now.
Best Regards
Masahiro Yamada
PATCH 1/6 nand: denali: add Denali NAND driver for SPL
Quoted 1 line · Masahiro Yamada
Hi Marek,
Hi!
Quoted 16 lines
On Fri, 4 Jul 2014 16:34:11 +0200
Quoted 4 lines · Marek Vasut
Quoted 4 lines
drivers/mtd/nand/denali_spl.c new file +4
-0+static void read_data_from_flash_mem (uint8_t *buf,int len) +{ +int i; +uint32_t *buf32;Quoted 8 lines
drivers/mtd/nand/denali_spl.c line 67
Quoted 5 lines
drivers/mtd/nand/denali_spl.c new file +5
-0+ +/* transfer the data from the flash */ + buf32 = (uint32_t *)buf; +for (i =0 ; i < len /4 ; i++) + *buf32++ =readl (denali_flash_mem +INDEX_DATA_REG );Won't this trigger unaligned access if $buf is not aligned to 4-byte boundary ?
Quoted 6 lines
Thanks for catching this.
Actually, it would seldom happen because the aligned load address is generally given.
But I will add a sanity check here in v2, just in case.
Or just use put_unaligned() ?
Quoted 6 lines
Quoted 5 lines
drivers/mtd/nand/denali_spl.c line 87
Quoted 3 lines
drivers/mtd/nand/denali_spl.c new file +3
-0+ +/* setup the pipeline command */ +index_addr (cmd,0x2000 | page_count);Magic value
0x2000should be fixed here.
Quoted 7 lines
Actually, this part is the same as that of the normal Denali driver by Chin Liang See
http://patchwork.ozlabs.org/patch/357717/Moreover, it is the same as in Linux Kernel.
I understand what you mean, but I guess we can excuse here.
OK, I see. Is there any chance to fix this in Linux maybe eventually?
[...]
Best regards,
Marek Vasut
PATCH 1/6 nand: denali: add Denali NAND driver for SPL
Hi Marek,
Quoted 17 lines · On Thu, 10 Jul 2014 12:10:25 +0200 Marek Vasut <[email protected]> wrote:
Quoted 17 lines
On Fri, 4 Jul 2014 16:34:11 +0200
Quoted 12 lines · Marek Vasut
drivers/mtd/nand/denali_spl.c line 67
Quoted 9 lines
drivers/mtd/nand/denali_spl.c new file +9
-0+static void read_data_from_flash_mem (uint8_t *buf,int len) +{ +int i; +uint32_t *buf32; + +/* transfer the data from the flash */ + buf32 = (uint32_t *)buf; +for (i =0 ; i < len /4 ; i++) + *buf32++ =readl (denali_flash_mem +INDEX_DATA_REG );Won't this trigger unaligned access if $buf is not aligned to 4-byte boundary ?
Quoted 8 lines
Quoted 6 lines
Thanks for catching this.
Actually, it would seldom happen because the aligned load address is generally given.
But I will add a sanity check here in v2, just in case.
Or just use
put_unaligned()?
Oh, year! put_unaligned() would be better.
Thanks!
Quoted 10 lines
Quoted 10 lines
Quoted 5 lines
drivers/mtd/nand/denali_spl.c line 87
Quoted 3 lines
drivers/mtd/nand/denali_spl.c new file +3
-0+ +/* setup the pipeline command */ +index_addr (cmd,0x2000 | page_count);Magic value
0x2000should be fixed here.Actually, this part is the same as that of the normal Denali driver by Chin Liang See
http://patchwork.ozlabs.org/patch/357717/
Quoted 6 lines
Quoted 3 lines
Moreover, it is the same as in Linux Kernel.
I understand what you mean, but I guess we can excuse here.
OK, I see. Is there any chance to fix this in Linux maybe eventually?
OK.
I will send a patch to linux-mtd ML
to use "#define PIPELINE_ACCESS 2000"
Best Regards
Masahiro Yamada
PATCH 1/6 nand: denali: add Denali NAND driver for SPL
Quoted 1 line · Masahiro Yamada
Hi Marek,
Hi!
[...]
Quoted 17 lines
Quoted 1 line
Or just use
put_unaligned()?Oh, year!
put_unaligned()would be better.
Thanks!Quoted 12 lines
Quoted 12 lines
Quoted 5 lines
drivers/mtd/nand/denali_spl.c line 87
Quoted 3 lines
drivers/mtd/nand/denali_spl.c new file +3
-0+ +/* setup the pipeline command */ +index_addr (cmd,0x2000 | page_count);Magic value
0x2000should be fixed here.Actually, this part is the same as that of the normal Denali driver by Chin Liang See
http://patchwork.ozlabs.org/patch/357717/Moreover, it is the same as in Linux Kernel.
Quoted 7 lines
Quoted 3 lines
Quoted 1 line
I understand what you mean, but I guess we can excuse here.
OK, I see. Is there any chance to fix this in Linux maybe eventually?
OK.
I will send a patch to linux-mtd ML
to use "#definePIPELINE_ACCESS2000"
Ack on both, thank you !
Best regards,
Marek Vasut
PATCH 1/6 nand: denali: add Denali NAND driver for SPL
Hi Marek,
Quoted 14 lines · On Thu, 10 Jul 2014 13:30:38 +0200 Marek Vasut <[email protected]> wrote:
Quoted 14 lines
Quoted 14 lines
Quoted 13 lines
Quoted 5 lines
drivers/mtd/nand/denali_spl.c line 87
Quoted 3 lines
drivers/mtd/nand/denali_spl.c new file +3
-0+ +/* setup the pipeline command */ +index_addr (cmd,0x2000 | page_count);Magic value
0x2000should be fixed here.Actually, this part is the same as that of the normal Denali driver by Chin Liang See
http://patchwork.ozlabs.org/patch/357717/Moreover, it is the same as in Linux Kernel.
I understand what you mean, but I guess we can excuse here.
Quoted 7 lines
Quoted 5 lines
Quoted 1 line
OK, I see. Is there any chance to fix this in Linux maybe eventually?
OK.
I will send a patch to linux-mtd ML
to use "#definePIPELINE_ACCESS2000"Ack on both, thank you !
Done.
http://patchwork.ozlabs.org/patch/368933/
Best Regards
Masahiro Yamada
PATCH 2/6 serial: add UniPhier serial driver
In reply to Masahiro YamadaThe driver for on-chip UART used on Panasonic UniPhier platform.
---
drivers/serial/Makefile | 1 + drivers/serial/serial.c | 2 + drivers/serial/serial_uniphier.c | 206 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 209 insertions(+) create mode 100644 drivers/serial/serial_uniphier.c
drivers/serial/Makefile +1 -0
@@ -34,6 +34,7 @@ obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o obj-$(CONFIG_MXS_AUART) += mxs_auart.o obj-$(CONFIG_ARC_SERIAL) += serial_arc.o +obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o
drivers/serial/serial.c +2 -0
@@ -157,6 +157,7 @@ serial_initfunc(sh_serial_initialize);serial_initfunc (arm_dcc_initialize);serial_initfunc (mxs_auart_initialize);serial_initfunc (arc_serial_initialize); +serial_initfunc (uniphier_serial_initialize);/** * serial_register() - Register serial driver with serial driver core
@@ -250,6 +251,7 @@ void serial_initialize(void)arm_dcc_initialize ();mxs_auart_initialize ();arc_serial_initialize (); +uniphier_serial_initialize ();serial_assign (default_serial_console ()->name); }
drivers/serial/serial_uniphier.c new file +206 -0
206 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH 2/6 serial: add UniPhier serial driver
Quoted 3 lines · Masahiro Yamada
The driver for on-chip UART used on Panasonic UniPhier platform.
Signed-off-by Masahiro Yamada <[email protected]>
[...]
drivers/serial/serial_uniphier.c line 57
Quoted 5 lines
drivers/serial/serial_uniphier.c new file +5
-0+static void uniphier_serial_init (struct uniphier_serial *port) +{ +writeb (UART_LCR_WLS_8 , &port->lcr); + +#define MODE_X_DIV 16
You can use just const unsigned here instead of #define.
Quoted 30 lines
drivers/serial/serial_uniphier.c new file +29
-0+ +/* Compute divisor value. Normally, we should simply return: +* CONFIG_SYS_NS16550_CLK) / MODE_X_DIV / gd->baudrate +* but we need to round that value by adding 0.5. +* Rounding is especially important at high baud rates. +*/ +writew ((CONFIG_SYS_UNIPHIER_UART_CLK + (gd->baudrate * + (MODE_X_DIV /2 ))) / (MODE_X_DIV * gd->baudrate), &port->dlr); +} + +static void uniphier_serial_setbrg (struct uniphier_serial *port) +{ +uniphier_serial_init (port); +} + +static int uniphier_serial_tstc (struct uniphier_serial *port) +{ +return (readb (&port->lsr) &UART_LSR_DR ) !=0 ; +} + +static int uniphier_serial_getc (struct uniphier_serial *port) +{ +while (!uniphier_serial_tstc (port)) + ; + +return readb (&port->rbr); +} + +static void uniphier_serial_putc(struct uniphier_serial *port, const charc) +{
drivers/serial/serial_uniphier.c line 92
Quoted 5 lines
drivers/serial/serial_uniphier.c new file +5
-0+if (c =='\n' ) +uniphier_serial_putc (port,'\r' ); + +while (!(readb (&port->lsr) &UART_LSR_THRE )) + ;
I think in this function, you can avoid such completely unbounded loop.
[...]
Best regard,
Marek Vasut
PATCH 2/6 serial: add UniPhier serial driver
Hi Marek,
Quoted 7 lines · On Fri, 4 Jul 2014 16:40:29 +0200 Marek Vasut <[email protected]> wrote:
drivers/serial/serial_uniphier.c line 57
Quoted 5 lines
drivers/serial/serial_uniphier.c new file +5
-0+static void uniphier_serial_init (struct uniphier_serial *port) +{ +writeb (UART_LCR_WLS_8 , &port->lcr); + +#define MODE_X_DIV 16You can use just const unsigned here instead of #define.
I adjusted drivers/serial/serial_ns16550.c for my own.
Is using a macro here so bad?
If so, should I also fix the line 138 of drivers/serial/serial_ns16550.c ?
Quoted 11 lines
drivers/serial/serial_uniphier.c line 92
Quoted 7 lines
+static void uniphier_serial_putc(struct
uniphier_serial*port, const char
c) +{drivers/serial/serial_uniphier.c new file +5
-0+if (c =='\n' ) +uniphier_serial_putc (port,'\r' ); + +while (!(readb (&port->lsr) &UART_LSR_THRE )) + ;I think in this function, you can avoid such completely unbounded loop.
[...]
Why?
Could you give me more detailed explanation?
Best Regards
Masahiro Yamada
PATCH 2/6 serial: add UniPhier serial driver
Quoted 14 lines · Masahiro Yamada
Hi Marek,
On Fri, 4 Jul 2014 16:40:29 +0200
Quoted 7 lines · Marek Vasut
drivers/serial/serial_uniphier.c line 57
Quoted 5 lines
drivers/serial/serial_uniphier.c new file +5
-0+static void uniphier_serial_init (struct uniphier_serial *port) +{ +writeb (UART_LCR_WLS_8 , &port->lcr); + +#define MODE_X_DIV 16You can use just const unsigned here instead of #define.
Quoted 4 lines
I adjusted
drivers/serial/serial_ns16550.cfor my own.Is using a macro here so bad?
If so, should I also fix the line 138 ofdrivers/serial/serial_ns16550.c?
You're loosing the typechecking, that's all.
Quoted 10 lines
Quoted 10 lines
drivers/serial/serial_uniphier.c line 92
Quoted 7 lines
+static void
uniphier_serial_putc(struct uniphier_serial *port, const char c)+{drivers/serial/serial_uniphier.c new file +5
-0+if (c =='\n' ) +uniphier_serial_putc (port,'\r' ); + +while (!(readb (&port->lsr) &UART_LSR_THRE )) + ;I think in this function, you can avoid such completely unbounded loop.
Quoted 4 lines
Quoted 1 line
[...]
Why?
Could you give me more detailed explanation?
In case the LSR_THRE bit would never get cleared, this loop would keep spinning forever. On the other hand, if there was some kind of a timeout, U-Boot would be able to continue doing at least something when exiting this loop by timing out. Though you're right that something would most likely have gone really bonkers if this LSR_THRE never got cleared.
Best regards,
Marek Vasut
PATCH 2/6 serial: add UniPhier serial driver
Hi Marek,
Quoted 13 lines · On Thu, 10 Jul 2014 12:14:35 +0200 Marek Vasut <[email protected]> wrote:
Quoted 13 lines
Quoted 12 lines
drivers/serial/serial_uniphier.c line 92
Quoted 8 lines
+static void
uniphier_serial_putc(struct uniphier_serial *port, const char c)+{drivers/serial/serial_uniphier.c new file +5
-0+if (c =='\n' ) +uniphier_serial_putc (port,'\r' ); + +while (!(readb (&port->lsr) &UART_LSR_THRE )) + ;I think in this function, you can avoid such completely unbounded loop.
[...]
Quoted 9 lines
Quoted 2 lines
Why?
Could you give me more detailed explanation?In case the
LSR_THREbit would never get cleared, this loop would keep spinning forever. On the other hand, if there was some kind of a timeout, U-Boot would be able to continue doing at least something when exiting this loop by timing out. Though you're right that something would most likely have gone really bonkers if thisLSR_THREnever got cleared.
I guess you mentioned the case where the flow control with CTS/RTS results in the dead lock.
I am not sure if we need to be so careful.
Is there any other UART driver using timeout check?
(What would U-Boot continue to do in case console cannot display the error message?)
Best Regards
Masahiro Masahiro
PATCH 2/6 serial: add UniPhier serial driver
Quoted 1 line · Masahiro Yamada
Hi Marek,
Hi!
Quoted 26 lines
On Thu, 10 Jul 2014 12:14:35 +0200
Quoted 16 lines · Marek Vasut
Quoted 11 lines
Quoted 11 lines
drivers/serial/serial_uniphier.c line 92
Quoted 7 lines
+static void
uniphier_serial_putc(struct uniphier_serial *port, const char c)+{drivers/serial/serial_uniphier.c new file +5
-0+if (c =='\n' ) +uniphier_serial_putc (port,'\r' ); + +while (!(readb (&port->lsr) &UART_LSR_THRE )) + ;I think in this function, you can avoid such completely unbounded loop.
Quoted 4 lines
Quoted 1 line
[...]
Why?
Could you give me more detailed explanation?Quoted 6 lines
In case the
LSR_THREbit would never get cleared, this loop would keep spinning forever. On the other hand, if there was some kind of a timeout, U-Boot would be able to continue doing at least something when exiting this loop by timing out. Though you're right that something would most likely have gone really bonkers if thisLSR_THREnever got cleared.
Quoted 2 lines
I guess you mentioned the case where the flow control with CTS/RTS results in the dead lock.
Either that or plain hardware failure.
Quoted 3 lines
I am not sure if we need to be so careful.
Is there any other UART driver using timeout check?
I don't know. If you feel this is not needed, then please just ignore my suggestion. I'm just pushing the usual "let's not do unbounded loops where reasonable" thing here ;-)
Quoted 2 lines
(What would U-Boot continue to do in case console cannot display the error message?)
It can still boot kernel, even if it cannot print on console.
Best regards,
Marek Vasut
PATCH 2/6 serial: add UniPhier serial driver
Hi Marek,
Quoted 40 lines · On Thu, 10 Jul 2014 14:37:18 +0200 Marek Vasut <[email protected]> wrote:
Quoted 1 line · Masahiro Yamada
Hi Marek,
Hi!
Quoted 26 lines
On Thu, 10 Jul 2014 12:14:35 +0200
Quoted 16 lines · Marek Vasut
Quoted 11 lines
Quoted 11 lines
drivers/serial/serial_uniphier.c line 92
Quoted 7 lines
+static void
uniphier_serial_putc(struct uniphier_serial *port, const char c)+{drivers/serial/serial_uniphier.c new file +5
-0+if (c =='\n' ) +uniphier_serial_putc (port,'\r' ); + +while (!(readb (&port->lsr) &UART_LSR_THRE )) + ;I think in this function, you can avoid such completely unbounded loop.
Quoted 4 lines
Quoted 1 line
[...]
Why?
Could you give me more detailed explanation?Quoted 6 lines
In case the
LSR_THREbit would never get cleared, this loop would keep spinning forever. On the other hand, if there was some kind of a timeout, U-Boot would be able to continue doing at least something when exiting this loop by timing out. Though you're right that something would most likely have gone really bonkers if thisLSR_THREnever got cleared.Quoted 2 lines
I guess you mentioned the case where the flow control with CTS/RTS results in the dead lock.
Either that or plain hardware failure.
Quoted 3 lines
I am not sure if we need to be so careful.
Is there any other UART driver using timeout check?
Quoted 9 lines
I don't know. If you feel this is not needed, then please just ignore my suggestion. I'm just pushing the usual "let's not do unbounded loops where reasonable" thing here ;-)
Quoted 2 lines
(What would U-Boot continue to do in case console cannot display the error message?)
It can still boot kernel, even if it cannot print on console.
Finally, I decided to keep this as is because:
[1] Our on-chip UART do not have the flow control feature. It uses only TX/RX signals.
[2] So, the eternal loop occurrs only when the hardware is broken. In this case, the situation is really fatal and I don't think it is reasonable to continue to do something.
[3] I checked some (but not all) other serial drivers but I could not find ones using timeout and break thing.
Best Regards
Masahiro Yamada
PATCH 2/6 serial: add UniPhier serial driver
On Friday, July 11, 2014 at 07:37:13 AM, Masahiro Yamada wrote:
[...]
Quoted 7 lines
Quoted 1 line
It can still boot kernel, even if it cannot print on console.
Finally, I decided to keep this as is because:
[1] Our on-chip UART do not have the flow control feature. It uses only TX/RX signals.
Quoted 6 lines
[2] So, the eternal loop occurrs only when the hardware is broken. In this case, the situation is really fatal and I don't think it is reasonable to continue to do something.
[3] I checked some (but not all) other serial drivers but I could not find ones using timeout and break thing.
Hi!
All right then.
Best regards,
Marek Vasut
PATCH 3/6 arm: uniphier: add UniPhier SoC suppurt code
In reply to Masahiro YamadaThese are used by Panasonic UniPhier SoC family.
---
arch/arm/cpu/armv7/uniphier/Makefile | 23 + arch/arm/cpu/armv7/uniphier/board_common.c | 32 + arch/arm/cpu/armv7/uniphier/board_late_init.c | 37 + arch/arm/cpu/armv7/uniphier/cache_uniphier.c | 154 +++ arch/arm/cpu/armv7/uniphier/cmd_pinmon.c | 33 + arch/arm/cpu/armv7/uniphier/cpu_info.c | 59 ++ arch/arm/cpu/armv7/uniphier/dram_init.c | 37 + arch/arm/cpu/armv7/uniphier/init_page_table.c | 1068 ++++++++++++++++++++ arch/arm/cpu/armv7/uniphier/lowlevel_init.S | 159 +++ arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile | 10 + arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c | 33 + arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c | 16 + .../armv7/uniphier/ph1-ld4/board_postclk_init.c | 42 + arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c | 29 + arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c | 63 ++ arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c | 189 ++++ arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c | 44 + arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c | 28 + arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c | 10 + arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile | 10 + arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c | 16 + .../armv7/uniphier/ph1-pro4/board_postclk_init.c | 39 + arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c | 66 ++ arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c | 29 + arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c | 45 + arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c | 168 +++ .../arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c | 18 + arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c | 75 ++ arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c | 28 + arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c | 10 + arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile | 10 + arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c | 16 + .../armv7/uniphier/ph1-sld8/board_postclk_init.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c | 29 + arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c | 57 ++ arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c | 201 ++++ .../arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c | 51 + arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c | 10 + arch/arm/cpu/armv7/uniphier/reset.c | 29 + arch/arm/cpu/armv7/uniphier/smp.S | 54 + arch/arm/cpu/armv7/uniphier/spl.c | 17 + arch/arm/cpu/armv7/uniphier/support_card.c | 180 ++++ arch/arm/cpu/armv7/uniphier/timer.c | 39 + arch/arm/include/asm/arch-uniphier/arm-mpcore.h | 46 + arch/arm/include/asm/arch-uniphier/bcu-regs.h | 29 + arch/arm/include/asm/arch-uniphier/board.h | 35 + arch/arm/include/asm/arch-uniphier/boot-device.h | 20 + arch/arm/include/asm/arch-uniphier/led.h | 101 ++ arch/arm/include/asm/arch-uniphier/sbc-regs.h | 107 ++ arch/arm/include/asm/arch-uniphier/sc-regs.h | 62 ++ arch/arm/include/asm/arch-uniphier/sg-regs.h | 182 ++++ arch/arm/include/asm/arch-uniphier/ssc-regs.h | 65 ++ 58 files changed, 3917 insertions(+) create mode 100644 arch/arm/cpu/armv7/uniphier/Makefile create mode 100644 arch/arm/cpu/armv7/uniphier/board_common.c create mode 100644 arch/arm/cpu/armv7/uniphier/board_late_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/cache_uniphier.c create mode 100644 arch/arm/cpu/armv7/uniphier/cmd_pinmon.c create mode 100644 arch/arm/cpu/armv7/uniphier/cpu_info.c create mode 100644 arch/arm/cpu/armv7/uniphier/dram_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/init_page_table.c create mode 100644 arch/arm/cpu/armv7/uniphier/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/reset.c create mode 100644 arch/arm/cpu/armv7/uniphier/smp.S create mode 100644 arch/arm/cpu/armv7/uniphier/spl.c create mode 100644 arch/arm/cpu/armv7/uniphier/support_card.c create mode 100644 arch/arm/cpu/armv7/uniphier/timer.c create mode 100644 arch/arm/include/asm/arch-uniphier/arm-mpcore.h create mode 100644 arch/arm/include/asm/arch-uniphier/bcu-regs.h create mode 100644 arch/arm/include/asm/arch-uniphier/board.h create mode 100644 arch/arm/include/asm/arch-uniphier/boot-device.h create mode 100644 arch/arm/include/asm/arch-uniphier/led.h create mode 100644 arch/arm/include/asm/arch-uniphier/sbc-regs.h create mode 100644 arch/arm/include/asm/arch-uniphier/sc-regs.h create mode 100644 arch/arm/include/asm/arch-uniphier/sg-regs.h create mode 100644 arch/arm/include/asm/arch-uniphier/ssc-regs.h
arch/arm/cpu/armv7/uniphier/Makefile new file +23 -0
@@ -0,0 +1,23 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_SPL_BUILD) += lowlevel_init.o init_page_table.o +obj-$(CONFIG_SPL_BUILD) += spl.o + +obj-y += timer.o +obj-y += reset.o +obj-y += cache_uniphier.o +obj-y += dram_init.o +obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o +obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o +obj-$(CONFIG_UNIPHIER_SMP) += smp.o +obj-$(if $(CONFIG_SPL_BUILD),,y) += cmd_pinmon.o + +obj-y += board_common.o +obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o +obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o + +obj-$(CONFIG_PH1_LD4) += ph1-ld4/ +obj-$(CONFIG_PH1_PRO4) += ph1-pro4/ +obj-$(CONFIG_PH1_SLD8) += ph1-sld8/
arch/arm/cpu/armv7/uniphier/board_common.c new file +32 -0
@@ -0,0 +1,32 @@ +/* +* Copyright (C) 2012-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/arch/led.h> + +/* +* Routine: board_init +* Description: Early hardware init. +*/ +int board_init (void ) +{ +led_write (U ,B ,O ,O ); + +return 0 ; +} + +#if CONFIG_NR_DRAM_BANKS >=2 +void dram_init_banksize (void ) +{ +DECLARE_GLOBAL_DATA_PTR ; + + gd->bd->bi_dram[0 ].start =CONFIG_SDRAM0_BASE ; + gd->bd->bi_dram[0 ].size =CONFIG_SDRAM0_SIZE ; + gd->bd->bi_dram[1 ].start =CONFIG_SDRAM1_BASE ; + gd->bd->bi_dram[1 ].size =CONFIG_SDRAM1_SIZE ; +} +#endif
arch/arm/cpu/armv7/uniphier/board_late_init.c new file +37 -0
@@ -0,0 +1,37 @@ +/* +* Copyright (C) 2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <spl.h> +#include <nand.h> +#include <asm/io.h> +#include <../drivers/mtd/nand/denali.h> + +static void nand_denali_wp_disable (void ) +{ +void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE ; + +writel (WRITE_PROTECT__FLAG , denali_reg +WRITE_PROTECT ); +} + +int board_late_init (void ) +{ +puts ("MODE: " ); + +switch (spl_boot_device ()) { +case BOOT_DEVICE_NAND : +printf ("NAND Boot\n" ); +setenv ("bootmode" ,"nandboot" ); +nand_denali_wp_disable (); +break ; +default : +printf ("Unsupported Boot Mode\n" ); +return -1 ; + } + +return 0 ; +}
arch/arm/cpu/armv7/uniphier/cache_uniphier.c new file +154 -0
154 lines not on this page · raw message
arch/arm/cpu/armv7/uniphier/cmd_pinmon.c new file +33 -0
@@ -0,0 +1,33 @@ +/* +* Copyright (C) 2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/arch/boot-device.h> + +static int do_pinmon (cmd_tbl_t *cmdtp,int flag,int argc,char *const argv[]) +{ +struct boot_device_info *table; +u32 mode_sel, n =0 ; + + mode_sel =get_boot_mode_sel (); + +puts ("Boot Mode Pin:\n" ); + +for (table = boot_device_table;strlen (table->info); table++) { +printf (" %c %02x %s\n" , n == mode_sel ?'*' :' ' , n, + table->info); + n++; + } + +return 0 ; +} + +U_BOOT_CMD ( + pinmon,1 ,1 , do_pinmon, +"pin monitor" , +"" +);
arch/arm/cpu/armv7/uniphier/cpu_info.c new file +59 -0
59 lines not on this page · raw message
arch/arm/cpu/armv7/uniphier/dram_init.c new file +37 -0
@@ -0,0 +1,37 @@ +/* +* Copyright (C) 2012-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/arch/led.h> + +int umc_init (void ); +void enable_dpll_ssc (void ); + +int dram_init (void ) +{ +DECLARE_GLOBAL_DATA_PTR ; + gd->ram_size =CONFIG_SYS_SDRAM_SIZE ; + +#if !defined(CONFIG_SPL ) || defined(CONFIG_SPL_BUILD ) + led_write(B, 4, , ); + + { +int res; + + res =umc_init (); +if (res <0 ) +return res; + } + led_write(B, 5, , ); + +enable_dpll_ssc (); +#endif + + led_write(B, 6, , ); + +return 0 ; +}
arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1068 -0
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arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +159 -0
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arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile new file +10 -0
@@ -0,0 +1,10 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o +obj-y += boot-mode.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ + sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o +obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ + umc_init.o
arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c new file +33 -0
@@ -0,0 +1,33 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/bcu-regs.h> + +#define ch (x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) + +void bcu_init (void ) +{ +int shift; + +writel (0x44444444 ,BCSCR0 );/* 0x20000000-0x3fffffff: ASM bus */ +writel (0x11111111 ,BCSCR2 );/* 0x80000000-0x9fffffff: IPPC/IPPD-bus */ +writel (0x11111111 ,BCSCR3 );/* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */ +writel (0x11111111 ,BCSCR4 );/* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */ +writel (0x11111111 ,BCSCR5 );/* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */ + +/* Specify DDR channel */ + shift = (CONFIG_SDRAM1_BASE -CONFIG_SDRAM0_BASE ) /0x04000000 *4 ; +writel (ch (shift),BCIPPCCHR2 );/* 0x80000000-0x9fffffff */ + + shift -=32 ; +writel (ch (shift),BCIPPCCHR3 );/* 0xa0000000-0xbfffffff */ + + shift -=32 ; +writel (ch (shift),BCIPPCCHR4 );/* 0xc0000000-0xdfffffff */ +}
arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c new file +16 -0
@@ -0,0 +1,16 @@ +/* +* Copyright (C) 2012-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/arch/board.h> + +int checkboard (void ) +{ +puts ("Board: PH1-LD4 Board\n" ); + +return check_support_card (); +}
arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c new file +42 -0
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arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c new file +1 -0
@@ -0,0 +1 @@ +#include "../ph1-pro4/boot-mode.c"
arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c new file +29 -0
@@ -0,0 +1,29 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sc-regs.h> + +void clkrst_init (void ) +{ +u32 tmp; + +/* deassert reset */ + tmp =readl (SC_RSTCTRL ); + tmp |=SC_RSTCTRL_NRST_ETHER |SC_RSTCTRL_NRST_UMC1 + |SC_RSTCTRL_NRST_UMC0 |SC_RSTCTRL_NRST_NAND ; +writel (tmp,SC_RSTCTRL ); +readl (SC_RSTCTRL );/* dummy read */ + +/* privide clocks */ + tmp =readl (SC_CLKCTRL ); + tmp |=SC_CLKCTRL_CLK_ETHER |SC_CLKCTRL_CLK_MIO |SC_CLKCTRL_CLK_UMC + |SC_CLKCTRL_CLK_NAND |SC_CLKCTRL_CLK_SBC |SC_CLKCTRL_CLK_PERI ; +writel (tmp,SC_CLKCTRL ); +readl (SC_CLKCTRL );/* dummy read */ +}
arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c new file +63 -0
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arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c new file +189 -0
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arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c new file +1 -0
@@ -0,0 +1 @@ +#include "../ph1-pro4/pll_spectrum.c"
arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c new file +44 -0
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arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c new file +28 -0
@@ -0,0 +1,28 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sg-regs.h> + +void sg_init (void ) +{ +u32 tmp; + +/* Set DDR size */ + tmp =sg_memconf_val_ch0 (CONFIG_SDRAM0_SIZE ,CONFIG_DDR_NUM_CH0 ); + tmp |=sg_memconf_val_ch1 (CONFIG_SDRAM1_SIZE ,CONFIG_DDR_NUM_CH1 ); +#if CONFIG_SDRAM0_BASE +CONFIG_SDRAM0_SIZE <CONFIG_SDRAM1_BASE + tmp |=SG_MEMCONF_SPARSEMEM ; +#endif +writel (tmp,SG_MEMCONF ); + +/* Must enable in-port before deasserting reset signals of cores */ + tmp =readl (SG_IECTRL ); + tmp |=0x1 ; +writel (tmp,SG_IECTRL ); +}
arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c new file +10 -0
@@ -0,0 +1,10 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +int umc_init (void ) +{ +return 0 ; +}
arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile new file +10 -0
@@ -0,0 +1,10 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o +obj-y += boot-mode.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \ + sg_init.o pll_init.o clkrst_init.o pinctrl.o +obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ + umc_init.o
arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c new file +16 -0
@@ -0,0 +1,16 @@ +/* +* Copyright (C) 2012-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/arch/board.h> + +int checkboard (void ) +{ +puts ("Board: PH1-Pro4 Board\n" ); + +return check_support_card (); +}
arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c new file +39 -0
@@ -0,0 +1,39 @@ +/* +* Copyright (C) 2012-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/arch/led.h> +#include <asm/arch/board.h> + +void sbc_init (void ); +void sg_init (void ); +void pll_init (void ); +void pin_init (void ); +void clkrst_init (void ); + +int board_postclk_init (void ) +{ +sbc_init (); + +sg_init (); + +pll_init (); + +uniphier_board_init (); + + led_write(B, 1, , ); + +pin_init (); + + led_write(B, 2, , ); + +clkrst_init (); + + led_write(B, 3, , ); + +return 0 ; +}
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +66 -0
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arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c new file +29 -0
@@ -0,0 +1,29 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sc-regs.h> + +void clkrst_init (void ) +{ +u32 tmp; + +/* deassert reset */ + tmp =readl (SC_RSTCTRL ); + tmp |=SC_RSTCTRL_NRST_ETHER |SC_RSTCTRL_NRST_UMC1 + |SC_RSTCTRL_NRST_UMC0 |SC_RSTCTRL_NRST_NAND ; +writel (tmp,SC_RSTCTRL ); +readl (SC_RSTCTRL );/* dummy read */ + +/* privide clocks */ + tmp =readl (SC_CLKCTRL ); + tmp |=SC_CLKCTRL_CLK_ETHER |SC_CLKCTRL_CLK_MIO |SC_CLKCTRL_CLK_UMC + |SC_CLKCTRL_CLK_NAND |SC_CLKCTRL_CLK_SBC |SC_CLKCTRL_CLK_PERI ; +writel (tmp,SC_CLKCTRL ); +readl (SC_CLKCTRL );/* dummy read */ +}
arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c new file +45 -0
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arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c new file +168 -0
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arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c new file +18 -0
@@ -0,0 +1,18 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sc-regs.h> + +void enable_dpll_ssc (void ) +{ +u32 tmp; + + tmp =readl (SC_DPLLCTRL ); + tmp |=SC_DPLLCTRL_SSC_EN ; +writel (tmp,SC_DPLLCTRL ); +}
arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c new file +75 -0
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arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c new file +28 -0
@@ -0,0 +1,28 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sg-regs.h> + +void sg_init (void ) +{ +u32 tmp; + +/* Set DDR size */ + tmp =sg_memconf_val_ch0 (CONFIG_SDRAM0_SIZE ,CONFIG_DDR_NUM_CH0 ); + tmp |=sg_memconf_val_ch1 (CONFIG_SDRAM1_SIZE ,CONFIG_DDR_NUM_CH1 ); +#if CONFIG_SDRAM0_BASE +CONFIG_SDRAM0_SIZE <CONFIG_SDRAM1_BASE + tmp |=SG_MEMCONF_SPARSEMEM ; +#endif +writel (tmp,SG_MEMCONF ); + +/* Must enable in-port before deasserting reset signals of cores */ + tmp =readl (SG_IECTRL ); + tmp |=0x1 ; +writel (tmp,SG_IECTRL ); +}
arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c new file +10 -0
@@ -0,0 +1,10 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +int umc_init (void ) +{ +return 0 ; +}
arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile new file +10 -0
@@ -0,0 +1,10 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o +obj-y += boot-mode.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ + sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o +obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ + umc_init.o
arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c new file +1 -0
@@ -0,0 +1 @@ +#include "../ph1-ld4/bcu_init.c"
arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c new file +16 -0
@@ -0,0 +1,16 @@ +/* +* Copyright (C) 2012-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/arch/board.h> + +int checkboard (void ) +{ +puts ("Board: PH1-sLD8 Board\n" ); + +return check_support_card (); +}
arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c new file +1 -0
@@ -0,0 +1 @@ +#include "../ph1-ld4/board_postclk_init.c"
arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c new file +1 -0
@@ -0,0 +1 @@ +#include "../ph1-pro4/boot-mode.c"
arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c new file +29 -0
@@ -0,0 +1,29 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sc-regs.h> + +void clkrst_init (void ) +{ +u32 tmp; + +/* deassert reset */ + tmp =readl (SC_RSTCTRL ); + tmp |=SC_RSTCTRL_NRST_ETHER |SC_RSTCTRL_NRST_UMC1 + |SC_RSTCTRL_NRST_UMC0 |SC_RSTCTRL_NRST_NAND ; +writel (tmp,SC_RSTCTRL ); +readl (SC_RSTCTRL );/* dummy read */ + +/* privide clocks */ + tmp =readl (SC_CLKCTRL ); + tmp |=SC_CLKCTRL_CLK_ETHER |SC_CLKCTRL_CLK_MIO |SC_CLKCTRL_CLK_UMC + |SC_CLKCTRL_CLK_NAND |SC_CLKCTRL_CLK_SBC |SC_CLKCTRL_CLK_PERI ; +writel (tmp,SC_CLKCTRL ); +readl (SC_CLKCTRL );/* dummy read */ +}
arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c new file +57 -0
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arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c new file +201 -0
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arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c new file +1 -0
@@ -0,0 +1 @@ +#include "../ph1-ld4/pll_spectrum.c"
arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c new file +51 -0
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arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c new file +1 -0
@@ -0,0 +1 @@ +#include "../ph1-ld4/sg_init.c"
arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c new file +10 -0
@@ -0,0 +1,10 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +int umc_init (void ) +{ +return 0 ; +}
arch/arm/cpu/armv7/uniphier/reset.c new file +29 -0
@@ -0,0 +1,29 @@ +/* +* Copyright (C) 2012-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sc-regs.h> +#include <asm/arch/board.h> + +void reset_cpu (unsigned long ignored) +{ +u32 tmp; + +uniphier_board_reset (); + +writel (5 ,SC_IRQTIMSET );/* default value */ + + tmp =readl (SC_SLFRSTSEL ); + tmp &= ~0x3 ;/* mask [1:0] */ + tmp |=0x0 ;/* XRST reboot */ +writel (tmp,SC_SLFRSTSEL ); + + tmp =readl (SC_SLFRSTCTL ); + tmp |=0x1 ; +writel (tmp,SC_SLFRSTCTL ); +}
arch/arm/cpu/armv7/uniphier/smp.S new file +54 -0
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arch/arm/cpu/armv7/uniphier/spl.c new file +17 -0
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arch/arm/cpu/armv7/uniphier/support_card.c new file +180 -0
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arch/arm/cpu/armv7/uniphier/timer.c new file +39 -0
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arch/arm/include/asm/arch-uniphier/arm-mpcore.h new file +46 -0
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arch/arm/include/asm/arch-uniphier/bcu-regs.h new file +29 -0
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arch/arm/include/asm/arch-uniphier/board.h new file +35 -0
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arch/arm/include/asm/arch-uniphier/boot-device.h new file +20 -0
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arch/arm/include/asm/arch-uniphier/led.h new file +101 -0
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arch/arm/include/asm/arch-uniphier/sbc-regs.h new file +107 -0
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arch/arm/include/asm/arch-uniphier/sc-regs.h new file +62 -0
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arch/arm/include/asm/arch-uniphier/sg-regs.h new file +182 -0
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arch/arm/include/asm/arch-uniphier/ssc-regs.h new file +65 -0
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Signature · 1 line
1.9.1
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PATCH 3/6 arm: uniphier: add UniPhier SoC suppurt code
Hi Masahiro,
Quoted 1 line · Masahiro Yamada
Subject: [PATCH 3/6] arm: uniphier: add UniPhier SoC suppurt code
Typo in subject -- since you're going to do a v2, please fix this too, thanks!
Quoted 221 lines
These are used by Panasonic UniPhier SoC family.
Signed-off-by Masahiro Yamada <[email protected]>---
arch/arm/cpu/armv7/uniphier/Makefile | 23 + arch/arm/cpu/armv7/uniphier/board_common.c | 32 + arch/arm/cpu/armv7/uniphier/board_late_init.c | 37 + arch/arm/cpu/armv7/uniphier/cache_uniphier.c | 154 +++ arch/arm/cpu/armv7/uniphier/cmd_pinmon.c | 33 + arch/arm/cpu/armv7/uniphier/cpu_info.c | 59 ++ arch/arm/cpu/armv7/uniphier/dram_init.c | 37 + arch/arm/cpu/armv7/uniphier/init_page_table.c | 1068 ++++++++++++++++++++ arch/arm/cpu/armv7/uniphier/lowlevel_init.S | 159 +++ arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile | 10 + arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c | 33 + arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c | 16 + .../armv7/uniphier/ph1-ld4/board_postclk_init.c | 42 + arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c | 29 + arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c | 63 ++ arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c | 189 ++++ arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c | 44 + arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c | 28 + arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c | 10 + arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile | 10 + arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c | 16 + .../armv7/uniphier/ph1-pro4/board_postclk_init.c | 39 + arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c | 66 ++ arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c | 29 + arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c | 45 + arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c | 168 +++ .../arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c | 18 + arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c | 75 ++ arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c | 28 + arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c | 10 + arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile | 10 + arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c | 16 + .../armv7/uniphier/ph1-sld8/board_postclk_init.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c | 29 + arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c | 57 ++ arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c | 201 ++++ .../arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c | 51 + arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c | 10 + arch/arm/cpu/armv7/uniphier/reset.c | 29 + arch/arm/cpu/armv7/uniphier/smp.S | 54 + arch/arm/cpu/armv7/uniphier/spl.c | 17 + arch/arm/cpu/armv7/uniphier/support_card.c | 180 ++++ arch/arm/cpu/armv7/uniphier/timer.c | 39 + arch/arm/include/asm/arch-uniphier/arm-mpcore.h | 46 + arch/arm/include/asm/arch-uniphier/bcu-regs.h | 29 + arch/arm/include/asm/arch-uniphier/board.h | 35 + arch/arm/include/asm/arch-uniphier/boot-device.h | 20 + arch/arm/include/asm/arch-uniphier/led.h | 101 ++ arch/arm/include/asm/arch-uniphier/sbc-regs.h | 107 ++ arch/arm/include/asm/arch-uniphier/sc-regs.h | 62 ++ arch/arm/include/asm/arch-uniphier/sg-regs.h | 182 ++++ arch/arm/include/asm/arch-uniphier/ssc-regs.h | 65 ++ 58 fileschanged, 3917 insertions(+) create mode 100644
arch/arm/cpu/armv7/uniphier/Makefilecreate mode 100644arch/arm/cpu/armv7/uniphier/board_common.ccreate mode 100644arch/arm/cpu/armv7/uniphier/board_late_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/cache_uniphier.ccreate mode 100644arch/arm/cpu/armv7/uniphier/cmd_pinmon.ccreate mode 100644arch/arm/cpu/armv7/uniphier/cpu_info.ccreate mode 100644arch/arm/cpu/armv7/uniphier/dram_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/init_page_table.ccreate mode 100644arch/arm/cpu/armv7/uniphier/lowlevel_init.Screate mode 100644arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefilecreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefilecreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefilecreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.ccreate mode 100644arch/arm/cpu/armv7/uniphier/reset.ccreate mode 100644arch/arm/cpu/armv7/uniphier/smp.Screate mode 100644arch/arm/cpu/armv7/uniphier/spl.ccreate mode 100644arch/arm/cpu/armv7/uniphier/support_card.ccreate mode 100644arch/arm/cpu/armv7/uniphier/timer.ccreate mode 100644arch/arm/include/asm/arch-uniphier/arm-mpcore.hcreate mode 100644arch/arm/include/asm/arch-uniphier/bcu-regs.hcreate mode 100644arch/arm/include/asm/arch-uniphier/board.hcreate mode 100644arch/arm/include/asm/arch-uniphier/boot-device.hcreate mode 100644arch/arm/include/asm/arch-uniphier/led.hcreate mode 100644arch/arm/include/asm/arch-uniphier/sbc-regs.hcreate mode 100644arch/arm/include/asm/arch-uniphier/sc-regs.hcreate mode 100644arch/arm/include/asm/arch-uniphier/sg-regs.hcreate mode 100644arch/arm/include/asm/arch-uniphier/ssc-regs.h(quoted diff) +0
-0b/arch/arm/cpu/armv7/uniphier/Makefile new file mode 100644 index 0000000..13d6ef1
arch/arm/cpu/armv7/uniphier/Makefile new file +23
-0@@ -0,0 +1,23 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_SPL_BUILD) += lowlevel_init.o init_page_table.o +obj-$(CONFIG_SPL_BUILD) += spl.o + +obj-y += timer.o +obj-y += reset.o +obj-y += cache_uniphier.o +obj-y += dram_init.o +obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o +obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o +obj-$(CONFIG_UNIPHIER_SMP) += smp.o +obj-$(if $(CONFIG_SPL_BUILD),,y) += cmd_pinmon.o + +obj-y += board_common.o +obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o +obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o + +obj-$(CONFIG_PH1_LD4) += ph1-ld4/ +obj-$(CONFIG_PH1_PRO4) += ph1-pro4/ +obj-$(CONFIG_PH1_SLD8) += ph1-sld8/(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/board_common.cnew file mode 100644 index 0000000..3fb26c6arch/arm/cpu/armv7/uniphier/board_common.c new file +32
-0@@ -0,0 +1,32 @@ +/* +* Copyright (C) 2012-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/arch/led.h> + +/* +* Routine: board_init +* Description: Early hardware init. +*/ +int board_init (void ) +{ +led_write (U ,B ,O ,O ); + +return 0 ; +} + +#if CONFIG_NR_DRAM_BANKS >=2 +void dram_init_banksize (void ) +{ +DECLARE_GLOBAL_DATA_PTR ; + + gd->bd->bi_dram[0 ].start =CONFIG_SDRAM0_BASE ; + gd->bd->bi_dram[0 ].size =CONFIG_SDRAM0_SIZE ; + gd->bd->bi_dram[1 ].start =CONFIG_SDRAM1_BASE ; + gd->bd->bi_dram[1 ].size =CONFIG_SDRAM1_SIZE ; +} +#endif (quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/board_late_init.cnew file mode 100644 index 0000000..844b3e1arch/arm/cpu/armv7/uniphier/board_late_init.c new file +16
-0@@ -0,0 +1,37 @@ +/* +* Copyright (C) 2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <spl.h> +#include <nand.h> +#include <asm/io.h> +#include <../drivers/mtd/nand/denali.h> + +static void nand_denali_wp_disable (void ) +{ + void __iomem *denali_reg = (void __iomem*)CONFIG_SYS_NAND_REGS_BASE; +
arch/arm/cpu/armv7/uniphier/board_late_init.c new file +5
-0+writel (WRITE_PROTECT__FLAG , denali_reg +WRITE_PROTECT ); +} + +int board_late_init (void ) +{
arch/arm/cpu/armv7/uniphier/board_late_init.c line 32
Quoted 10 lines
arch/arm/cpu/armv7/uniphier/board_late_init.c new file +10
-0+puts ("MODE: " ); + +switch (spl_boot_device ()) { +case BOOT_DEVICE_NAND : +printf ("NAND Boot\n" ); +setenv ("bootmode" ,"nandboot" ); +nand_denali_wp_disable (); +break ; +default : +printf ("Unsupported Boot Mode\n" );
Please add the mode value (decimal, hex or binary as you prefer, as long as the reader can understand the format) to the output.
Quoted 99 lines
arch/arm/cpu/armv7/uniphier/board_late_init.c new file +5
-0+return -1 ; + } + +return 0 ; +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/cache_uniphier.cnew file mode 100644 index 0000000..e47f977arch/arm/cpu/armv7/uniphier/cache_uniphier.c new file +19
-0@@ -0,0 +1,154 @@ +/* +* Copyright (C) 2012-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/armv7.h> +#include <asm/arch/ssc-regs.h> + +#ifdef CONFIG_UNIPHIER_L2CACHE_ON +static void uniphier_cache_maint_all (u32 operation) +{ +/* try until the command is successfully set */ + do { + writel(SSCOQM_S_ALL | SSCOQM_CE | operation, SSCOQM); + } while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE |
SSCOPPQSEF_OE)); +arch/arm/cpu/armv7/uniphier/cache_uniphier.c new file +22
-0+/* wait until the operation is completed */ +while (readl (SSCOLPQS ) !=SSCOLPQS_EF ) + ; + +/* clear the complete notification flag */ +writel (SSCOLPQS_EF ,SSCOLPQS ); + +writel (SSCOPE_CM_SYNC ,SSCOPE );/* drain internal buffers */ +readl (SSCOPE );/* need a read back to confirm */ +} + +void v7_outer_cache_flush_all (void ) +{ +uniphier_cache_maint_all (SSCOQM_CM_WB_INV ); +} + +void v7_outer_cache_inval_all (void ) +{ +uniphier_cache_maint_all (SSCOQM_CM_INV ); +} + +static void __uniphier_cache_maint_range(u32 start, u32 size, u32operation) +{
arch/arm/cpu/armv7/uniphier/cache_uniphier.c new file +3
-0+/* try until the command is successfully set */ + do { + writel(SSCOQM_S_ADDRESS | SSCOQM_CE | operation,SSCOQM);
arch/arm/cpu/armv7/uniphier/cache_uniphier.c new file +4
-0+writel (start,SSCOQAD ); +writel (size,SSCOQSZ ); + + } while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE |
SSCOPPQSEF_OE)); +arch/arm/cpu/armv7/uniphier/cache_uniphier.c new file +9
-0+/* wait until the operation is completed */ +while (readl (SSCOLPQS ) !=SSCOLPQS_EF ) + ; + +/* clear the complete notification flag */ +writel (SSCOLPQS_EF ,SSCOLPQS ); +} + +static void uniphier_cache_maint_range(u32 start, u32 end, u32operation) +{
arch/arm/cpu/armv7/uniphier/cache_uniphier.c new file +19
-0+u32 size; + +/* +* If start address is not aligned to cache-line, +* do cache operation for the first cache-line +*/ + start = start & ~(SSC_LINE_SIZE -1 ); + +if (start ==0 && end >= (u32)(-SSC_LINE_SIZE )) { +/* this means cache operation for all range */ +uniphier_cache_maint_all (operation); +return ; + } + +/* +* If end address is not aligned to cache-line, +* do cache operation for the last cache-line +*/ + size = (end - start + SSC_LINE_SIZE - 1) & ~(SSC_LINE_SIZE -1); +
arch/arm/cpu/armv7/uniphier/cache_uniphier.c new file +3
-0+while (size) { + u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ? +
SSC_RANGE_OP_MAX_SIZE: size;arch/arm/cpu/armv7/uniphier/cache_uniphier.c new file +1
-0+ __uniphier_cache_maint_range(start, chunk_size,operation); +
arch/arm/cpu/armv7/uniphier/cache_uniphier.c line 92
Quoted 6 lines
arch/arm/cpu/armv7/uniphier/cache_uniphier.c new file +6
-0+ start += chunk_size; + size -= chunk_size; + } + +writel (SSCOPE_CM_SYNC ,SSCOPE );/* drain internal buffers */ +readl (SSCOPE );/* need a read back to confirm */
Does the readback contain some status showing whether the drain is in progress vs. complete? If it does, then shouldn't the line above be a loop waiting for completion?
Quoted 141 lines
arch/arm/cpu/armv7/uniphier/cache_uniphier.c new file +62
-0+} + +void v7_outer_cache_flush_range (u32 start,u32 end) +{ +uniphier_cache_maint_range (start, end,SSCOQM_CM_WB_INV ); +} + +void v7_outer_cache_inval_range (u32 start,u32 end) +{ +uniphier_cache_maint_range (start, end,SSCOQM_CM_INV ); +} + +void v7_outer_cache_enable (void ) +{ +u32 tmp; + tmp =readl (SSCC ); + tmp |=SSCC_ON ; +writel (tmp,SSCC ); +} +#endif + +void v7_outer_cache_disable (void ) +{ +u32 tmp; + tmp =readl (SSCC ); + tmp &= ~SSCC_ON ; +writel (tmp,SSCC ); +} + +void wakeup_secondary (void ); + +void enable_caches (void ) +{ +uint32_t reg; + +#ifdef CONFIG_UNIPHIER_SMP +/* +* The secondary CPU must move to DDR, +* before L2 disable. +* On SPL, the Page Table is located on the L2. +*/ +wakeup_secondary (); +#endif +/* +* UniPhier SoCs must use L2 cache for init stack pointer. +* We disable L2 and L1 in this order. +* If CONFIG_SYS_DCACHE_OFF is not defined, +* caches are enabled again with a new page table. +*/ + +/* L2 disable */ +v7_outer_cache_disable (); + +/* L1 disable */ + reg =get_cr (); + reg &= ~(CR_C |CR_M ); +set_cr (reg); + +#ifndef CONFIG_SYS_DCACHE_OFF +dcache_enable (); +#endif +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/cmd_pinmon.cnew file mode 100644 index 0000000..eef9f39arch/arm/cpu/armv7/uniphier/cmd_pinmon.c new file +11
-0@@ -0,0 +1,33 @@ +/* +* Copyright (C) 2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/arch/boot-device.h> + +static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{
arch/arm/cpu/armv7/uniphier/cmd_pinmon.c new file +8
-0+struct boot_device_info *table; +u32 mode_sel, n =0 ; + + mode_sel =get_boot_mode_sel (); + +puts ("Boot Mode Pin:\n" ); + + for (table = boot_device_table; strlen(table->info);table++) {
arch/arm/cpu/armv7/uniphier/cmd_pinmon.c new file +13
-0+printf (" %c %02x %s\n" , n == mode_sel ?'*' :' ' , n, + table->info); + n++; + } + +return 0 ; +} + +U_BOOT_CMD ( + pinmon,1 ,1 , do_pinmon, +"pin monitor" , +"" +);(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/cpu_info.cnew file mode 100644 index 0000000..86d079aarch/arm/cpu/armv7/uniphier/cpu_info.c new file +14
-0@@ -0,0 +1,59 @@ +/* +* Copyright (C) 2013-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sg-regs.h> + +int print_cpuinfo (void ) +{ + u32 revision, type, model, rev, required_model = 1,
required_rev= 1; +arch/arm/cpu/armv7/uniphier/cpu_info.c new file +2
-0+ revision =readl (SG_REVISION ); + type = (revision & SG_REVISION_TYPE_MASK) >>
SG_REVISION_TYPE_SHIFT;arch/arm/cpu/armv7/uniphier/cpu_info.c new file +1
-0+ model = (revision & SG_REVISION_MODEL_MASK) >>
SG_REVISION_MODEL_SHIFT;arch/arm/cpu/armv7/uniphier/cpu_info.c new file +1
-0+ rev = (revision & SG_REVISION_REV_MASK) >>
SG_REVISION_REV_SHIFT; +arch/arm/cpu/armv7/uniphier/cpu_info.c new file +11
-0+puts ("CPU: " ); + +switch (type) { +case 0x25 : +puts ("PH1-sLD3 (MN2WS0220)" ); + required_model =2 ; +break ; +case 0x26 : +puts ("PH1-LD4 (MN2WS0250)" ); + required_rev =2 ; +break ;
arch/arm/cpu/armv7/uniphier/cpu_info.c line 41
Quoted 10 lines
arch/arm/cpu/armv7/uniphier/cpu_info.c new file +10
-0+case 0x28 : +puts ("PH1-Pro4 (MN2WS0230)" ); +break ; +case 0x29 : +puts ("PH1-sLD8 (MN2WS0270)" ); +break ; +default : +printf ("Unknown Processor ID (0x%x)\n" , revision); +return -1 ; + }
Maybe use symbolic constants rather tha magic numbers in switch cases above.
Quoted 2,159 lines
arch/arm/cpu/armv7/uniphier/cpu_info.c new file +17
-0+if (model >1 ) +printf (" model %d" , model); + +printf (" (rev. %d)\n" , rev); + +if (model < required_model) { +printf ("Sorry, this model is not supported.\n" ); +printf ("Required model is %d." , required_model); +return -1 ; + }else if (rev < required_rev) { +printf ("Sorry, this revision is not supported.\n" ); +printf ("Required revision is %d." , required_rev); +return -1 ; + } + +return 0 ; +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/dram_init.cnew file mode 100644 index 0000000..5465a0earch/arm/cpu/armv7/uniphier/dram_init.c new file +37
-0@@ -0,0 +1,37 @@ +/* +* Copyright (C) 2012-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/arch/led.h> + +int umc_init (void ); +void enable_dpll_ssc (void ); + +int dram_init (void ) +{ +DECLARE_GLOBAL_DATA_PTR ; + gd->ram_size =CONFIG_SYS_SDRAM_SIZE ; + +#if !defined(CONFIG_SPL ) || defined(CONFIG_SPL_BUILD ) + led_write(B, 4, , ); + + { +int res; + + res =umc_init (); +if (res <0 ) +return res; + } + led_write(B, 5, , ); + +enable_dpll_ssc (); +#endif + + led_write(B, 6, , ); + +return 0 ; +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/init_page_table.cnew file mode 100644 index 0000000..d273835arch/arm/cpu/armv7/uniphier/init_page_table.c new file +13
-0@@ -0,0 +1,1068 @@ +/* +* Copyright (C) 2012-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> + +/* encoding without TEX remap */ +#define NO_MAP 0x00000000/* No Map */ +#define DEVICE 0x00002002/* Non-shareable Device */ +#define NORMAL 0x0000000e/* Normal Memory Write-Back, No Write-Allocate */ +
arch/arm/cpu/armv7/uniphier/init_page_table.c new file +7
-0+#define SSC NORMAL/* System Cache: Normal */ +#define EXT DEVICE/* External Bus: Device */ +#define REG DEVICE/* IO Register: Device */ +#define DDR DEVICE/* DDR SDRAM: Device */ + +#ifdef CONFIG_SPL_BUILD +#define IS_SPL_TEXT_AREA (x) ((x) == ((CONFIG_SPL_TEXT_BASE)Quoted 1 line
Quoted 1 line
20)) +#else
+#define
IS_SPL_TEXT_AREA(x)((x) == ((CONFIG_SYS_TEXT_BASE)Quoted 1 line
Quoted 1 line
20)) +#endif
arch/arm/cpu/armv7/uniphier/init_page_table.c new file +2
-0+ +#define IS_INIT_STACK_AREA (x) ((x) ==((
CONFIG_SYS_INIT_SP_ADDR) >> 20)) +arch/arm/cpu/armv7/uniphier/init_page_table.c new file +10
-0+#define IS_SSC (x) ((IS_SPL_TEXT_AREA(x)) || \ + (IS_INIT_STACK_AREA(x))) +#define IS_EXT (x) ((x) < 0x100) +#define IS_REG (x) (0x500 <= (x) && (x) < 0x700) +#define IS_DDR (x) (0x800 <= (x) && (x) < 0xf00) + +#define MMU_FLAGS (x) (IS_SSC(x)) ? SSC : \ + (IS_EXT(x)) ? EXT : \ + (IS_REG(x)) ? REG : \ +(
IS_DDR(x)) ? DDR : \
+NO_MAP+arch/arm/cpu/armv7/uniphier/init_page_table.c new file +3
-0+#define TBL_ENTRY (x) (((x) << 20) | (MMU_FLAGS(x))) + +const u32 __aligned(PGTABLE_SIZE) init_page_table[PGTABLE_SIZE /sizeof(u32)]
+
= {arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x000), TBL_ENTRY(0x001), TBL_ENTRY(0x002),
TBL_ENTRY(0x003),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x004), TBL_ENTRY(0x005), TBL_ENTRY(0x006),
TBL_ENTRY(0x007),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x008), TBL_ENTRY(0x009), TBL_ENTRY(0x00a),
TBL_ENTRY(0x00b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x00c), TBL_ENTRY(0x00d), TBL_ENTRY(0x00e),
TBL_ENTRY(0x00f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x010), TBL_ENTRY(0x011), TBL_ENTRY(0x012),
TBL_ENTRY(0x013),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x014), TBL_ENTRY(0x015), TBL_ENTRY(0x016),
TBL_ENTRY(0x017),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x018), TBL_ENTRY(0x019), TBL_ENTRY(0x01a),
TBL_ENTRY(0x01b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x01c), TBL_ENTRY(0x01d), TBL_ENTRY(0x01e),
TBL_ENTRY(0x01f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x020), TBL_ENTRY(0x021), TBL_ENTRY(0x022),
TBL_ENTRY(0x023),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x024), TBL_ENTRY(0x025), TBL_ENTRY(0x026),
TBL_ENTRY(0x027),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x028), TBL_ENTRY(0x029), TBL_ENTRY(0x02a),
TBL_ENTRY(0x02b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x02c), TBL_ENTRY(0x02d), TBL_ENTRY(0x02e),
TBL_ENTRY(0x02f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x030), TBL_ENTRY(0x031), TBL_ENTRY(0x032),
TBL_ENTRY(0x033),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x034), TBL_ENTRY(0x035), TBL_ENTRY(0x036),
TBL_ENTRY(0x037),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x038), TBL_ENTRY(0x039), TBL_ENTRY(0x03a),
TBL_ENTRY(0x03b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x03c), TBL_ENTRY(0x03d), TBL_ENTRY(0x03e),
TBL_ENTRY(0x03f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x040), TBL_ENTRY(0x041), TBL_ENTRY(0x042),
TBL_ENTRY(0x043),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x044), TBL_ENTRY(0x045), TBL_ENTRY(0x046),
TBL_ENTRY(0x047),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x048), TBL_ENTRY(0x049), TBL_ENTRY(0x04a),
TBL_ENTRY(0x04b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x04c), TBL_ENTRY(0x04d), TBL_ENTRY(0x04e),
TBL_ENTRY(0x04f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x050), TBL_ENTRY(0x051), TBL_ENTRY(0x052),
TBL_ENTRY(0x053),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x054), TBL_ENTRY(0x055), TBL_ENTRY(0x056),
TBL_ENTRY(0x057),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x058), TBL_ENTRY(0x059), TBL_ENTRY(0x05a),
TBL_ENTRY(0x05b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x05c), TBL_ENTRY(0x05d), TBL_ENTRY(0x05e),
TBL_ENTRY(0x05f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x060), TBL_ENTRY(0x061), TBL_ENTRY(0x062),
TBL_ENTRY(0x063),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x064), TBL_ENTRY(0x065), TBL_ENTRY(0x066),
TBL_ENTRY(0x067),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x068), TBL_ENTRY(0x069), TBL_ENTRY(0x06a),
TBL_ENTRY(0x06b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x06c), TBL_ENTRY(0x06d), TBL_ENTRY(0x06e),
TBL_ENTRY(0x06f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x070), TBL_ENTRY(0x071), TBL_ENTRY(0x072),
TBL_ENTRY(0x073),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x074), TBL_ENTRY(0x075), TBL_ENTRY(0x076),
TBL_ENTRY(0x077),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x078), TBL_ENTRY(0x079), TBL_ENTRY(0x07a),
TBL_ENTRY(0x07b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x07c), TBL_ENTRY(0x07d), TBL_ENTRY(0x07e),
TBL_ENTRY(0x07f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x080), TBL_ENTRY(0x081), TBL_ENTRY(0x082),
TBL_ENTRY(0x083),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x084), TBL_ENTRY(0x085), TBL_ENTRY(0x086),
TBL_ENTRY(0x087),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x088), TBL_ENTRY(0x089), TBL_ENTRY(0x08a),
TBL_ENTRY(0x08b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x08c), TBL_ENTRY(0x08d), TBL_ENTRY(0x08e),
TBL_ENTRY(0x08f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x090), TBL_ENTRY(0x091), TBL_ENTRY(0x092),
TBL_ENTRY(0x093),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x094), TBL_ENTRY(0x095), TBL_ENTRY(0x096),
TBL_ENTRY(0x097),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x098), TBL_ENTRY(0x099), TBL_ENTRY(0x09a),
TBL_ENTRY(0x09b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x09c), TBL_ENTRY(0x09d), TBL_ENTRY(0x09e),
TBL_ENTRY(0x09f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0a0), TBL_ENTRY(0x0a1), TBL_ENTRY(0x0a2),
TBL_ENTRY(0x0a3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0a4), TBL_ENTRY(0x0a5), TBL_ENTRY(0x0a6),
TBL_ENTRY(0x0a7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0a8), TBL_ENTRY(0x0a9), TBL_ENTRY(0x0aa),
TBL_ENTRY(0x0ab),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0ac), TBL_ENTRY(0x0ad), TBL_ENTRY(0x0ae),
TBL_ENTRY(0x0af),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0b0), TBL_ENTRY(0x0b1), TBL_ENTRY(0x0b2),
TBL_ENTRY(0x0b3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0b4), TBL_ENTRY(0x0b5), TBL_ENTRY(0x0b6),
TBL_ENTRY(0x0b7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0b8), TBL_ENTRY(0x0b9), TBL_ENTRY(0x0ba),
TBL_ENTRY(0x0bb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0bc), TBL_ENTRY(0x0bd), TBL_ENTRY(0x0be),
TBL_ENTRY(0x0bf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0c0), TBL_ENTRY(0x0c1), TBL_ENTRY(0x0c2),
TBL_ENTRY(0x0c3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0c4), TBL_ENTRY(0x0c5), TBL_ENTRY(0x0c6),
TBL_ENTRY(0x0c7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0c8), TBL_ENTRY(0x0c9), TBL_ENTRY(0x0ca),
TBL_ENTRY(0x0cb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0cc), TBL_ENTRY(0x0cd), TBL_ENTRY(0x0ce),
TBL_ENTRY(0x0cf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0d0), TBL_ENTRY(0x0d1), TBL_ENTRY(0x0d2),
TBL_ENTRY(0x0d3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0d4), TBL_ENTRY(0x0d5), TBL_ENTRY(0x0d6),
TBL_ENTRY(0x0d7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0d8), TBL_ENTRY(0x0d9), TBL_ENTRY(0x0da),
TBL_ENTRY(0x0db),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0dc), TBL_ENTRY(0x0dd), TBL_ENTRY(0x0de),
TBL_ENTRY(0x0df),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0e0), TBL_ENTRY(0x0e1), TBL_ENTRY(0x0e2),
TBL_ENTRY(0x0e3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0e4), TBL_ENTRY(0x0e5), TBL_ENTRY(0x0e6),
TBL_ENTRY(0x0e7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0e8), TBL_ENTRY(0x0e9), TBL_ENTRY(0x0ea),
TBL_ENTRY(0x0eb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0ec), TBL_ENTRY(0x0ed), TBL_ENTRY(0x0ee),
TBL_ENTRY(0x0ef),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0f0), TBL_ENTRY(0x0f1), TBL_ENTRY(0x0f2),
TBL_ENTRY(0x0f3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0f4), TBL_ENTRY(0x0f5), TBL_ENTRY(0x0f6),
TBL_ENTRY(0x0f7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0f8), TBL_ENTRY(0x0f9), TBL_ENTRY(0x0fa),
TBL_ENTRY(0x0fb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x0fc), TBL_ENTRY(0x0fd), TBL_ENTRY(0x0fe),
TBL_ENTRY(0x0ff),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x100), TBL_ENTRY(0x101), TBL_ENTRY(0x102),
TBL_ENTRY(0x103),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x104), TBL_ENTRY(0x105), TBL_ENTRY(0x106),
TBL_ENTRY(0x107),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x108), TBL_ENTRY(0x109), TBL_ENTRY(0x10a),
TBL_ENTRY(0x10b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x10c), TBL_ENTRY(0x10d), TBL_ENTRY(0x10e),
TBL_ENTRY(0x10f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x110), TBL_ENTRY(0x111), TBL_ENTRY(0x112),
TBL_ENTRY(0x113),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x114), TBL_ENTRY(0x115), TBL_ENTRY(0x116),
TBL_ENTRY(0x117),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x118), TBL_ENTRY(0x119), TBL_ENTRY(0x11a),
TBL_ENTRY(0x11b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x11c), TBL_ENTRY(0x11d), TBL_ENTRY(0x11e),
TBL_ENTRY(0x11f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x120), TBL_ENTRY(0x121), TBL_ENTRY(0x122),
TBL_ENTRY(0x123),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x124), TBL_ENTRY(0x125), TBL_ENTRY(0x126),
TBL_ENTRY(0x127),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x128), TBL_ENTRY(0x129), TBL_ENTRY(0x12a),
TBL_ENTRY(0x12b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x12c), TBL_ENTRY(0x12d), TBL_ENTRY(0x12e),
TBL_ENTRY(0x12f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x130), TBL_ENTRY(0x131), TBL_ENTRY(0x132),
TBL_ENTRY(0x133),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x134), TBL_ENTRY(0x135), TBL_ENTRY(0x136),
TBL_ENTRY(0x137),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x138), TBL_ENTRY(0x139), TBL_ENTRY(0x13a),
TBL_ENTRY(0x13b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x13c), TBL_ENTRY(0x13d), TBL_ENTRY(0x13e),
TBL_ENTRY(0x13f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x140), TBL_ENTRY(0x141), TBL_ENTRY(0x142),
TBL_ENTRY(0x143),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x144), TBL_ENTRY(0x145), TBL_ENTRY(0x146),
TBL_ENTRY(0x147),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x148), TBL_ENTRY(0x149), TBL_ENTRY(0x14a),
TBL_ENTRY(0x14b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x14c), TBL_ENTRY(0x14d), TBL_ENTRY(0x14e),
TBL_ENTRY(0x14f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x150), TBL_ENTRY(0x151), TBL_ENTRY(0x152),
TBL_ENTRY(0x153),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x154), TBL_ENTRY(0x155), TBL_ENTRY(0x156),
TBL_ENTRY(0x157),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x158), TBL_ENTRY(0x159), TBL_ENTRY(0x15a),
TBL_ENTRY(0x15b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x15c), TBL_ENTRY(0x15d), TBL_ENTRY(0x15e),
TBL_ENTRY(0x15f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x160), TBL_ENTRY(0x161), TBL_ENTRY(0x162),
TBL_ENTRY(0x163),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x164), TBL_ENTRY(0x165), TBL_ENTRY(0x166),
TBL_ENTRY(0x167),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x168), TBL_ENTRY(0x169), TBL_ENTRY(0x16a),
TBL_ENTRY(0x16b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x16c), TBL_ENTRY(0x16d), TBL_ENTRY(0x16e),
TBL_ENTRY(0x16f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x170), TBL_ENTRY(0x171), TBL_ENTRY(0x172),
TBL_ENTRY(0x173),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x174), TBL_ENTRY(0x175), TBL_ENTRY(0x176),
TBL_ENTRY(0x177),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x178), TBL_ENTRY(0x179), TBL_ENTRY(0x17a),
TBL_ENTRY(0x17b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x17c), TBL_ENTRY(0x17d), TBL_ENTRY(0x17e),
TBL_ENTRY(0x17f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x180), TBL_ENTRY(0x181), TBL_ENTRY(0x182),
TBL_ENTRY(0x183),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x184), TBL_ENTRY(0x185), TBL_ENTRY(0x186),
TBL_ENTRY(0x187),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x188), TBL_ENTRY(0x189), TBL_ENTRY(0x18a),
TBL_ENTRY(0x18b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x18c), TBL_ENTRY(0x18d), TBL_ENTRY(0x18e),
TBL_ENTRY(0x18f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x190), TBL_ENTRY(0x191), TBL_ENTRY(0x192),
TBL_ENTRY(0x193),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x194), TBL_ENTRY(0x195), TBL_ENTRY(0x196),
TBL_ENTRY(0x197),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x198), TBL_ENTRY(0x199), TBL_ENTRY(0x19a),
TBL_ENTRY(0x19b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x19c), TBL_ENTRY(0x19d), TBL_ENTRY(0x19e),
TBL_ENTRY(0x19f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1a0), TBL_ENTRY(0x1a1), TBL_ENTRY(0x1a2),
TBL_ENTRY(0x1a3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1a4), TBL_ENTRY(0x1a5), TBL_ENTRY(0x1a6),
TBL_ENTRY(0x1a7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1a8), TBL_ENTRY(0x1a9), TBL_ENTRY(0x1aa),
TBL_ENTRY(0x1ab),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1ac), TBL_ENTRY(0x1ad), TBL_ENTRY(0x1ae),
TBL_ENTRY(0x1af),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1b0), TBL_ENTRY(0x1b1), TBL_ENTRY(0x1b2),
TBL_ENTRY(0x1b3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1b4), TBL_ENTRY(0x1b5), TBL_ENTRY(0x1b6),
TBL_ENTRY(0x1b7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1b8), TBL_ENTRY(0x1b9), TBL_ENTRY(0x1ba),
TBL_ENTRY(0x1bb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1bc), TBL_ENTRY(0x1bd), TBL_ENTRY(0x1be),
TBL_ENTRY(0x1bf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1c0), TBL_ENTRY(0x1c1), TBL_ENTRY(0x1c2),
TBL_ENTRY(0x1c3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1c4), TBL_ENTRY(0x1c5), TBL_ENTRY(0x1c6),
TBL_ENTRY(0x1c7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1c8), TBL_ENTRY(0x1c9), TBL_ENTRY(0x1ca),
TBL_ENTRY(0x1cb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1cc), TBL_ENTRY(0x1cd), TBL_ENTRY(0x1ce),
TBL_ENTRY(0x1cf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1d0), TBL_ENTRY(0x1d1), TBL_ENTRY(0x1d2),
TBL_ENTRY(0x1d3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1d4), TBL_ENTRY(0x1d5), TBL_ENTRY(0x1d6),
TBL_ENTRY(0x1d7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1d8), TBL_ENTRY(0x1d9), TBL_ENTRY(0x1da),
TBL_ENTRY(0x1db),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1dc), TBL_ENTRY(0x1dd), TBL_ENTRY(0x1de),
TBL_ENTRY(0x1df),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1e0), TBL_ENTRY(0x1e1), TBL_ENTRY(0x1e2),
TBL_ENTRY(0x1e3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1e4), TBL_ENTRY(0x1e5), TBL_ENTRY(0x1e6),
TBL_ENTRY(0x1e7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1e8), TBL_ENTRY(0x1e9), TBL_ENTRY(0x1ea),
TBL_ENTRY(0x1eb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1ec), TBL_ENTRY(0x1ed), TBL_ENTRY(0x1ee),
TBL_ENTRY(0x1ef),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1f0), TBL_ENTRY(0x1f1), TBL_ENTRY(0x1f2),
TBL_ENTRY(0x1f3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1f4), TBL_ENTRY(0x1f5), TBL_ENTRY(0x1f6),
TBL_ENTRY(0x1f7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1f8), TBL_ENTRY(0x1f9), TBL_ENTRY(0x1fa),
TBL_ENTRY(0x1fb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x1fc), TBL_ENTRY(0x1fd), TBL_ENTRY(0x1fe),
TBL_ENTRY(0x1ff),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x200), TBL_ENTRY(0x201), TBL_ENTRY(0x202),
TBL_ENTRY(0x203),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x204), TBL_ENTRY(0x205), TBL_ENTRY(0x206),
TBL_ENTRY(0x207),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x208), TBL_ENTRY(0x209), TBL_ENTRY(0x20a),
TBL_ENTRY(0x20b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x20c), TBL_ENTRY(0x20d), TBL_ENTRY(0x20e),
TBL_ENTRY(0x20f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x210), TBL_ENTRY(0x211), TBL_ENTRY(0x212),
TBL_ENTRY(0x213),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x214), TBL_ENTRY(0x215), TBL_ENTRY(0x216),
TBL_ENTRY(0x217),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x218), TBL_ENTRY(0x219), TBL_ENTRY(0x21a),
TBL_ENTRY(0x21b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x21c), TBL_ENTRY(0x21d), TBL_ENTRY(0x21e),
TBL_ENTRY(0x21f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x220), TBL_ENTRY(0x221), TBL_ENTRY(0x222),
TBL_ENTRY(0x223),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x224), TBL_ENTRY(0x225), TBL_ENTRY(0x226),
TBL_ENTRY(0x227),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x228), TBL_ENTRY(0x229), TBL_ENTRY(0x22a),
TBL_ENTRY(0x22b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x22c), TBL_ENTRY(0x22d), TBL_ENTRY(0x22e),
TBL_ENTRY(0x22f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x230), TBL_ENTRY(0x231), TBL_ENTRY(0x232),
TBL_ENTRY(0x233),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x234), TBL_ENTRY(0x235), TBL_ENTRY(0x236),
TBL_ENTRY(0x237),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x238), TBL_ENTRY(0x239), TBL_ENTRY(0x23a),
TBL_ENTRY(0x23b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x23c), TBL_ENTRY(0x23d), TBL_ENTRY(0x23e),
TBL_ENTRY(0x23f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x240), TBL_ENTRY(0x241), TBL_ENTRY(0x242),
TBL_ENTRY(0x243),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x244), TBL_ENTRY(0x245), TBL_ENTRY(0x246),
TBL_ENTRY(0x247),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x248), TBL_ENTRY(0x249), TBL_ENTRY(0x24a),
TBL_ENTRY(0x24b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x24c), TBL_ENTRY(0x24d), TBL_ENTRY(0x24e),
TBL_ENTRY(0x24f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x250), TBL_ENTRY(0x251), TBL_ENTRY(0x252),
TBL_ENTRY(0x253),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x254), TBL_ENTRY(0x255), TBL_ENTRY(0x256),
TBL_ENTRY(0x257),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x258), TBL_ENTRY(0x259), TBL_ENTRY(0x25a),
TBL_ENTRY(0x25b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x25c), TBL_ENTRY(0x25d), TBL_ENTRY(0x25e),
TBL_ENTRY(0x25f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x260), TBL_ENTRY(0x261), TBL_ENTRY(0x262),
TBL_ENTRY(0x263),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x264), TBL_ENTRY(0x265), TBL_ENTRY(0x266),
TBL_ENTRY(0x267),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x268), TBL_ENTRY(0x269), TBL_ENTRY(0x26a),
TBL_ENTRY(0x26b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x26c), TBL_ENTRY(0x26d), TBL_ENTRY(0x26e),
TBL_ENTRY(0x26f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x270), TBL_ENTRY(0x271), TBL_ENTRY(0x272),
TBL_ENTRY(0x273),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x274), TBL_ENTRY(0x275), TBL_ENTRY(0x276),
TBL_ENTRY(0x277),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x278), TBL_ENTRY(0x279), TBL_ENTRY(0x27a),
TBL_ENTRY(0x27b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x27c), TBL_ENTRY(0x27d), TBL_ENTRY(0x27e),
TBL_ENTRY(0x27f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x280), TBL_ENTRY(0x281), TBL_ENTRY(0x282),
TBL_ENTRY(0x283),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x284), TBL_ENTRY(0x285), TBL_ENTRY(0x286),
TBL_ENTRY(0x287),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x288), TBL_ENTRY(0x289), TBL_ENTRY(0x28a),
TBL_ENTRY(0x28b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x28c), TBL_ENTRY(0x28d), TBL_ENTRY(0x28e),
TBL_ENTRY(0x28f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x290), TBL_ENTRY(0x291), TBL_ENTRY(0x292),
TBL_ENTRY(0x293),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x294), TBL_ENTRY(0x295), TBL_ENTRY(0x296),
TBL_ENTRY(0x297),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x298), TBL_ENTRY(0x299), TBL_ENTRY(0x29a),
TBL_ENTRY(0x29b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x29c), TBL_ENTRY(0x29d), TBL_ENTRY(0x29e),
TBL_ENTRY(0x29f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2a0), TBL_ENTRY(0x2a1), TBL_ENTRY(0x2a2),
TBL_ENTRY(0x2a3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2a4), TBL_ENTRY(0x2a5), TBL_ENTRY(0x2a6),
TBL_ENTRY(0x2a7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2a8), TBL_ENTRY(0x2a9), TBL_ENTRY(0x2aa),
TBL_ENTRY(0x2ab),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2ac), TBL_ENTRY(0x2ad), TBL_ENTRY(0x2ae),
TBL_ENTRY(0x2af),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2b0), TBL_ENTRY(0x2b1), TBL_ENTRY(0x2b2),
TBL_ENTRY(0x2b3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2b4), TBL_ENTRY(0x2b5), TBL_ENTRY(0x2b6),
TBL_ENTRY(0x2b7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2b8), TBL_ENTRY(0x2b9), TBL_ENTRY(0x2ba),
TBL_ENTRY(0x2bb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2bc), TBL_ENTRY(0x2bd), TBL_ENTRY(0x2be),
TBL_ENTRY(0x2bf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2c0), TBL_ENTRY(0x2c1), TBL_ENTRY(0x2c2),
TBL_ENTRY(0x2c3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2c4), TBL_ENTRY(0x2c5), TBL_ENTRY(0x2c6),
TBL_ENTRY(0x2c7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2c8), TBL_ENTRY(0x2c9), TBL_ENTRY(0x2ca),
TBL_ENTRY(0x2cb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2cc), TBL_ENTRY(0x2cd), TBL_ENTRY(0x2ce),
TBL_ENTRY(0x2cf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2d0), TBL_ENTRY(0x2d1), TBL_ENTRY(0x2d2),
TBL_ENTRY(0x2d3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2d4), TBL_ENTRY(0x2d5), TBL_ENTRY(0x2d6),
TBL_ENTRY(0x2d7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2d8), TBL_ENTRY(0x2d9), TBL_ENTRY(0x2da),
TBL_ENTRY(0x2db),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2dc), TBL_ENTRY(0x2dd), TBL_ENTRY(0x2de),
TBL_ENTRY(0x2df),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2e0), TBL_ENTRY(0x2e1), TBL_ENTRY(0x2e2),
TBL_ENTRY(0x2e3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2e4), TBL_ENTRY(0x2e5), TBL_ENTRY(0x2e6),
TBL_ENTRY(0x2e7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2e8), TBL_ENTRY(0x2e9), TBL_ENTRY(0x2ea),
TBL_ENTRY(0x2eb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2ec), TBL_ENTRY(0x2ed), TBL_ENTRY(0x2ee),
TBL_ENTRY(0x2ef),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2f0), TBL_ENTRY(0x2f1), TBL_ENTRY(0x2f2),
TBL_ENTRY(0x2f3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2f4), TBL_ENTRY(0x2f5), TBL_ENTRY(0x2f6),
TBL_ENTRY(0x2f7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2f8), TBL_ENTRY(0x2f9), TBL_ENTRY(0x2fa),
TBL_ENTRY(0x2fb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x2fc), TBL_ENTRY(0x2fd), TBL_ENTRY(0x2fe),
TBL_ENTRY(0x2ff),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x300), TBL_ENTRY(0x301), TBL_ENTRY(0x302),
TBL_ENTRY(0x303),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x304), TBL_ENTRY(0x305), TBL_ENTRY(0x306),
TBL_ENTRY(0x307),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x308), TBL_ENTRY(0x309), TBL_ENTRY(0x30a),
TBL_ENTRY(0x30b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x30c), TBL_ENTRY(0x30d), TBL_ENTRY(0x30e),
TBL_ENTRY(0x30f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x310), TBL_ENTRY(0x311), TBL_ENTRY(0x312),
TBL_ENTRY(0x313),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x314), TBL_ENTRY(0x315), TBL_ENTRY(0x316),
TBL_ENTRY(0x317),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x318), TBL_ENTRY(0x319), TBL_ENTRY(0x31a),
TBL_ENTRY(0x31b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x31c), TBL_ENTRY(0x31d), TBL_ENTRY(0x31e),
TBL_ENTRY(0x31f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x320), TBL_ENTRY(0x321), TBL_ENTRY(0x322),
TBL_ENTRY(0x323),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x324), TBL_ENTRY(0x325), TBL_ENTRY(0x326),
TBL_ENTRY(0x327),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x328), TBL_ENTRY(0x329), TBL_ENTRY(0x32a),
TBL_ENTRY(0x32b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x32c), TBL_ENTRY(0x32d), TBL_ENTRY(0x32e),
TBL_ENTRY(0x32f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x330), TBL_ENTRY(0x331), TBL_ENTRY(0x332),
TBL_ENTRY(0x333),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x334), TBL_ENTRY(0x335), TBL_ENTRY(0x336),
TBL_ENTRY(0x337),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x338), TBL_ENTRY(0x339), TBL_ENTRY(0x33a),
TBL_ENTRY(0x33b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x33c), TBL_ENTRY(0x33d), TBL_ENTRY(0x33e),
TBL_ENTRY(0x33f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x340), TBL_ENTRY(0x341), TBL_ENTRY(0x342),
TBL_ENTRY(0x343),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x344), TBL_ENTRY(0x345), TBL_ENTRY(0x346),
TBL_ENTRY(0x347),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x348), TBL_ENTRY(0x349), TBL_ENTRY(0x34a),
TBL_ENTRY(0x34b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x34c), TBL_ENTRY(0x34d), TBL_ENTRY(0x34e),
TBL_ENTRY(0x34f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x350), TBL_ENTRY(0x351), TBL_ENTRY(0x352),
TBL_ENTRY(0x353),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x354), TBL_ENTRY(0x355), TBL_ENTRY(0x356),
TBL_ENTRY(0x357),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x358), TBL_ENTRY(0x359), TBL_ENTRY(0x35a),
TBL_ENTRY(0x35b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x35c), TBL_ENTRY(0x35d), TBL_ENTRY(0x35e),
TBL_ENTRY(0x35f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x360), TBL_ENTRY(0x361), TBL_ENTRY(0x362),
TBL_ENTRY(0x363),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x364), TBL_ENTRY(0x365), TBL_ENTRY(0x366),
TBL_ENTRY(0x367),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x368), TBL_ENTRY(0x369), TBL_ENTRY(0x36a),
TBL_ENTRY(0x36b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x36c), TBL_ENTRY(0x36d), TBL_ENTRY(0x36e),
TBL_ENTRY(0x36f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x370), TBL_ENTRY(0x371), TBL_ENTRY(0x372),
TBL_ENTRY(0x373),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x374), TBL_ENTRY(0x375), TBL_ENTRY(0x376),
TBL_ENTRY(0x377),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x378), TBL_ENTRY(0x379), TBL_ENTRY(0x37a),
TBL_ENTRY(0x37b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x37c), TBL_ENTRY(0x37d), TBL_ENTRY(0x37e),
TBL_ENTRY(0x37f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x380), TBL_ENTRY(0x381), TBL_ENTRY(0x382),
TBL_ENTRY(0x383),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x384), TBL_ENTRY(0x385), TBL_ENTRY(0x386),
TBL_ENTRY(0x387),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x388), TBL_ENTRY(0x389), TBL_ENTRY(0x38a),
TBL_ENTRY(0x38b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x38c), TBL_ENTRY(0x38d), TBL_ENTRY(0x38e),
TBL_ENTRY(0x38f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x390), TBL_ENTRY(0x391), TBL_ENTRY(0x392),
TBL_ENTRY(0x393),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x394), TBL_ENTRY(0x395), TBL_ENTRY(0x396),
TBL_ENTRY(0x397),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x398), TBL_ENTRY(0x399), TBL_ENTRY(0x39a),
TBL_ENTRY(0x39b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x39c), TBL_ENTRY(0x39d), TBL_ENTRY(0x39e),
TBL_ENTRY(0x39f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3a0), TBL_ENTRY(0x3a1), TBL_ENTRY(0x3a2),
TBL_ENTRY(0x3a3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3a4), TBL_ENTRY(0x3a5), TBL_ENTRY(0x3a6),
TBL_ENTRY(0x3a7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3a8), TBL_ENTRY(0x3a9), TBL_ENTRY(0x3aa),
TBL_ENTRY(0x3ab),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3ac), TBL_ENTRY(0x3ad), TBL_ENTRY(0x3ae),
TBL_ENTRY(0x3af),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3b0), TBL_ENTRY(0x3b1), TBL_ENTRY(0x3b2),
TBL_ENTRY(0x3b3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3b4), TBL_ENTRY(0x3b5), TBL_ENTRY(0x3b6),
TBL_ENTRY(0x3b7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3b8), TBL_ENTRY(0x3b9), TBL_ENTRY(0x3ba),
TBL_ENTRY(0x3bb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3bc), TBL_ENTRY(0x3bd), TBL_ENTRY(0x3be),
TBL_ENTRY(0x3bf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3c0), TBL_ENTRY(0x3c1), TBL_ENTRY(0x3c2),
TBL_ENTRY(0x3c3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3c4), TBL_ENTRY(0x3c5), TBL_ENTRY(0x3c6),
TBL_ENTRY(0x3c7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3c8), TBL_ENTRY(0x3c9), TBL_ENTRY(0x3ca),
TBL_ENTRY(0x3cb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3cc), TBL_ENTRY(0x3cd), TBL_ENTRY(0x3ce),
TBL_ENTRY(0x3cf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3d0), TBL_ENTRY(0x3d1), TBL_ENTRY(0x3d2),
TBL_ENTRY(0x3d3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3d4), TBL_ENTRY(0x3d5), TBL_ENTRY(0x3d6),
TBL_ENTRY(0x3d7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3d8), TBL_ENTRY(0x3d9), TBL_ENTRY(0x3da),
TBL_ENTRY(0x3db),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3dc), TBL_ENTRY(0x3dd), TBL_ENTRY(0x3de),
TBL_ENTRY(0x3df),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3e0), TBL_ENTRY(0x3e1), TBL_ENTRY(0x3e2),
TBL_ENTRY(0x3e3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3e4), TBL_ENTRY(0x3e5), TBL_ENTRY(0x3e6),
TBL_ENTRY(0x3e7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3e8), TBL_ENTRY(0x3e9), TBL_ENTRY(0x3ea),
TBL_ENTRY(0x3eb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3ec), TBL_ENTRY(0x3ed), TBL_ENTRY(0x3ee),
TBL_ENTRY(0x3ef),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3f0), TBL_ENTRY(0x3f1), TBL_ENTRY(0x3f2),
TBL_ENTRY(0x3f3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3f4), TBL_ENTRY(0x3f5), TBL_ENTRY(0x3f6),
TBL_ENTRY(0x3f7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3f8), TBL_ENTRY(0x3f9), TBL_ENTRY(0x3fa),
TBL_ENTRY(0x3fb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x3fc), TBL_ENTRY(0x3fd), TBL_ENTRY(0x3fe),
TBL_ENTRY(0x3ff),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x400), TBL_ENTRY(0x401), TBL_ENTRY(0x402),
TBL_ENTRY(0x403),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x404), TBL_ENTRY(0x405), TBL_ENTRY(0x406),
TBL_ENTRY(0x407),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x408), TBL_ENTRY(0x409), TBL_ENTRY(0x40a),
TBL_ENTRY(0x40b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x40c), TBL_ENTRY(0x40d), TBL_ENTRY(0x40e),
TBL_ENTRY(0x40f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x410), TBL_ENTRY(0x411), TBL_ENTRY(0x412),
TBL_ENTRY(0x413),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x414), TBL_ENTRY(0x415), TBL_ENTRY(0x416),
TBL_ENTRY(0x417),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x418), TBL_ENTRY(0x419), TBL_ENTRY(0x41a),
TBL_ENTRY(0x41b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x41c), TBL_ENTRY(0x41d), TBL_ENTRY(0x41e),
TBL_ENTRY(0x41f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x420), TBL_ENTRY(0x421), TBL_ENTRY(0x422),
TBL_ENTRY(0x423),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x424), TBL_ENTRY(0x425), TBL_ENTRY(0x426),
TBL_ENTRY(0x427),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x428), TBL_ENTRY(0x429), TBL_ENTRY(0x42a),
TBL_ENTRY(0x42b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x42c), TBL_ENTRY(0x42d), TBL_ENTRY(0x42e),
TBL_ENTRY(0x42f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x430), TBL_ENTRY(0x431), TBL_ENTRY(0x432),
TBL_ENTRY(0x433),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x434), TBL_ENTRY(0x435), TBL_ENTRY(0x436),
TBL_ENTRY(0x437),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x438), TBL_ENTRY(0x439), TBL_ENTRY(0x43a),
TBL_ENTRY(0x43b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x43c), TBL_ENTRY(0x43d), TBL_ENTRY(0x43e),
TBL_ENTRY(0x43f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x440), TBL_ENTRY(0x441), TBL_ENTRY(0x442),
TBL_ENTRY(0x443),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x444), TBL_ENTRY(0x445), TBL_ENTRY(0x446),
TBL_ENTRY(0x447),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x448), TBL_ENTRY(0x449), TBL_ENTRY(0x44a),
TBL_ENTRY(0x44b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x44c), TBL_ENTRY(0x44d), TBL_ENTRY(0x44e),
TBL_ENTRY(0x44f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x450), TBL_ENTRY(0x451), TBL_ENTRY(0x452),
TBL_ENTRY(0x453),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x454), TBL_ENTRY(0x455), TBL_ENTRY(0x456),
TBL_ENTRY(0x457),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x458), TBL_ENTRY(0x459), TBL_ENTRY(0x45a),
TBL_ENTRY(0x45b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x45c), TBL_ENTRY(0x45d), TBL_ENTRY(0x45e),
TBL_ENTRY(0x45f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x460), TBL_ENTRY(0x461), TBL_ENTRY(0x462),
TBL_ENTRY(0x463),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x464), TBL_ENTRY(0x465), TBL_ENTRY(0x466),
TBL_ENTRY(0x467),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x468), TBL_ENTRY(0x469), TBL_ENTRY(0x46a),
TBL_ENTRY(0x46b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x46c), TBL_ENTRY(0x46d), TBL_ENTRY(0x46e),
TBL_ENTRY(0x46f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x470), TBL_ENTRY(0x471), TBL_ENTRY(0x472),
TBL_ENTRY(0x473),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x474), TBL_ENTRY(0x475), TBL_ENTRY(0x476),
TBL_ENTRY(0x477),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x478), TBL_ENTRY(0x479), TBL_ENTRY(0x47a),
TBL_ENTRY(0x47b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x47c), TBL_ENTRY(0x47d), TBL_ENTRY(0x47e),
TBL_ENTRY(0x47f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x480), TBL_ENTRY(0x481), TBL_ENTRY(0x482),
TBL_ENTRY(0x483),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x484), TBL_ENTRY(0x485), TBL_ENTRY(0x486),
TBL_ENTRY(0x487),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x488), TBL_ENTRY(0x489), TBL_ENTRY(0x48a),
TBL_ENTRY(0x48b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x48c), TBL_ENTRY(0x48d), TBL_ENTRY(0x48e),
TBL_ENTRY(0x48f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x490), TBL_ENTRY(0x491), TBL_ENTRY(0x492),
TBL_ENTRY(0x493),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x494), TBL_ENTRY(0x495), TBL_ENTRY(0x496),
TBL_ENTRY(0x497),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x498), TBL_ENTRY(0x499), TBL_ENTRY(0x49a),
TBL_ENTRY(0x49b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x49c), TBL_ENTRY(0x49d), TBL_ENTRY(0x49e),
TBL_ENTRY(0x49f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4a0), TBL_ENTRY(0x4a1), TBL_ENTRY(0x4a2),
TBL_ENTRY(0x4a3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4a4), TBL_ENTRY(0x4a5), TBL_ENTRY(0x4a6),
TBL_ENTRY(0x4a7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4a8), TBL_ENTRY(0x4a9), TBL_ENTRY(0x4aa),
TBL_ENTRY(0x4ab),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4ac), TBL_ENTRY(0x4ad), TBL_ENTRY(0x4ae),
TBL_ENTRY(0x4af),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4b0), TBL_ENTRY(0x4b1), TBL_ENTRY(0x4b2),
TBL_ENTRY(0x4b3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4b4), TBL_ENTRY(0x4b5), TBL_ENTRY(0x4b6),
TBL_ENTRY(0x4b7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4b8), TBL_ENTRY(0x4b9), TBL_ENTRY(0x4ba),
TBL_ENTRY(0x4bb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4bc), TBL_ENTRY(0x4bd), TBL_ENTRY(0x4be),
TBL_ENTRY(0x4bf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4c0), TBL_ENTRY(0x4c1), TBL_ENTRY(0x4c2),
TBL_ENTRY(0x4c3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4c4), TBL_ENTRY(0x4c5), TBL_ENTRY(0x4c6),
TBL_ENTRY(0x4c7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4c8), TBL_ENTRY(0x4c9), TBL_ENTRY(0x4ca),
TBL_ENTRY(0x4cb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4cc), TBL_ENTRY(0x4cd), TBL_ENTRY(0x4ce),
TBL_ENTRY(0x4cf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4d0), TBL_ENTRY(0x4d1), TBL_ENTRY(0x4d2),
TBL_ENTRY(0x4d3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4d4), TBL_ENTRY(0x4d5), TBL_ENTRY(0x4d6),
TBL_ENTRY(0x4d7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4d8), TBL_ENTRY(0x4d9), TBL_ENTRY(0x4da),
TBL_ENTRY(0x4db),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4dc), TBL_ENTRY(0x4dd), TBL_ENTRY(0x4de),
TBL_ENTRY(0x4df),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4e0), TBL_ENTRY(0x4e1), TBL_ENTRY(0x4e2),
TBL_ENTRY(0x4e3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4e4), TBL_ENTRY(0x4e5), TBL_ENTRY(0x4e6),
TBL_ENTRY(0x4e7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4e8), TBL_ENTRY(0x4e9), TBL_ENTRY(0x4ea),
TBL_ENTRY(0x4eb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4ec), TBL_ENTRY(0x4ed), TBL_ENTRY(0x4ee),
TBL_ENTRY(0x4ef),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4f0), TBL_ENTRY(0x4f1), TBL_ENTRY(0x4f2),
TBL_ENTRY(0x4f3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4f4), TBL_ENTRY(0x4f5), TBL_ENTRY(0x4f6),
TBL_ENTRY(0x4f7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4f8), TBL_ENTRY(0x4f9), TBL_ENTRY(0x4fa),
TBL_ENTRY(0x4fb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x4fc), TBL_ENTRY(0x4fd), TBL_ENTRY(0x4fe),
TBL_ENTRY(0x4ff),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x500), TBL_ENTRY(0x501), TBL_ENTRY(0x502),
TBL_ENTRY(0x503),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x504), TBL_ENTRY(0x505), TBL_ENTRY(0x506),
TBL_ENTRY(0x507),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x508), TBL_ENTRY(0x509), TBL_ENTRY(0x50a),
TBL_ENTRY(0x50b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x50c), TBL_ENTRY(0x50d), TBL_ENTRY(0x50e),
TBL_ENTRY(0x50f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x510), TBL_ENTRY(0x511), TBL_ENTRY(0x512),
TBL_ENTRY(0x513),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x514), TBL_ENTRY(0x515), TBL_ENTRY(0x516),
TBL_ENTRY(0x517),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x518), TBL_ENTRY(0x519), TBL_ENTRY(0x51a),
TBL_ENTRY(0x51b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x51c), TBL_ENTRY(0x51d), TBL_ENTRY(0x51e),
TBL_ENTRY(0x51f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x520), TBL_ENTRY(0x521), TBL_ENTRY(0x522),
TBL_ENTRY(0x523),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x524), TBL_ENTRY(0x525), TBL_ENTRY(0x526),
TBL_ENTRY(0x527),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x528), TBL_ENTRY(0x529), TBL_ENTRY(0x52a),
TBL_ENTRY(0x52b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x52c), TBL_ENTRY(0x52d), TBL_ENTRY(0x52e),
TBL_ENTRY(0x52f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x530), TBL_ENTRY(0x531), TBL_ENTRY(0x532),
TBL_ENTRY(0x533),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x534), TBL_ENTRY(0x535), TBL_ENTRY(0x536),
TBL_ENTRY(0x537),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x538), TBL_ENTRY(0x539), TBL_ENTRY(0x53a),
TBL_ENTRY(0x53b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0x53c), TBL_ENTRY(0x53d), TBL_ENTRY(0x53e),
TBL_ENTRY(0x53f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x563),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x567),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x56f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x573),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x577),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x57b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x57f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x583),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x587),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x58b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x58f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x593),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x597),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x59b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x59f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5a3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5a7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5ab),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5af),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5b3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5b7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5bb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5bf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5c3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5c7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5cb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5cf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5d3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5d7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5db),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5df),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5e3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5e7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5eb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5ef),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5f3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5f7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5fb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x5ff),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x603),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x607),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x60b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x60f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x613),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x617),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x61b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x61f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x623),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x627),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x62b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x62f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x633),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x637),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x63b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x63f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x643),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x647),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x64b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x64f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x653),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x657),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x65b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x65f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x663),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x667),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x66b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x66f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x673),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x677),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x67b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x67f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x683),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x687),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x68b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x68f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x693),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x697),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x69b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x69f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6a3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6a7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6ab),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6af),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6b3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6b7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6bb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6bf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6c3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6c7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6cb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6cf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6d3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6d7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6db),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6df),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6e3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6e7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6eb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6ef),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6f3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6f7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6fb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x6ff),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x703),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x8b3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x8bb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x8bf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x8c3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x8c7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x8cb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x8cf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x8d3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x8d7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x8db),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x8df),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x8e3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x8e7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x8eb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x8ef),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x8f3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x8f7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x8fb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x8ff),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x903),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x907),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x90b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x90f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x913),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x917),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x91b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x91f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x923),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x927),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x92b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x92f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x933),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x937),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x93b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x93f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x943),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x947),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x94b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x94f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x953),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x957),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x95b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x95f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x963),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x967),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x96b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x96f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x973),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x977),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x97b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x97f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x983),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x987),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x98b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x98f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x993),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x997),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x99b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x99f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9a3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9a7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9ab),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9af),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9b3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9b7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9bb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9bf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9c3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9c7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9cb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9cf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9d3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9d7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9db),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9df),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9e3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9e7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9eb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9ef),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9f3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9f7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9fb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0x9ff),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa03),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa07),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa0b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa0f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa13),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa17),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa1b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa1f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa23),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa27),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa2b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa2f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa33),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa37),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa3b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa3f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa43),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa47),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa4b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa4f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa53),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa57),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa5b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa5f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa63),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa67),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa6b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa6f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa73),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa77),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa7b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa7f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa83),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa87),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
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TBL_ENTRY(0xa8b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xa8c), TBL_ENTRY(0xa8d), TBL_ENTRY(0xa8e),
TBL_ENTRY(0xa8f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xa90), TBL_ENTRY(0xa91), TBL_ENTRY(0xa92),
TBL_ENTRY(0xa93),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xa94), TBL_ENTRY(0xa95), TBL_ENTRY(0xa96),
TBL_ENTRY(0xa97),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xa98), TBL_ENTRY(0xa99), TBL_ENTRY(0xa9a),
TBL_ENTRY(0xa9b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xa9c), TBL_ENTRY(0xa9d), TBL_ENTRY(0xa9e),
TBL_ENTRY(0xa9f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xaa0), TBL_ENTRY(0xaa1), TBL_ENTRY(0xaa2),
TBL_ENTRY(0xaa3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xaa4), TBL_ENTRY(0xaa5), TBL_ENTRY(0xaa6),
TBL_ENTRY(0xaa7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xaa8), TBL_ENTRY(0xaa9), TBL_ENTRY(0xaaa),
TBL_ENTRY(0xaab),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xaac), TBL_ENTRY(0xaad), TBL_ENTRY(0xaae),
TBL_ENTRY(0xaaf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xab0), TBL_ENTRY(0xab1), TBL_ENTRY(0xab2),
TBL_ENTRY(0xab3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xab4), TBL_ENTRY(0xab5), TBL_ENTRY(0xab6),
TBL_ENTRY(0xab7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xab8), TBL_ENTRY(0xab9), TBL_ENTRY(0xaba),
TBL_ENTRY(0xabb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xabc), TBL_ENTRY(0xabd), TBL_ENTRY(0xabe),
TBL_ENTRY(0xabf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xac0), TBL_ENTRY(0xac1), TBL_ENTRY(0xac2),
TBL_ENTRY(0xac3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xac4), TBL_ENTRY(0xac5), TBL_ENTRY(0xac6),
TBL_ENTRY(0xac7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xac8), TBL_ENTRY(0xac9), TBL_ENTRY(0xaca),
TBL_ENTRY(0xacb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xacc), TBL_ENTRY(0xacd), TBL_ENTRY(0xace),
TBL_ENTRY(0xacf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xad0), TBL_ENTRY(0xad1), TBL_ENTRY(0xad2),
TBL_ENTRY(0xad3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xad4), TBL_ENTRY(0xad5), TBL_ENTRY(0xad6),
TBL_ENTRY(0xad7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xad8), TBL_ENTRY(0xad9), TBL_ENTRY(0xada),
TBL_ENTRY(0xadb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xadc), TBL_ENTRY(0xadd), TBL_ENTRY(0xade),
TBL_ENTRY(0xadf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xae0), TBL_ENTRY(0xae1), TBL_ENTRY(0xae2),
TBL_ENTRY(0xae3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xae4), TBL_ENTRY(0xae5), TBL_ENTRY(0xae6),
TBL_ENTRY(0xae7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xae8), TBL_ENTRY(0xae9), TBL_ENTRY(0xaea),
TBL_ENTRY(0xaeb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xaec), TBL_ENTRY(0xaed), TBL_ENTRY(0xaee),
TBL_ENTRY(0xaef),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xaf0), TBL_ENTRY(0xaf1), TBL_ENTRY(0xaf2),
TBL_ENTRY(0xaf3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xaf4), TBL_ENTRY(0xaf5), TBL_ENTRY(0xaf6),
TBL_ENTRY(0xaf7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xaf8), TBL_ENTRY(0xaf9), TBL_ENTRY(0xafa),
TBL_ENTRY(0xafb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xafc), TBL_ENTRY(0xafd), TBL_ENTRY(0xafe),
TBL_ENTRY(0xaff),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb00), TBL_ENTRY(0xb01), TBL_ENTRY(0xb02),
TBL_ENTRY(0xb03),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb04), TBL_ENTRY(0xb05), TBL_ENTRY(0xb06),
TBL_ENTRY(0xb07),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb08), TBL_ENTRY(0xb09), TBL_ENTRY(0xb0a),
TBL_ENTRY(0xb0b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb0c), TBL_ENTRY(0xb0d), TBL_ENTRY(0xb0e),
TBL_ENTRY(0xb0f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb10), TBL_ENTRY(0xb11), TBL_ENTRY(0xb12),
TBL_ENTRY(0xb13),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb14), TBL_ENTRY(0xb15), TBL_ENTRY(0xb16),
TBL_ENTRY(0xb17),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb18), TBL_ENTRY(0xb19), TBL_ENTRY(0xb1a),
TBL_ENTRY(0xb1b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb1c), TBL_ENTRY(0xb1d), TBL_ENTRY(0xb1e),
TBL_ENTRY(0xb1f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb20), TBL_ENTRY(0xb21), TBL_ENTRY(0xb22),
TBL_ENTRY(0xb23),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb24), TBL_ENTRY(0xb25), TBL_ENTRY(0xb26),
TBL_ENTRY(0xb27),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb28), TBL_ENTRY(0xb29), TBL_ENTRY(0xb2a),
TBL_ENTRY(0xb2b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb2c), TBL_ENTRY(0xb2d), TBL_ENTRY(0xb2e),
TBL_ENTRY(0xb2f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb30), TBL_ENTRY(0xb31), TBL_ENTRY(0xb32),
TBL_ENTRY(0xb33),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb34), TBL_ENTRY(0xb35), TBL_ENTRY(0xb36),
TBL_ENTRY(0xb37),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb38), TBL_ENTRY(0xb39), TBL_ENTRY(0xb3a),
TBL_ENTRY(0xb3b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb3c), TBL_ENTRY(0xb3d), TBL_ENTRY(0xb3e),
TBL_ENTRY(0xb3f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb40), TBL_ENTRY(0xb41), TBL_ENTRY(0xb42),
TBL_ENTRY(0xb43),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb44), TBL_ENTRY(0xb45), TBL_ENTRY(0xb46),
TBL_ENTRY(0xb47),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb48), TBL_ENTRY(0xb49), TBL_ENTRY(0xb4a),
TBL_ENTRY(0xb4b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb4c), TBL_ENTRY(0xb4d), TBL_ENTRY(0xb4e),
TBL_ENTRY(0xb4f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb50), TBL_ENTRY(0xb51), TBL_ENTRY(0xb52),
TBL_ENTRY(0xb53),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb54), TBL_ENTRY(0xb55), TBL_ENTRY(0xb56),
TBL_ENTRY(0xb57),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb58), TBL_ENTRY(0xb59), TBL_ENTRY(0xb5a),
TBL_ENTRY(0xb5b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb5c), TBL_ENTRY(0xb5d), TBL_ENTRY(0xb5e),
TBL_ENTRY(0xb5f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb60), TBL_ENTRY(0xb61), TBL_ENTRY(0xb62),
TBL_ENTRY(0xb63),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb64), TBL_ENTRY(0xb65), TBL_ENTRY(0xb66),
TBL_ENTRY(0xb67),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb68), TBL_ENTRY(0xb69), TBL_ENTRY(0xb6a),
TBL_ENTRY(0xb6b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb6c), TBL_ENTRY(0xb6d), TBL_ENTRY(0xb6e),
TBL_ENTRY(0xb6f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb70), TBL_ENTRY(0xb71), TBL_ENTRY(0xb72),
TBL_ENTRY(0xb73),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb74), TBL_ENTRY(0xb75), TBL_ENTRY(0xb76),
TBL_ENTRY(0xb77),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb78), TBL_ENTRY(0xb79), TBL_ENTRY(0xb7a),
TBL_ENTRY(0xb7b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb7c), TBL_ENTRY(0xb7d), TBL_ENTRY(0xb7e),
TBL_ENTRY(0xb7f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb80), TBL_ENTRY(0xb81), TBL_ENTRY(0xb82),
TBL_ENTRY(0xb83),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb84), TBL_ENTRY(0xb85), TBL_ENTRY(0xb86),
TBL_ENTRY(0xb87),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb88), TBL_ENTRY(0xb89), TBL_ENTRY(0xb8a),
TBL_ENTRY(0xb8b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb8c), TBL_ENTRY(0xb8d), TBL_ENTRY(0xb8e),
TBL_ENTRY(0xb8f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb90), TBL_ENTRY(0xb91), TBL_ENTRY(0xb92),
TBL_ENTRY(0xb93),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb94), TBL_ENTRY(0xb95), TBL_ENTRY(0xb96),
TBL_ENTRY(0xb97),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb98), TBL_ENTRY(0xb99), TBL_ENTRY(0xb9a),
TBL_ENTRY(0xb9b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xb9c), TBL_ENTRY(0xb9d), TBL_ENTRY(0xb9e),
TBL_ENTRY(0xb9f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xba0), TBL_ENTRY(0xba1), TBL_ENTRY(0xba2),
TBL_ENTRY(0xba3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xba4), TBL_ENTRY(0xba5), TBL_ENTRY(0xba6),
TBL_ENTRY(0xba7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xba8), TBL_ENTRY(0xba9), TBL_ENTRY(0xbaa),
TBL_ENTRY(0xbab),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbac), TBL_ENTRY(0xbad), TBL_ENTRY(0xbae),
TBL_ENTRY(0xbaf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbb0), TBL_ENTRY(0xbb1), TBL_ENTRY(0xbb2),
TBL_ENTRY(0xbb3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbb4), TBL_ENTRY(0xbb5), TBL_ENTRY(0xbb6),
TBL_ENTRY(0xbb7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbb8), TBL_ENTRY(0xbb9), TBL_ENTRY(0xbba),
TBL_ENTRY(0xbbb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbbc), TBL_ENTRY(0xbbd), TBL_ENTRY(0xbbe),
TBL_ENTRY(0xbbf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbc0), TBL_ENTRY(0xbc1), TBL_ENTRY(0xbc2),
TBL_ENTRY(0xbc3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbc4), TBL_ENTRY(0xbc5), TBL_ENTRY(0xbc6),
TBL_ENTRY(0xbc7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbc8), TBL_ENTRY(0xbc9), TBL_ENTRY(0xbca),
TBL_ENTRY(0xbcb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbcc), TBL_ENTRY(0xbcd), TBL_ENTRY(0xbce),
TBL_ENTRY(0xbcf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbd0), TBL_ENTRY(0xbd1), TBL_ENTRY(0xbd2),
TBL_ENTRY(0xbd3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbd4), TBL_ENTRY(0xbd5), TBL_ENTRY(0xbd6),
TBL_ENTRY(0xbd7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbd8), TBL_ENTRY(0xbd9), TBL_ENTRY(0xbda),
TBL_ENTRY(0xbdb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbdc), TBL_ENTRY(0xbdd), TBL_ENTRY(0xbde),
TBL_ENTRY(0xbdf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbe0), TBL_ENTRY(0xbe1), TBL_ENTRY(0xbe2),
TBL_ENTRY(0xbe3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbe4), TBL_ENTRY(0xbe5), TBL_ENTRY(0xbe6),
TBL_ENTRY(0xbe7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbe8), TBL_ENTRY(0xbe9), TBL_ENTRY(0xbea),
TBL_ENTRY(0xbeb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbec), TBL_ENTRY(0xbed), TBL_ENTRY(0xbee),
TBL_ENTRY(0xbef),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbf0), TBL_ENTRY(0xbf1), TBL_ENTRY(0xbf2),
TBL_ENTRY(0xbf3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbf4), TBL_ENTRY(0xbf5), TBL_ENTRY(0xbf6),
TBL_ENTRY(0xbf7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbf8), TBL_ENTRY(0xbf9), TBL_ENTRY(0xbfa),
TBL_ENTRY(0xbfb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xbfc), TBL_ENTRY(0xbfd), TBL_ENTRY(0xbfe),
TBL_ENTRY(0xbff),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc00), TBL_ENTRY(0xc01), TBL_ENTRY(0xc02),
TBL_ENTRY(0xc03),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc04), TBL_ENTRY(0xc05), TBL_ENTRY(0xc06),
TBL_ENTRY(0xc07),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc08), TBL_ENTRY(0xc09), TBL_ENTRY(0xc0a),
TBL_ENTRY(0xc0b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc0c), TBL_ENTRY(0xc0d), TBL_ENTRY(0xc0e),
TBL_ENTRY(0xc0f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc10), TBL_ENTRY(0xc11), TBL_ENTRY(0xc12),
TBL_ENTRY(0xc13),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc14), TBL_ENTRY(0xc15), TBL_ENTRY(0xc16),
TBL_ENTRY(0xc17),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc18), TBL_ENTRY(0xc19), TBL_ENTRY(0xc1a),
TBL_ENTRY(0xc1b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc1c), TBL_ENTRY(0xc1d), TBL_ENTRY(0xc1e),
TBL_ENTRY(0xc1f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc20), TBL_ENTRY(0xc21), TBL_ENTRY(0xc22),
TBL_ENTRY(0xc23),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc24), TBL_ENTRY(0xc25), TBL_ENTRY(0xc26),
TBL_ENTRY(0xc27),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc28), TBL_ENTRY(0xc29), TBL_ENTRY(0xc2a),
TBL_ENTRY(0xc2b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc2c), TBL_ENTRY(0xc2d), TBL_ENTRY(0xc2e),
TBL_ENTRY(0xc2f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc30), TBL_ENTRY(0xc31), TBL_ENTRY(0xc32),
TBL_ENTRY(0xc33),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc34), TBL_ENTRY(0xc35), TBL_ENTRY(0xc36),
TBL_ENTRY(0xc37),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc38), TBL_ENTRY(0xc39), TBL_ENTRY(0xc3a),
TBL_ENTRY(0xc3b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc3c), TBL_ENTRY(0xc3d), TBL_ENTRY(0xc3e),
TBL_ENTRY(0xc3f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc40), TBL_ENTRY(0xc41), TBL_ENTRY(0xc42),
TBL_ENTRY(0xc43),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc44), TBL_ENTRY(0xc45), TBL_ENTRY(0xc46),
TBL_ENTRY(0xc47),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc48), TBL_ENTRY(0xc49), TBL_ENTRY(0xc4a),
TBL_ENTRY(0xc4b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc4c), TBL_ENTRY(0xc4d), TBL_ENTRY(0xc4e),
TBL_ENTRY(0xc4f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc50), TBL_ENTRY(0xc51), TBL_ENTRY(0xc52),
TBL_ENTRY(0xc53),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc54), TBL_ENTRY(0xc55), TBL_ENTRY(0xc56),
TBL_ENTRY(0xc57),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc58), TBL_ENTRY(0xc59), TBL_ENTRY(0xc5a),
TBL_ENTRY(0xc5b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc5c), TBL_ENTRY(0xc5d), TBL_ENTRY(0xc5e),
TBL_ENTRY(0xc5f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc60), TBL_ENTRY(0xc61), TBL_ENTRY(0xc62),
TBL_ENTRY(0xc63),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc64), TBL_ENTRY(0xc65), TBL_ENTRY(0xc66),
TBL_ENTRY(0xc67),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc68), TBL_ENTRY(0xc69), TBL_ENTRY(0xc6a),
TBL_ENTRY(0xc6b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc6c), TBL_ENTRY(0xc6d), TBL_ENTRY(0xc6e),
TBL_ENTRY(0xc6f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc70), TBL_ENTRY(0xc71), TBL_ENTRY(0xc72),
TBL_ENTRY(0xc73),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc74), TBL_ENTRY(0xc75), TBL_ENTRY(0xc76),
TBL_ENTRY(0xc77),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc78), TBL_ENTRY(0xc79), TBL_ENTRY(0xc7a),
TBL_ENTRY(0xc7b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc7c), TBL_ENTRY(0xc7d), TBL_ENTRY(0xc7e),
TBL_ENTRY(0xc7f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc80), TBL_ENTRY(0xc81), TBL_ENTRY(0xc82),
TBL_ENTRY(0xc83),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc84), TBL_ENTRY(0xc85), TBL_ENTRY(0xc86),
TBL_ENTRY(0xc87),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc88), TBL_ENTRY(0xc89), TBL_ENTRY(0xc8a),
TBL_ENTRY(0xc8b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc8c), TBL_ENTRY(0xc8d), TBL_ENTRY(0xc8e),
TBL_ENTRY(0xc8f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc90), TBL_ENTRY(0xc91), TBL_ENTRY(0xc92),
TBL_ENTRY(0xc93),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc94), TBL_ENTRY(0xc95), TBL_ENTRY(0xc96),
TBL_ENTRY(0xc97),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc98), TBL_ENTRY(0xc99), TBL_ENTRY(0xc9a),
TBL_ENTRY(0xc9b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xc9c), TBL_ENTRY(0xc9d), TBL_ENTRY(0xc9e),
TBL_ENTRY(0xc9f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xca0), TBL_ENTRY(0xca1), TBL_ENTRY(0xca2),
TBL_ENTRY(0xca3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xca4), TBL_ENTRY(0xca5), TBL_ENTRY(0xca6),
TBL_ENTRY(0xca7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xca8), TBL_ENTRY(0xca9), TBL_ENTRY(0xcaa),
TBL_ENTRY(0xcab),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xcac), TBL_ENTRY(0xcad), TBL_ENTRY(0xcae),
TBL_ENTRY(0xcaf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xcb0), TBL_ENTRY(0xcb1), TBL_ENTRY(0xcb2),
TBL_ENTRY(0xcb3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xcb4), TBL_ENTRY(0xcb5), TBL_ENTRY(0xcb6),
TBL_ENTRY(0xcb7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xcb8), TBL_ENTRY(0xcb9), TBL_ENTRY(0xcba),
TBL_ENTRY(0xcbb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xcbc), TBL_ENTRY(0xcbd), TBL_ENTRY(0xcbe),
TBL_ENTRY(0xcbf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xcc0), TBL_ENTRY(0xcc1), TBL_ENTRY(0xcc2),
TBL_ENTRY(0xcc3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xcc4), TBL_ENTRY(0xcc5), TBL_ENTRY(0xcc6),
TBL_ENTRY(0xcc7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xcc8), TBL_ENTRY(0xcc9), TBL_ENTRY(0xcca),
TBL_ENTRY(0xccb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xccc), TBL_ENTRY(0xccd), TBL_ENTRY(0xcce),
TBL_ENTRY(0xccf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xcd0), TBL_ENTRY(0xcd1), TBL_ENTRY(0xcd2),
TBL_ENTRY(0xcd3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xcd4), TBL_ENTRY(0xcd5), TBL_ENTRY(0xcd6),
TBL_ENTRY(0xcd7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xcd8), TBL_ENTRY(0xcd9), TBL_ENTRY(0xcda),
TBL_ENTRY(0xcdb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xcdc), TBL_ENTRY(0xcdd), TBL_ENTRY(0xcde),
TBL_ENTRY(0xcdf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xce0), TBL_ENTRY(0xce1), TBL_ENTRY(0xce2),
TBL_ENTRY(0xce3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xce4), TBL_ENTRY(0xce5), TBL_ENTRY(0xce6),
TBL_ENTRY(0xce7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xce8), TBL_ENTRY(0xce9), TBL_ENTRY(0xcea),
TBL_ENTRY(0xceb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xcec), TBL_ENTRY(0xced), TBL_ENTRY(0xcee),
TBL_ENTRY(0xcef),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xcf0), TBL_ENTRY(0xcf1), TBL_ENTRY(0xcf2),
TBL_ENTRY(0xcf3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xcf4), TBL_ENTRY(0xcf5), TBL_ENTRY(0xcf6),
TBL_ENTRY(0xcf7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xcf8), TBL_ENTRY(0xcf9), TBL_ENTRY(0xcfa),
TBL_ENTRY(0xcfb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xcfc), TBL_ENTRY(0xcfd), TBL_ENTRY(0xcfe),
TBL_ENTRY(0xcff),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd00), TBL_ENTRY(0xd01), TBL_ENTRY(0xd02),
TBL_ENTRY(0xd03),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd04), TBL_ENTRY(0xd05), TBL_ENTRY(0xd06),
TBL_ENTRY(0xd07),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd08), TBL_ENTRY(0xd09), TBL_ENTRY(0xd0a),
TBL_ENTRY(0xd0b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd0c), TBL_ENTRY(0xd0d), TBL_ENTRY(0xd0e),
TBL_ENTRY(0xd0f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd10), TBL_ENTRY(0xd11), TBL_ENTRY(0xd12),
TBL_ENTRY(0xd13),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd14), TBL_ENTRY(0xd15), TBL_ENTRY(0xd16),
TBL_ENTRY(0xd17),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd18), TBL_ENTRY(0xd19), TBL_ENTRY(0xd1a),
TBL_ENTRY(0xd1b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd1c), TBL_ENTRY(0xd1d), TBL_ENTRY(0xd1e),
TBL_ENTRY(0xd1f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd20), TBL_ENTRY(0xd21), TBL_ENTRY(0xd22),
TBL_ENTRY(0xd23),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd24), TBL_ENTRY(0xd25), TBL_ENTRY(0xd26),
TBL_ENTRY(0xd27),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd28), TBL_ENTRY(0xd29), TBL_ENTRY(0xd2a),
TBL_ENTRY(0xd2b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd2c), TBL_ENTRY(0xd2d), TBL_ENTRY(0xd2e),
TBL_ENTRY(0xd2f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd30), TBL_ENTRY(0xd31), TBL_ENTRY(0xd32),
TBL_ENTRY(0xd33),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd34), TBL_ENTRY(0xd35), TBL_ENTRY(0xd36),
TBL_ENTRY(0xd37),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd38), TBL_ENTRY(0xd39), TBL_ENTRY(0xd3a),
TBL_ENTRY(0xd3b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd3c), TBL_ENTRY(0xd3d), TBL_ENTRY(0xd3e),
TBL_ENTRY(0xd3f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd40), TBL_ENTRY(0xd41), TBL_ENTRY(0xd42),
TBL_ENTRY(0xd43),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd44), TBL_ENTRY(0xd45), TBL_ENTRY(0xd46),
TBL_ENTRY(0xd47),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd48), TBL_ENTRY(0xd49), TBL_ENTRY(0xd4a),
TBL_ENTRY(0xd4b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd4c), TBL_ENTRY(0xd4d), TBL_ENTRY(0xd4e),
TBL_ENTRY(0xd4f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd50), TBL_ENTRY(0xd51), TBL_ENTRY(0xd52),
TBL_ENTRY(0xd53),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd54), TBL_ENTRY(0xd55), TBL_ENTRY(0xd56),
TBL_ENTRY(0xd57),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd58), TBL_ENTRY(0xd59), TBL_ENTRY(0xd5a),
TBL_ENTRY(0xd5b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd5c), TBL_ENTRY(0xd5d), TBL_ENTRY(0xd5e),
TBL_ENTRY(0xd5f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd60), TBL_ENTRY(0xd61), TBL_ENTRY(0xd62),
TBL_ENTRY(0xd63),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd64), TBL_ENTRY(0xd65), TBL_ENTRY(0xd66),
TBL_ENTRY(0xd67),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd68), TBL_ENTRY(0xd69), TBL_ENTRY(0xd6a),
TBL_ENTRY(0xd6b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd6c), TBL_ENTRY(0xd6d), TBL_ENTRY(0xd6e),
TBL_ENTRY(0xd6f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd70), TBL_ENTRY(0xd71), TBL_ENTRY(0xd72),
TBL_ENTRY(0xd73),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd74), TBL_ENTRY(0xd75), TBL_ENTRY(0xd76),
TBL_ENTRY(0xd77),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd78), TBL_ENTRY(0xd79), TBL_ENTRY(0xd7a),
TBL_ENTRY(0xd7b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd7c), TBL_ENTRY(0xd7d), TBL_ENTRY(0xd7e),
TBL_ENTRY(0xd7f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd80), TBL_ENTRY(0xd81), TBL_ENTRY(0xd82),
TBL_ENTRY(0xd83),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd84), TBL_ENTRY(0xd85), TBL_ENTRY(0xd86),
TBL_ENTRY(0xd87),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd88), TBL_ENTRY(0xd89), TBL_ENTRY(0xd8a),
TBL_ENTRY(0xd8b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd8c), TBL_ENTRY(0xd8d), TBL_ENTRY(0xd8e),
TBL_ENTRY(0xd8f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd90), TBL_ENTRY(0xd91), TBL_ENTRY(0xd92),
TBL_ENTRY(0xd93),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd94), TBL_ENTRY(0xd95), TBL_ENTRY(0xd96),
TBL_ENTRY(0xd97),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd98), TBL_ENTRY(0xd99), TBL_ENTRY(0xd9a),
TBL_ENTRY(0xd9b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xd9c), TBL_ENTRY(0xd9d), TBL_ENTRY(0xd9e),
TBL_ENTRY(0xd9f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xda0), TBL_ENTRY(0xda1), TBL_ENTRY(0xda2),
TBL_ENTRY(0xda3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xda4), TBL_ENTRY(0xda5), TBL_ENTRY(0xda6),
TBL_ENTRY(0xda7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xda8), TBL_ENTRY(0xda9), TBL_ENTRY(0xdaa),
TBL_ENTRY(0xdab),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xdac), TBL_ENTRY(0xdad), TBL_ENTRY(0xdae),
TBL_ENTRY(0xdaf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xdb0), TBL_ENTRY(0xdb1), TBL_ENTRY(0xdb2),
TBL_ENTRY(0xdb3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xdb4), TBL_ENTRY(0xdb5), TBL_ENTRY(0xdb6),
TBL_ENTRY(0xdb7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xdb8), TBL_ENTRY(0xdb9), TBL_ENTRY(0xdba),
TBL_ENTRY(0xdbb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xdbc), TBL_ENTRY(0xdbd), TBL_ENTRY(0xdbe),
TBL_ENTRY(0xdbf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xdc0), TBL_ENTRY(0xdc1), TBL_ENTRY(0xdc2),
TBL_ENTRY(0xdc3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xdc4), TBL_ENTRY(0xdc5), TBL_ENTRY(0xdc6),
TBL_ENTRY(0xdc7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xdc8), TBL_ENTRY(0xdc9), TBL_ENTRY(0xdca),
TBL_ENTRY(0xdcb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xdcc), TBL_ENTRY(0xdcd), TBL_ENTRY(0xdce),
TBL_ENTRY(0xdcf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xdd0), TBL_ENTRY(0xdd1), TBL_ENTRY(0xdd2),
TBL_ENTRY(0xdd3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xdd4), TBL_ENTRY(0xdd5), TBL_ENTRY(0xdd6),
TBL_ENTRY(0xdd7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xdd8), TBL_ENTRY(0xdd9), TBL_ENTRY(0xdda),
TBL_ENTRY(0xddb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xddc), TBL_ENTRY(0xddd), TBL_ENTRY(0xdde),
TBL_ENTRY(0xddf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xde0), TBL_ENTRY(0xde1), TBL_ENTRY(0xde2),
TBL_ENTRY(0xde3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xde4), TBL_ENTRY(0xde5), TBL_ENTRY(0xde6),
TBL_ENTRY(0xde7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xde8), TBL_ENTRY(0xde9), TBL_ENTRY(0xdea),
TBL_ENTRY(0xdeb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xdec), TBL_ENTRY(0xded), TBL_ENTRY(0xdee),
TBL_ENTRY(0xdef),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xdf0), TBL_ENTRY(0xdf1), TBL_ENTRY(0xdf2),
TBL_ENTRY(0xdf3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xdf4), TBL_ENTRY(0xdf5), TBL_ENTRY(0xdf6),
TBL_ENTRY(0xdf7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xdf8), TBL_ENTRY(0xdf9), TBL_ENTRY(0xdfa),
TBL_ENTRY(0xdfb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xdfc), TBL_ENTRY(0xdfd), TBL_ENTRY(0xdfe),
TBL_ENTRY(0xdff),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe00), TBL_ENTRY(0xe01), TBL_ENTRY(0xe02),
TBL_ENTRY(0xe03),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe04), TBL_ENTRY(0xe05), TBL_ENTRY(0xe06),
TBL_ENTRY(0xe07),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe08), TBL_ENTRY(0xe09), TBL_ENTRY(0xe0a),
TBL_ENTRY(0xe0b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe0c), TBL_ENTRY(0xe0d), TBL_ENTRY(0xe0e),
TBL_ENTRY(0xe0f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe10), TBL_ENTRY(0xe11), TBL_ENTRY(0xe12),
TBL_ENTRY(0xe13),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe14), TBL_ENTRY(0xe15), TBL_ENTRY(0xe16),
TBL_ENTRY(0xe17),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe18), TBL_ENTRY(0xe19), TBL_ENTRY(0xe1a),
TBL_ENTRY(0xe1b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe1c), TBL_ENTRY(0xe1d), TBL_ENTRY(0xe1e),
TBL_ENTRY(0xe1f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe20), TBL_ENTRY(0xe21), TBL_ENTRY(0xe22),
TBL_ENTRY(0xe23),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe24), TBL_ENTRY(0xe25), TBL_ENTRY(0xe26),
TBL_ENTRY(0xe27),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe28), TBL_ENTRY(0xe29), TBL_ENTRY(0xe2a),
TBL_ENTRY(0xe2b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe2c), TBL_ENTRY(0xe2d), TBL_ENTRY(0xe2e),
TBL_ENTRY(0xe2f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe30), TBL_ENTRY(0xe31), TBL_ENTRY(0xe32),
TBL_ENTRY(0xe33),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe34), TBL_ENTRY(0xe35), TBL_ENTRY(0xe36),
TBL_ENTRY(0xe37),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe38), TBL_ENTRY(0xe39), TBL_ENTRY(0xe3a),
TBL_ENTRY(0xe3b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe3c), TBL_ENTRY(0xe3d), TBL_ENTRY(0xe3e),
TBL_ENTRY(0xe3f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe40), TBL_ENTRY(0xe41), TBL_ENTRY(0xe42),
TBL_ENTRY(0xe43),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe44), TBL_ENTRY(0xe45), TBL_ENTRY(0xe46),
TBL_ENTRY(0xe47),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe48), TBL_ENTRY(0xe49), TBL_ENTRY(0xe4a),
TBL_ENTRY(0xe4b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe4c), TBL_ENTRY(0xe4d), TBL_ENTRY(0xe4e),
TBL_ENTRY(0xe4f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe50), TBL_ENTRY(0xe51), TBL_ENTRY(0xe52),
TBL_ENTRY(0xe53),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe54), TBL_ENTRY(0xe55), TBL_ENTRY(0xe56),
TBL_ENTRY(0xe57),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe58), TBL_ENTRY(0xe59), TBL_ENTRY(0xe5a),
TBL_ENTRY(0xe5b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe5c), TBL_ENTRY(0xe5d), TBL_ENTRY(0xe5e),
TBL_ENTRY(0xe5f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe60), TBL_ENTRY(0xe61), TBL_ENTRY(0xe62),
TBL_ENTRY(0xe63),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe64), TBL_ENTRY(0xe65), TBL_ENTRY(0xe66),
TBL_ENTRY(0xe67),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe68), TBL_ENTRY(0xe69), TBL_ENTRY(0xe6a),
TBL_ENTRY(0xe6b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe6c), TBL_ENTRY(0xe6d), TBL_ENTRY(0xe6e),
TBL_ENTRY(0xe6f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe70), TBL_ENTRY(0xe71), TBL_ENTRY(0xe72),
TBL_ENTRY(0xe73),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe74), TBL_ENTRY(0xe75), TBL_ENTRY(0xe76),
TBL_ENTRY(0xe77),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe78), TBL_ENTRY(0xe79), TBL_ENTRY(0xe7a),
TBL_ENTRY(0xe7b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe7c), TBL_ENTRY(0xe7d), TBL_ENTRY(0xe7e),
TBL_ENTRY(0xe7f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe80), TBL_ENTRY(0xe81), TBL_ENTRY(0xe82),
TBL_ENTRY(0xe83),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe84), TBL_ENTRY(0xe85), TBL_ENTRY(0xe86),
TBL_ENTRY(0xe87),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe88), TBL_ENTRY(0xe89), TBL_ENTRY(0xe8a),
TBL_ENTRY(0xe8b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe8c), TBL_ENTRY(0xe8d), TBL_ENTRY(0xe8e),
TBL_ENTRY(0xe8f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe90), TBL_ENTRY(0xe91), TBL_ENTRY(0xe92),
TBL_ENTRY(0xe93),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe94), TBL_ENTRY(0xe95), TBL_ENTRY(0xe96),
TBL_ENTRY(0xe97),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe98), TBL_ENTRY(0xe99), TBL_ENTRY(0xe9a),
TBL_ENTRY(0xe9b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xe9c), TBL_ENTRY(0xe9d), TBL_ENTRY(0xe9e),
TBL_ENTRY(0xe9f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xea0), TBL_ENTRY(0xea1), TBL_ENTRY(0xea2),
TBL_ENTRY(0xea3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xea4), TBL_ENTRY(0xea5), TBL_ENTRY(0xea6),
TBL_ENTRY(0xea7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xea8), TBL_ENTRY(0xea9), TBL_ENTRY(0xeaa),
TBL_ENTRY(0xeab),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xeac), TBL_ENTRY(0xead), TBL_ENTRY(0xeae),
TBL_ENTRY(0xeaf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xeb0), TBL_ENTRY(0xeb1), TBL_ENTRY(0xeb2),
TBL_ENTRY(0xeb3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xeb4), TBL_ENTRY(0xeb5), TBL_ENTRY(0xeb6),
TBL_ENTRY(0xeb7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xeb8), TBL_ENTRY(0xeb9), TBL_ENTRY(0xeba),
TBL_ENTRY(0xebb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xebc), TBL_ENTRY(0xebd), TBL_ENTRY(0xebe),
TBL_ENTRY(0xebf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xec0), TBL_ENTRY(0xec1), TBL_ENTRY(0xec2),
TBL_ENTRY(0xec3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xec4), TBL_ENTRY(0xec5), TBL_ENTRY(0xec6),
TBL_ENTRY(0xec7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xec8), TBL_ENTRY(0xec9), TBL_ENTRY(0xeca),
TBL_ENTRY(0xecb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xecc), TBL_ENTRY(0xecd), TBL_ENTRY(0xece),
TBL_ENTRY(0xecf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xed0), TBL_ENTRY(0xed1), TBL_ENTRY(0xed2),
TBL_ENTRY(0xed3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xed4), TBL_ENTRY(0xed5), TBL_ENTRY(0xed6),
TBL_ENTRY(0xed7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xed8), TBL_ENTRY(0xed9), TBL_ENTRY(0xeda),
TBL_ENTRY(0xedb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xedc), TBL_ENTRY(0xedd), TBL_ENTRY(0xede),
TBL_ENTRY(0xedf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xee0), TBL_ENTRY(0xee1), TBL_ENTRY(0xee2),
TBL_ENTRY(0xee3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xee4), TBL_ENTRY(0xee5), TBL_ENTRY(0xee6),
TBL_ENTRY(0xee7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xee8), TBL_ENTRY(0xee9), TBL_ENTRY(0xeea),
TBL_ENTRY(0xeeb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xeec), TBL_ENTRY(0xeed), TBL_ENTRY(0xeee),
TBL_ENTRY(0xeef),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xef0), TBL_ENTRY(0xef1), TBL_ENTRY(0xef2),
TBL_ENTRY(0xef3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xef4), TBL_ENTRY(0xef5), TBL_ENTRY(0xef6),
TBL_ENTRY(0xef7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xef8), TBL_ENTRY(0xef9), TBL_ENTRY(0xefa),
TBL_ENTRY(0xefb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xefc), TBL_ENTRY(0xefd), TBL_ENTRY(0xefe),
TBL_ENTRY(0xeff),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf00), TBL_ENTRY(0xf01), TBL_ENTRY(0xf02),
TBL_ENTRY(0xf03),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf04), TBL_ENTRY(0xf05), TBL_ENTRY(0xf06),
TBL_ENTRY(0xf07),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf08), TBL_ENTRY(0xf09), TBL_ENTRY(0xf0a),
TBL_ENTRY(0xf0b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf0c), TBL_ENTRY(0xf0d), TBL_ENTRY(0xf0e),
TBL_ENTRY(0xf0f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf10), TBL_ENTRY(0xf11), TBL_ENTRY(0xf12),
TBL_ENTRY(0xf13),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf14), TBL_ENTRY(0xf15), TBL_ENTRY(0xf16),
TBL_ENTRY(0xf17),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf18), TBL_ENTRY(0xf19), TBL_ENTRY(0xf1a),
TBL_ENTRY(0xf1b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf1c), TBL_ENTRY(0xf1d), TBL_ENTRY(0xf1e),
TBL_ENTRY(0xf1f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf20), TBL_ENTRY(0xf21), TBL_ENTRY(0xf22),
TBL_ENTRY(0xf23),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf24), TBL_ENTRY(0xf25), TBL_ENTRY(0xf26),
TBL_ENTRY(0xf27),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf28), TBL_ENTRY(0xf29), TBL_ENTRY(0xf2a),
TBL_ENTRY(0xf2b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf2c), TBL_ENTRY(0xf2d), TBL_ENTRY(0xf2e),
TBL_ENTRY(0xf2f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf30), TBL_ENTRY(0xf31), TBL_ENTRY(0xf32),
TBL_ENTRY(0xf33),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf34), TBL_ENTRY(0xf35), TBL_ENTRY(0xf36),
TBL_ENTRY(0xf37),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf38), TBL_ENTRY(0xf39), TBL_ENTRY(0xf3a),
TBL_ENTRY(0xf3b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf3c), TBL_ENTRY(0xf3d), TBL_ENTRY(0xf3e),
TBL_ENTRY(0xf3f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf40), TBL_ENTRY(0xf41), TBL_ENTRY(0xf42),
TBL_ENTRY(0xf43),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf44), TBL_ENTRY(0xf45), TBL_ENTRY(0xf46),
TBL_ENTRY(0xf47),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf48), TBL_ENTRY(0xf49), TBL_ENTRY(0xf4a),
TBL_ENTRY(0xf4b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf4c), TBL_ENTRY(0xf4d), TBL_ENTRY(0xf4e),
TBL_ENTRY(0xf4f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf50), TBL_ENTRY(0xf51), TBL_ENTRY(0xf52),
TBL_ENTRY(0xf53),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf54), TBL_ENTRY(0xf55), TBL_ENTRY(0xf56),
TBL_ENTRY(0xf57),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf58), TBL_ENTRY(0xf59), TBL_ENTRY(0xf5a),
TBL_ENTRY(0xf5b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf5c), TBL_ENTRY(0xf5d), TBL_ENTRY(0xf5e),
TBL_ENTRY(0xf5f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf60), TBL_ENTRY(0xf61), TBL_ENTRY(0xf62),
TBL_ENTRY(0xf63),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf64), TBL_ENTRY(0xf65), TBL_ENTRY(0xf66),
TBL_ENTRY(0xf67),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf68), TBL_ENTRY(0xf69), TBL_ENTRY(0xf6a),
TBL_ENTRY(0xf6b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf6c), TBL_ENTRY(0xf6d), TBL_ENTRY(0xf6e),
TBL_ENTRY(0xf6f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf70), TBL_ENTRY(0xf71), TBL_ENTRY(0xf72),
TBL_ENTRY(0xf73),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf74), TBL_ENTRY(0xf75), TBL_ENTRY(0xf76),
TBL_ENTRY(0xf77),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf78), TBL_ENTRY(0xf79), TBL_ENTRY(0xf7a),
TBL_ENTRY(0xf7b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf7c), TBL_ENTRY(0xf7d), TBL_ENTRY(0xf7e),
TBL_ENTRY(0xf7f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf80), TBL_ENTRY(0xf81), TBL_ENTRY(0xf82),
TBL_ENTRY(0xf83),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf84), TBL_ENTRY(0xf85), TBL_ENTRY(0xf86),
TBL_ENTRY(0xf87),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf88), TBL_ENTRY(0xf89), TBL_ENTRY(0xf8a),
TBL_ENTRY(0xf8b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf8c), TBL_ENTRY(0xf8d), TBL_ENTRY(0xf8e),
TBL_ENTRY(0xf8f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf90), TBL_ENTRY(0xf91), TBL_ENTRY(0xf92),
TBL_ENTRY(0xf93),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf94), TBL_ENTRY(0xf95), TBL_ENTRY(0xf96),
TBL_ENTRY(0xf97),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf98), TBL_ENTRY(0xf99), TBL_ENTRY(0xf9a),
TBL_ENTRY(0xf9b),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xf9c), TBL_ENTRY(0xf9d), TBL_ENTRY(0xf9e),
TBL_ENTRY(0xf9f),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xfa0), TBL_ENTRY(0xfa1), TBL_ENTRY(0xfa2),
TBL_ENTRY(0xfa3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xfa4), TBL_ENTRY(0xfa5), TBL_ENTRY(0xfa6),
TBL_ENTRY(0xfa7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xfa8), TBL_ENTRY(0xfa9), TBL_ENTRY(0xfaa),
TBL_ENTRY(0xfab),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xfac), TBL_ENTRY(0xfad), TBL_ENTRY(0xfae),
TBL_ENTRY(0xfaf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xfb0), TBL_ENTRY(0xfb1), TBL_ENTRY(0xfb2),
TBL_ENTRY(0xfb3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xfb4), TBL_ENTRY(0xfb5), TBL_ENTRY(0xfb6),
TBL_ENTRY(0xfb7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xfb8), TBL_ENTRY(0xfb9), TBL_ENTRY(0xfba),
TBL_ENTRY(0xfbb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xfbc), TBL_ENTRY(0xfbd), TBL_ENTRY(0xfbe),
TBL_ENTRY(0xfbf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xfc0), TBL_ENTRY(0xfc1), TBL_ENTRY(0xfc2),
TBL_ENTRY(0xfc3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xfc4), TBL_ENTRY(0xfc5), TBL_ENTRY(0xfc6),
TBL_ENTRY(0xfc7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xfc8), TBL_ENTRY(0xfc9), TBL_ENTRY(0xfca),
TBL_ENTRY(0xfcb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xfcc), TBL_ENTRY(0xfcd), TBL_ENTRY(0xfce),
TBL_ENTRY(0xfcf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xfd0), TBL_ENTRY(0xfd1), TBL_ENTRY(0xfd2),
TBL_ENTRY(0xfd3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xfd4), TBL_ENTRY(0xfd5), TBL_ENTRY(0xfd6),
TBL_ENTRY(0xfd7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xfd8), TBL_ENTRY(0xfd9), TBL_ENTRY(0xfda),
TBL_ENTRY(0xfdb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xfdc), TBL_ENTRY(0xfdd), TBL_ENTRY(0xfde),
TBL_ENTRY(0xfdf),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xfe0), TBL_ENTRY(0xfe1), TBL_ENTRY(0xfe2),
TBL_ENTRY(0xfe3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xfe4), TBL_ENTRY(0xfe5), TBL_ENTRY(0xfe6),
TBL_ENTRY(0xfe7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xfe8), TBL_ENTRY(0xfe9), TBL_ENTRY(0xfea),
TBL_ENTRY(0xfeb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xfec), TBL_ENTRY(0xfed), TBL_ENTRY(0xfee),
TBL_ENTRY(0xfef),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xff0), TBL_ENTRY(0xff1), TBL_ENTRY(0xff2),
TBL_ENTRY(0xff3),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xff4), TBL_ENTRY(0xff5), TBL_ENTRY(0xff6),
TBL_ENTRY(0xff7),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xff8), TBL_ENTRY(0xff9), TBL_ENTRY(0xffa),
TBL_ENTRY(0xffb),arch/arm/cpu/armv7/uniphier/init_page_table.c new file +1
-0+ TBL_ENTRY(0xffc), TBL_ENTRY(0xffd), TBL_ENTRY(0xffe),
Quoted 1 line
TBL_ENTRY(0xfff), +};
This table seems rather predictable -- the value of each entry seems to be computable from the index alone. Is there a shorter way to define it? I mean, here, it is an initialized non-const, bu we could also make it a un-initialized non-const and fill it through a for-loop, could we not?
Quoted 306 lines
(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/lowlevel_init.Snew file mode 100644 index 0000000..0ea12d3arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +16
-0@@ -0,0 +1,159 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada <[email protected]> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/linkage.h> +#include <asm/system.h> +#include <asm/arch/led.h> +#include <asm/arch/arm-mpcore.h> +#include <asm/arch/sbc-regs.h> + +ENTRY(lowlevel_init) + mov r8, lr @ persevere linkreg across call +
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +3
-0+ /* + * The UniPhier Boot ROM loads SPL code to the L2 cache. + * But CPUs can only do instruction fetch now because
start.Shasarch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +5
-0+ * cleared C and M bits. + * First we need to turn on MMU and Dcache again to get back + * data access to L2. + */ + mrc p15, 0, r0, c1, c0, 0 @ SCTLR(System Contrl Register)
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +1
-0+ orr r0, r0, #(CR_C | CR_M) @ enableMMU and Dcache
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +5
-0+ mcr p15, 0, r0, c1, c0, 0 + + /* + * Now we are using the page table embedded in the Boot ROM. + * It is not handy since it is not a straight mapped tablefor sLD3.
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +1
-0+ * What we need to do next is to switch over to the pagetable in SPL.
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +2
-0+ */ + ldr r3, =init_page_table @ page table must be16KB aligned +
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +2
-0+ /* Disable MMU and Dcache before switching Page Table */ + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (SystemContrl Register)
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +1
-0+ bic r0, r0, #(CR_C | CR_M) @ disable MMU andDcache
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +17
-0+ mcr p15, 0, r0, c1, c0, 0 + + bl enable_mmu + +#ifdef CONFIG_UNIPHIER_SMP + /* + * ACTLR (Auxiliary Control Register) for Cortex-A9 + * bit[9] Parity on + * bit[8] Alloc in one way + * bit[7] EXCL (Exclusive cache bit) + * bit[6] SMP + * bit[3] Write full line of zeros mode + * bit[2] L1 Prefetch enable + * bit[1] L2 prefetch enable + * bit[0] FW (Cache and TLB maintenance broadcast) + */ + mrc p15, 0, r0, c1, c0, 1 @ ACTLR (AuxiliaryControl Register)
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +5
-0+ orr r0, r0, #0x41 @ enable SMP, FW bit + mcr p15, 0, r0, c1, c0, 1 + + /* branch by CPU ID */ + mrc p15, 0, r0, c0, c0, 5 @ MPIDR(Multiprocessor Affinity Register)
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +11
-0+ and r0, r0, #0x3 + cmp r0, #0x0 + beq primary_cpu + ldr r1, =ROM_BOOT_ROMRSV2 + mov r0, #0 + str r0, [r1] +0: wfe + ldr r0, [r1] + cmp r0, #0 + beq 0b + bx r0 @ r0: entry point ofU-Boot main for the secondary CPU +primary_cpu:
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +2
-0+ ldr r1, =ROM_BOOT_ROMRSV2 + ldr r0, =_start @ entry for thesecondary CPU
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +2
-0+ str r0, [r1] + ldr r0, [r1] @ make sure str iscomplete before sev
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +2
-0+ sev @ kick the sedoncary CPU + mrc p15, 4, r1, c15, c0, 0 @ ConfigurationBase Address Register
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +3
-0+ bfc r1, #0, #13 @ clear bit 12-0 + mov r0, #-1 + str r0, [r1, #SCU_INV_ALL] @ SCU InvalidateAll Register
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +5
-0+ mov r0, #1 @ SCU enable + str r0, [r1, #SCU_CTRL] @ SCU Control Register +#endif + + bl setup_init_ram @ RAM area fortemporary stack pointer +
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +6
-0+ mov lr, r8 @ restore link + mov pc, lr @ back to my caller +ENDPROC(lowlevel_init) + +ENTRY(enable_mmu) + mrc p15, 0, r0, c2, c0, 2 @ TTBCR (TranslationTable Base Control Register)
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +5
-0+ bic r0, r0, #0x37 + orr r0, r0, #0x20 @ disable TTBR1 + mcr p15, 0, r0, c2, c0, 2 + + orr r0, r3, #0x8 @ Outer Cacheabilityfor table walks: WBWA
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +6
-0+ mcr p15, 0, r0, c2, c0, 0 @ TTBR0 + + mov r0, #0 + mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs + + mov r0, #-1 @ manager for alldomains (No permission check)
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +1
-0+ mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain AccessControl Register) +
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +8
-0+ dsb + isb + /* + * MMU on: + * TLBs was already invalidated in "../start.S" + * So, we don't need to invalidate it here. + */ + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (SystemContrl Register)
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +1
-0+ orr r0, r0, #(CR_C | CR_M) @ MMU and Dcacheenable
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +19
-0+ mcr p15, 0, r0, c1, c0, 0 + + mov pc, lr +ENDPROC(enable_mmu) + +#include <asm/arch/ssc-regs.h> + +#define BOOT_RAM_SIZE (SSC_WAY_SIZE) +#define BOOT_WAY_BITS (0x00000100) /* way 8 */ + +ENTRY(setup_init_ram) + /* + * Touch to zero for the boot way + */ +0: + /* + * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order + */ + ldr r0, = 0x00408006 @ touch to zero withaddress range
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +3
-0+ ldr r1, = SSCOQM + str r0, [r1] + ldr r0, = (CONFIG_SYS_INIT_SP_ADDR -
BOOT_RAM_SIZE) @ base addressarch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +11
-0+ ldr r1, = SSCOQAD + str r0, [r1] + ldr r0, = BOOT_RAM_SIZE + ldr r1, = SSCOQSZ + str r0, [r1] + ldr r0, = BOOT_WAY_BITS + ldr r1, = SSCOQWN + str r0, [r1] + ldr r1, = SSCOPPQSEF + ldr r0, [r1] + cmp r0, #0 @ check if thecommand is successfully set
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +1
-0+ bne 0b @ try again if an erroroccurres +
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +5
-0+ ldr r1, = SSCOLPQS +1: + ldr r0, [r1] + cmp r0, #0x4 + bne 1b @ wait until theoperation is completed
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +1
-0+ str r0, [r1] @ clear the completenotification flag +
arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file +2
-0+ mov pc, lr +ENDPROC(setup_init_ram)(quoted diff) +0
-0b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile new file mode 100644 index 0000000..b385e19
arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile new file +8
-0@@ -0,0 +1,10 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o +obj-y += boot-mode.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ + sbc_init.o sg_init.o pll_init.o clkrst_init.opinctrl.o +obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile new file +1
-0+ umc_init.o(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.cnew file mode 100644 index 0000000..85f37f2arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c new file +12
-0@@ -0,0 +1,33 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/bcu-regs.h> + +#define ch (x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 <<(x)) +
arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c new file +5
-0+void bcu_init (void ) +{ +int shift; + +writel (0x44444444 ,BCSCR0 );/* 0x20000000-0x3fffffff: ASM bus */
arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c new file +1
-0+writel (0x11111111 ,BCSCR2 );/* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c new file +1
-0+writel (0x11111111 ,BCSCR3 );/* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c new file +1
-0+writel (0x11111111 ,BCSCR4 );/* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c new file +1
-0+writel (0x11111111 ,BCSCR5 );/* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */ +
arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c new file +2
-0+/* Specify DDR channel */ + shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) /
0x04000000* 4;arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c new file +8
-0+writel (ch (shift),BCIPPCCHR2 );/* 0x80000000-0x9fffffff */ + + shift -=32 ; +writel (ch (shift),BCIPPCCHR3 );/* 0xa0000000-0xbfffffff */ + + shift -=32 ; +writel (ch (shift),BCIPPCCHR4 );/* 0xc0000000-0xdfffffff */ +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.cnew file mode 100644 index 0000000..27d772earch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c new file +16
-0@@ -0,0 +1,16 @@ +/* +* Copyright (C) 2012-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/arch/board.h> + +int checkboard (void ) +{ +puts ("Board: PH1-LD4 Board\n" ); + +return check_support_card (); +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.cnew file mode 100644 index 0000000..92972e1arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c new file +31
-0@@ -0,0 +1,42 @@ +/* +* Copyright (C) 2012-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/arch/led.h> +#include <asm/arch/board.h> + +void bcu_init (void ); +void sbc_init (void ); +void sg_init (void ); +void pll_init (void ); +void pin_init (void ); +void clkrst_init (void ); + +int board_postclk_init (void ) +{ +bcu_init (); + +sbc_init (); + +sg_init (); + +pll_init (); + +uniphier_board_init (); + + led_write(B, 1, , );
arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c line 41
Quoted 10 lines
arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c new file +10
-0+ +pin_init (); + + led_write(B, 2, , ); + +clkrst_init (); + + led_write(B, 3, , ); + +return 0 ;
Can you remove the blank lines? Ditto in other places where double spacing occurs.
Quoted 2,549 lines
arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c new file +1
-0+}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.cnew file mode 100644 index 0000000..d359b56arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c new file +1
-0@@ -0,0 +1 @@ +#include "../ph1-pro4/boot-mode.c" (quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.cnew file mode 100644 index 0000000..18965a9arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c new file +25
-0@@ -0,0 +1,29 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sc-regs.h> + +void clkrst_init (void ) +{ +u32 tmp; + +/* deassert reset */ + tmp =readl (SC_RSTCTRL ); + tmp |=SC_RSTCTRL_NRST_ETHER |SC_RSTCTRL_NRST_UMC1 + |SC_RSTCTRL_NRST_UMC0 |SC_RSTCTRL_NRST_NAND ; +writel (tmp,SC_RSTCTRL ); +readl (SC_RSTCTRL );/* dummy read */ + +/* privide clocks */ + tmp =readl (SC_CLKCTRL ); + tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO |
SC_CLKCTRL_CLK_UMCarch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c new file +1
-0+ | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC |
SC_CLKCTRL_CLK_PERI;arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c new file +3
-0+writel (tmp,SC_CLKCTRL ); +readl (SC_CLKCTRL );/* dummy read */ +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.cnew file mode 100644 index 0000000..a742940arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c new file +63
-0@@ -0,0 +1,63 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sg-regs.h> + +void pin_init (void ) +{ +u32 tmp; + +/* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL +sg_set_pinsel (85 ,1 );/* HSDOUT3 -> RXD0 */ +sg_set_pinsel (88 ,1 );/* HDDOUT6 -> TXD0 */ + +sg_set_pinsel (69 ,23 );/* PCIOWR -> TXD1 */ +sg_set_pinsel (70 ,23 );/* PCIORD -> RXD1 */ + +sg_set_pinsel (128 ,13 );/* XIRQ6 -> TXD2 */ +sg_set_pinsel (129 ,13 );/* XIRQ7 -> RXD2 */ + +sg_set_pinsel (110 ,1 );/* SBO0 -> TXD3 */ +sg_set_pinsel (111 ,1 );/* SBI0 -> RXD3 */ +#endif + +#ifdef CONFIG_NAND_DENALI +sg_set_pinsel (158 ,0 );/* XNFRE -> XNFRE_GB */ +sg_set_pinsel (159 ,0 );/* XNFWE -> XNFWE_GB */ +sg_set_pinsel (160 ,0 );/* XFALE -> NFALE_GB */ +sg_set_pinsel (161 ,0 );/* XFCLE -> NFCLE_GB */ +sg_set_pinsel (162 ,0 );/* XNFWP -> XFNWP_GB */ +sg_set_pinsel (163 ,0 );/* XNFCE0 -> XNFCE0_GB */ +sg_set_pinsel (164 ,0 );/* NANDRYBY0 -> NANDRYBY0_GB */ +sg_set_pinsel (22 ,0 );/* MMCCLK -> XFNCE1_GB */ +sg_set_pinsel (23 ,0 );/* MMCCMD -> NANDRYBY1_GB */ +sg_set_pinsel (24 ,0 );/* MMCDAT0 -> NFD0_GB */ +sg_set_pinsel (25 ,0 );/* MMCDAT1 -> NFD1_GB */ +sg_set_pinsel (26 ,0 );/* MMCDAT2 -> NFD2_GB */ +sg_set_pinsel (27 ,0 );/* MMCDAT3 -> NFD3_GB */ +sg_set_pinsel (28 ,0 );/* MMCDAT4 -> NFD4_GB */ +sg_set_pinsel (29 ,0 );/* MMCDAT5 -> NFD5_GB */ +sg_set_pinsel (30 ,0 );/* MMCDAT6 -> NFD6_GB */ +sg_set_pinsel (31 ,0 );/* MMCDAT7 -> NFD7_GB */ +#endif + +#ifdef CONFIG_USB_EHCI_UNIPHIER +sg_set_pinsel (53 ,0 );/* USB0VBUS -> USB0VBUS */ +sg_set_pinsel (54 ,0 );/* USB0OD -> USB0OD */ +sg_set_pinsel (55 ,0 );/* USB1VBUS -> USB1VBUS */ +sg_set_pinsel (56 ,0 );/* USB1OD -> USB1OD */ +/* sg_set_pinsel(67, 23); */ /* PCOE -> USB2VBUS */ +/* sg_set_pinsel(68, 23); */ /* PCWAIT -> USB2OD */ +#endif + + tmp =readl (SG_IECTRL ); + tmp |=0x41 ; +writel (tmp,SG_IECTRL ); +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.cnew file mode 100644 index 0000000..68b9d5farch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c new file +53
-0@@ -0,0 +1,189 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sc-regs.h> +#include <asm/arch/sg-regs.h> + +#undef DPLL_SSC_RATE_1PER + +void dpll_init (void ) +{ +u32 tmp; + +/* +* Set Frequency +* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) +* to FOUT (DPLLCTRL.bit[29:20]) +*/ + tmp =readl (SC_DPLLCTRL ); + tmp &= ~0x000f0000 ; +#if CONFIG_DDR_FREQ ==1600 + tmp |=0x000c0000 ; +#elif CONFIG_DDR_FREQ ==1333 + tmp |=0x000d0000 ; +#else +# error "Unknown frequency" +#endif + +#if defined(DPLL_SSC_RATE_1PER ) + tmp &= ~SC_DPLLCTRL_SSC_RATE ; +#else + tmp |=SC_DPLLCTRL_SSC_RATE ; +#endif +writel (tmp,SC_DPLLCTRL ); + + tmp =readl (SC_DPLLCTRL2 ); + tmp |=SC_DPLLCTRL2_NRSTDS ; +writel (tmp,SC_DPLLCTRL2 ); +} + +void upll_init (void ) +{ +u32 tmp, clk_mode_upll, clk_mode_axosel; + + tmp =readl (SG_PINMON0 ); + clk_mode_upll = tmp &SG_PINMON0_CLK_MODE_UPLLSRC_MASK ; + clk_mode_axosel = tmp &SG_PINMON0_CLK_MODE_AXOSEL_MASK ; + +/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c new file +6
-0+ tmp =readl (SC_UPLLCTRL ); + tmp &= ~0x18000000 ; +writel (tmp,SC_UPLLCTRL ); + +if (clk_mode_upll ==SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT ) { + if (clk_mode_axosel ==
SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U||arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c new file +1
-0+ clk_mode_axosel ==
SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c new file +66
-0+/* AXO: 25MHz */ + tmp &= ~0x07ffffff ; + tmp |=0x0228f5c0 ; + }else { +/* AXO: default 24.576MHz */ + tmp &= ~0x07ffffff ; + tmp |=0x02328000 ; + } + } + +writel (tmp,SC_UPLLCTRL ); + +/* set 1 to K_LD(UPLLCTRL.bit[27]) */ + tmp |=0x08000000 ; +writel (tmp,SC_UPLLCTRL ); + +/* wait 10 usec */ +udelay (10 ); + +/* set 1 to SNRT(UPLLCTRL.bit[28]) */ + tmp |=0x10000000 ; +writel (tmp,SC_UPLLCTRL ); +} + +void vpll_init (void ) +{ +u32 tmp, clk_mode_axosel; + + tmp =readl (SG_PINMON0 ); + clk_mode_axosel = tmp &SG_PINMON0_CLK_MODE_AXOSEL_MASK ; + +/* set 1 to VPLA27WP and VPLA27WP */ + tmp =readl (SC_VPLL27ACTRL ); + tmp |=0x00000001 ; +writel (tmp,SC_VPLL27ACTRL ); + tmp =readl (SC_VPLL27BCTRL ); + tmp |=0x00000001 ; +writel (tmp,SC_VPLL27BCTRL ); + +/* Set 0 to VPLA_K_LD and VPLB_K_LD */ + tmp =readl (SC_VPLL27ACTRL3 ); + tmp &= ~0x10000000 ; +writel (tmp,SC_VPLL27ACTRL3 ); + tmp =readl (SC_VPLL27BCTRL3 ); + tmp &= ~0x10000000 ; +writel (tmp,SC_VPLL27BCTRL3 ); + +/* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp =readl (SC_VPLL27ACTRL2 ); + tmp &= ~0x10000000 ; +writel (tmp,SC_VPLL27ACTRL2 ); + tmp =readl (SC_VPLL27BCTRL2 ); + tmp &= ~0x10000000 ; +writel (tmp,SC_VPLL27BCTRL2 ); + +/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ + tmp =readl (SC_VPLL27ACTRL2 ); + tmp &= ~0x0000007f ; + tmp |=0x00000020 ; +writel (tmp,SC_VPLL27ACTRL2 ); + tmp =readl (SC_VPLL27BCTRL2 ); + tmp &= ~0x0000007f ; + tmp |=0x00000020 ; +writel (tmp,SC_VPLL27BCTRL2 ); + + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U||
arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c new file +1
-0+ clk_mode_axosel ==
SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c new file +62
-0+/* AXO: 25MHz */ + tmp =readl (SC_VPLL27ACTRL3 ); + tmp &= ~0x000fffff ; + tmp |=0x00066664 ; +writel (tmp,SC_VPLL27ACTRL3 ); + tmp =readl (SC_VPLL27BCTRL3 ); + tmp &= ~0x000fffff ; + tmp |=0x00066664 ; +writel (tmp,SC_VPLL27BCTRL3 ); + }else { +/* AXO: default 24.576MHz */ + tmp =readl (SC_VPLL27ACTRL3 ); + tmp &= ~0x000fffff ; + tmp |=0x000f5800 ; +writel (tmp,SC_VPLL27ACTRL3 ); + tmp =readl (SC_VPLL27BCTRL3 ); + tmp &= ~0x000fffff ; + tmp |=0x000f5800 ; +writel (tmp,SC_VPLL27BCTRL3 ); + } + +/* Set 1 to VPLA_K_LD and VPLB_K_LD */ + tmp =readl (SC_VPLL27ACTRL3 ); + tmp |=0x10000000 ; +writel (tmp,SC_VPLL27ACTRL3 ); + tmp =readl (SC_VPLL27BCTRL3 ); + tmp |=0x10000000 ; +writel (tmp,SC_VPLL27BCTRL3 ); + +/* wait 10 usec */ +udelay (10 ); + +/* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp =readl (SC_VPLL27ACTRL2 ); + tmp |=0x10000000 ; +writel (tmp,SC_VPLL27ACTRL2 ); + tmp =readl (SC_VPLL27BCTRL2 ); + tmp |=0x10000000 ; +writel (tmp,SC_VPLL27BCTRL2 ); + +/* set 0 to VPLA27WP and VPLA27WP */ + tmp =readl (SC_VPLL27ACTRL ); + tmp &= ~0x00000001 ; +writel (tmp,SC_VPLL27ACTRL ); + tmp =readl (SC_VPLL27BCTRL ); + tmp |= ~0x00000001 ; +writel (tmp,SC_VPLL27BCTRL ); +} + +void pll_init (void ) +{ +dpll_init (); +upll_init (); +vpll_init (); + +/* +* Wait 500 usec until dpll get stable +* We wait 10 usec in upll_init() and vpll_init() +* so 20 usec can be saved here. +*/ +udelay (480 ); +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.cnew file mode 100644 index 0000000..837b2a8arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c new file +1
-0@@ -0,0 +1 @@ +#include "../ph1-pro4/pll_spectrum.c" (quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.cnew file mode 100644 index 0000000..a37ed16arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c new file +44
-0@@ -0,0 +1,44 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sbc-regs.h> +#include <asm/arch/sg-regs.h> + +void sbc_init (void ) +{ +/* XECS1: sub/boot memory (boot swap = off/on) */ +writel (SBCTRL0_SAVEPIN_MEM_VALUE ,SBCTRL10 ); +writel (SBCTRL1_SAVEPIN_MEM_VALUE ,SBCTRL11 ); +writel (SBCTRL2_SAVEPIN_MEM_VALUE ,SBCTRL12 ); +writel (SBCTRL4_SAVEPIN_MEM_VALUE ,SBCTRL14 ); + +#if !defined(CONFIG_SPL_BUILD ) +/* XECS0: boot/sub memory (boot swap = off/on) */ +writel (SBCTRL0_SAVEPIN_MEM_VALUE ,SBCTRL00 ); +writel (SBCTRL1_SAVEPIN_MEM_VALUE ,SBCTRL01 ); +writel (SBCTRL2_SAVEPIN_MEM_VALUE ,SBCTRL02 ); +writel (SBCTRL4_SAVEPIN_MEM_VALUE ,SBCTRL04 ); +#endif +/* XECS3: peripherals */ +writel (SBCTRL0_SAVEPIN_PERI_VALUE ,SBCTRL30 ); +writel (SBCTRL1_SAVEPIN_PERI_VALUE ,SBCTRL31 ); +writel (SBCTRL2_SAVEPIN_PERI_VALUE ,SBCTRL32 ); +writel (SBCTRL4_SAVEPIN_PERI_VALUE ,SBCTRL34 ); + +/* base address regsiters */ +writel (0x0000bc01 ,SBBASE0 ); +writel (0x0400bc01 ,SBBASE1 ); +writel (0x0800bf01 ,SBBASE3 ); + +#if !defined(CONFIG_SPL_BUILD ) +/* enable access to sub memory when boot swap is on */ +sg_set_pinsel (155 ,1 );/* PORT24 -> XECS0 */ +#endif +sg_set_pinsel (156 ,1 );/* PORT25 -> XECS3 */ +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.cnew file mode 100644 index 0000000..8200959arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c new file +17
-0@@ -0,0 +1,28 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sg-regs.h> + +void sg_init (void ) +{ +u32 tmp; + +/* Set DDR size */ + tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE,
CONFIG_DDR_NUM_CH0);arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c new file +1
-0+ tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE,
CONFIG_DDR_NUM_CH1); +#ifCONFIG_SDRAM0_BASE+CONFIG_SDRAM0_SIZE<CONFIG_SDRAM1_BASEarch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c new file +5
-0+ tmp |=SG_MEMCONF_SPARSEMEM ; +#endif +writel (tmp,SG_MEMCONF ); + +/* Must enable in-port before deasserting reset signals of cores */
arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c new file +4
-0+ tmp =readl (SG_IECTRL ); + tmp |=0x1 ; +writel (tmp,SG_IECTRL ); +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.cnew file mode 100644 index 0000000..e0e586barch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c new file +10
-0@@ -0,0 +1,10 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +int umc_init (void ) +{ +return 0 ; +}(quoted diff) +0
-0b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile new file mode 100644 index 0000000..712afd1
arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile new file +8
-0@@ -0,0 +1,10 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o +obj-y += boot-mode.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \ + sg_init.o pll_init.o clkrst_init.opinctrl.o +obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile new file +1
-0+ umc_init.o(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.cnew file mode 100644 index 0000000..325a4f6arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c new file +16
-0@@ -0,0 +1,16 @@ +/* +* Copyright (C) 2012-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/arch/board.h> + +int checkboard (void ) +{ +puts ("Board: PH1-Pro4 Board\n" ); + +return check_support_card (); +}diff --git
a/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.cb/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.cnew file mode 100644 index 0000000..e261513 ---/dev/null
+++b/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.carch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c new file +39
-0@@ -0,0 +1,39 @@ +/* +* Copyright (C) 2012-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/arch/led.h> +#include <asm/arch/board.h> + +void sbc_init (void ); +void sg_init (void ); +void pll_init (void ); +void pin_init (void ); +void clkrst_init (void ); + +int board_postclk_init (void ) +{ +sbc_init (); + +sg_init (); + +pll_init (); + +uniphier_board_init (); + + led_write(B, 1, , ); + +pin_init (); + + led_write(B, 2, , ); + +clkrst_init (); + + led_write(B, 3, , ); + +return 0 ; +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.cnew file mode 100644 index 0000000..33bccffarch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +16
-0@@ -0,0 +1,66 @@ +/* +* Copyright (C) 2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <spl.h> +#include <asm/io.h> +#include <asm/arch/boot-device.h> +#include <asm/arch/sg-regs.h> +#include <asm/arch/sbc-regs.h> + +struct boot_device_info boot_device_table[] = { + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB,Addr 4)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI,Addr 4)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +1
-0+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI,Addr 5)"},
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file +27
-0+ {BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"}, + {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, ""} +}; + +u32 get_boot_mode_sel (void ) +{ +return (readl (SG_PINMON0 ) >>1 ) &0x1f ; +} + +u32 spl_boot_device (void ) +{ +u32 boot_mode; + +if (boot_is_swapped ()) +return BOOT_DEVICE_NOR ; + + boot_mode =get_boot_mode_sel (); + +return boot_device_table[boot_mode].type; +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.cnew file mode 100644 index 0000000..18965a9arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c new file +25
-0@@ -0,0 +1,29 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sc-regs.h> + +void clkrst_init (void ) +{ +u32 tmp; + +/* deassert reset */ + tmp =readl (SC_RSTCTRL ); + tmp |=SC_RSTCTRL_NRST_ETHER |SC_RSTCTRL_NRST_UMC1 + |SC_RSTCTRL_NRST_UMC0 |SC_RSTCTRL_NRST_NAND ; +writel (tmp,SC_RSTCTRL ); +readl (SC_RSTCTRL );/* dummy read */ + +/* privide clocks */ + tmp =readl (SC_CLKCTRL ); + tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO |
SC_CLKCTRL_CLK_UMCarch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c new file +1
-0+ | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC |
SC_CLKCTRL_CLK_PERI;arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c new file +3
-0+writel (tmp,SC_CLKCTRL ); +readl (SC_CLKCTRL );/* dummy read */ +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.cnew file mode 100644 index 0000000..503c247arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c new file +45
-0@@ -0,0 +1,45 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sg-regs.h> + +void pin_init (void ) +{ +/* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL +sg_set_pinsel (127 ,0 );/* RXD0 -> RXD0 */ +sg_set_pinsel (128 ,0 );/* TXD0 -> TXD0 */ +sg_set_pinsel (129 ,0 );/* RXD1 -> RXD1 */ +sg_set_pinsel (130 ,0 );/* TXD1 -> TXD1 */ +sg_set_pinsel (131 ,0 );/* RXD2 -> RXD2 */ +sg_set_pinsel (132 ,0 );/* TXD2 -> TXD2 */ +sg_set_pinsel (88 ,2 );/* CH6CLK -> RXD3 */ +sg_set_pinsel (89 ,2 );/* CH6VAL -> TXD3 */ +#endif + +#ifdef CONFIG_NAND_DENALI +sg_set_pinsel (40 ,0 );/* NFD0 -> NFD0 */ +sg_set_pinsel (41 ,0 );/* NFD1 -> NFD1 */ +sg_set_pinsel (42 ,0 );/* NFD2 -> NFD2 */ +sg_set_pinsel (43 ,0 );/* NFD3 -> NFD3 */ +sg_set_pinsel (44 ,0 );/* NFD4 -> NFD4 */ +sg_set_pinsel (45 ,0 );/* NFD5 -> NFD5 */ +sg_set_pinsel (46 ,0 );/* NFD6 -> NFD6 */ +sg_set_pinsel (47 ,0 );/* NFD7 -> NFD7 */ +sg_set_pinsel (48 ,0 );/* NFALE -> NFALE */ +sg_set_pinsel (49 ,0 );/* NFCLE -> NFCLE */ +sg_set_pinsel (50 ,0 );/* XNFRE -> XNFRE */ +sg_set_pinsel (51 ,0 );/* XNFWE -> XNFWE */ +sg_set_pinsel (52 ,0 );/* XNFWP -> XNFWP */ +sg_set_pinsel (53 ,0 );/* XNFCE0 -> XNFCE0 */ +sg_set_pinsel (54 ,0 );/* NRYBY0 -> NRYBY0 */ +#endif + +writel (1 ,SG_LOADPINCTRL ); +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.cnew file mode 100644 index 0000000..fd08438arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c new file +74
-0@@ -0,0 +1,168 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sc-regs.h> +#include <asm/arch/sg-regs.h> + +#undef DPLL_SSC_RATE_1PER + +void dpll_init (void ) +{ +u32 tmp; + +/* +* Set Frequency +* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) +* to FOUT ( DPLLCTRL.bit[29:20] ) +*/ + tmp =readl (SC_DPLLCTRL ); + tmp &= ~(0x000f0000 ); +#if CONFIG_DDR_FREQ ==1600 + tmp |=0x000c0000 ; +#elif CONFIG_DDR_FREQ ==1333 + tmp |=0x000d0000 ; +#else +# error "Unsupported frequency" +#endif + +/* +* Set Moduration rate +* Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15]) +*/ +#if defined(DPLL_SSC_RATE_1PER ) + tmp &= ~0x00008000 ; +#else + tmp |=0x00008000 ; +#endif +writel (tmp,SC_DPLLCTRL ); + + tmp =readl (SC_DPLLCTRL2 ); + tmp |=SC_DPLLCTRL2_NRSTDS ; +writel (tmp,SC_DPLLCTRL2 ); +} + +void stop_mpll (void ) +{ +u32 tmp; + + tmp =readl (SC_MPLLOSCCTL ); + +if (!(tmp &SC_MPLLOSCCTL_MPLLST )) +return ;/* already stopped */ + + tmp &= ~SC_MPLLOSCCTL_MPLLEN ; +writel (tmp,SC_MPLLOSCCTL ); + +while (readl (SC_MPLLOSCCTL ) &SC_MPLLOSCCTL_MPLLST ) + ; +} + +void vpll_init (void ) +{ +u32 tmp, clk_mode_axosel; + +/* Set VPLL27A & VPLL27B */ + tmp =readl (SG_PINMON0 ); + clk_mode_axosel = tmp &SG_PINMON0_CLK_MODE_AXOSEL_MASK ; + +#if defined(CONFIG_PH1_PRO4 ) +/* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c new file +6
-0+if (clk_mode_axosel ==SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ || + clk_mode_axosel ==SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ ) +return ; +#endif + +/* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c new file +68
-0+ tmp =readl (SC_VPLL27ACTRL ); + tmp |=0x00000001 ; +writel (tmp,SC_VPLL27ACTRL ); + tmp =readl (SC_VPLL27BCTRL ); + tmp |=0x00000001 ; +writel (tmp,SC_VPLL27BCTRL ); + +/* Unset VPLA_K_LD and VPLB_K_LD bit */ + tmp =readl (SC_VPLL27ACTRL3 ); + tmp &= ~0x10000000 ; +writel (tmp,SC_VPLL27ACTRL3 ); + tmp =readl (SC_VPLL27BCTRL3 ); + tmp &= ~0x10000000 ; +writel (tmp,SC_VPLL27BCTRL3 ); + +/* Set VPLA_M and VPLB_M to 0x20 */ + tmp =readl (SC_VPLL27ACTRL2 ); + tmp &= ~0x0000007f ; + tmp |=0x00000020 ; +writel (tmp,SC_VPLL27ACTRL2 ); + tmp =readl (SC_VPLL27BCTRL2 ); + tmp &= ~0x0000007f ; + tmp |=0x00000020 ; +writel (tmp,SC_VPLL27BCTRL2 ); + +if (clk_mode_axosel ==SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ || + clk_mode_axosel ==SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ ) { +/* Set VPLA_K and VPLB_K for AXO: 25MHz */ + tmp =readl (SC_VPLL27ACTRL3 ); + tmp &= ~0x000fffff ; + tmp |=0x00066666 ; +writel (tmp,SC_VPLL27ACTRL3 ); + tmp =readl (SC_VPLL27BCTRL3 ); + tmp &= ~0x000fffff ; + tmp |=0x00066666 ; +writel (tmp,SC_VPLL27BCTRL3 ); + }else { +/* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */ + tmp =readl (SC_VPLL27ACTRL3 ); + tmp &= ~0x000fffff ; + tmp |=0x000f5800 ; +writel (tmp,SC_VPLL27ACTRL3 ); + tmp =readl (SC_VPLL27BCTRL3 ); + tmp &= ~0x000fffff ; + tmp |=0x000f5800 ; +writel (tmp,SC_VPLL27BCTRL3 ); + } + +/* wait 1 usec */ +udelay (1 ); + +/* Set VPLA_K_LD and VPLB_K_LD to load K parameters */ + tmp =readl (SC_VPLL27ACTRL3 ); + tmp |=0x10000000 ; +writel (tmp,SC_VPLL27ACTRL3 ); + tmp =readl (SC_VPLL27BCTRL3 ); + tmp |=0x10000000 ; +writel (tmp,SC_VPLL27BCTRL3 ); + +/* Unset VPLA_SNRST and VPLB_SNRST bit */ + tmp =readl (SC_VPLL27ACTRL2 ); + tmp |=0x10000000 ; +writel (tmp,SC_VPLL27ACTRL2 ); + tmp =readl (SC_VPLL27BCTRL2 ); + tmp |=0x10000000 ; +writel (tmp,SC_VPLL27BCTRL2 ); + +/* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c new file +20
-0+ tmp =readl (SC_VPLL27ACTRL ); + tmp &= ~0x00000001 ; +writel (tmp,SC_VPLL27ACTRL ); + tmp =readl (SC_VPLL27BCTRL ); + tmp &= ~0x00000001 ; +writel (tmp,SC_VPLL27BCTRL ); +} + +void pll_init (void ) +{ +dpll_init (); +stop_mpll (); +vpll_init (); + +/* +* Wait 500 usec until dpll get stable +* We wait 1 usec in vpll_init() so 1 usec can be saved here. +*/ +udelay (499 ); +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.cnew file mode 100644 index 0000000..4538d1aarch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c new file +18
-0@@ -0,0 +1,18 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sc-regs.h> + +void enable_dpll_ssc (void ) +{ +u32 tmp; + + tmp =readl (SC_DPLLCTRL ); + tmp |=SC_DPLLCTRL_SSC_EN ; +writel (tmp,SC_DPLLCTRL ); +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.cnew file mode 100644 index 0000000..f113db5arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c new file +37
-0@@ -0,0 +1,75 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sbc-regs.h> +#include <asm/arch/sg-regs.h> + +void sbc_init (void ) +{ +#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD ) +/* +* Only CS1 is connected to support card. +* BKSZ[1:0] should be set to "01". +*/ +writel (SBCTRL0_SAVEPIN_PERI_VALUE ,SBCTRL10 ); +writel (SBCTRL1_SAVEPIN_PERI_VALUE ,SBCTRL11 ); +writel (SBCTRL2_SAVEPIN_PERI_VALUE ,SBCTRL12 ); +writel (SBCTRL4_SAVEPIN_PERI_VALUE ,SBCTRL14 ); + +if (readl (SBBASE0 ) &0x1 ) { +/* +* Boot Swap Off: boot from mask ROM +* 0x00000000-0x01ffffff: mask ROM +* 0x02000000-0x3effffff: memory bank (31MB) +* 0x03f00000-0x3fffffff: peripherals (1MB) +*/ +writel (0x0000be01 ,SBBASE0 );/* dummy */ +writel (0x0200be01 ,SBBASE1 ); + }else { +/* +* Boot Swap On: boot from external NOR/SRAM +* 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c new file +2
-0+* +* 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c new file +1
-0+* 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c new file +35
-0+*/ +writel (0x0000bc01 ,SBBASE0 ); + } +#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD ) +#if !defined(CONFIG_SPL_BUILD ) +/* XECS0: boot/sub memory (boot swap = off/on) */ +writel (SBCTRL0_SAVEPIN_MEM_VALUE ,SBCTRL00 ); +writel (SBCTRL1_SAVEPIN_MEM_VALUE ,SBCTRL01 ); +writel (SBCTRL2_SAVEPIN_MEM_VALUE ,SBCTRL02 ); +writel (SBCTRL4_SAVEPIN_MEM_VALUE ,SBCTRL04 ); +#endif +/* XECS1: sub/boot memory (boot swap = off/on) */ +writel (SBCTRL0_SAVEPIN_MEM_VALUE ,SBCTRL10 ); +writel (SBCTRL1_SAVEPIN_MEM_VALUE ,SBCTRL11 ); +writel (SBCTRL2_SAVEPIN_MEM_VALUE ,SBCTRL12 ); +writel (SBCTRL4_SAVEPIN_MEM_VALUE ,SBCTRL14 ); + +/* XECS3: peripherals */ +writel (SBCTRL0_SAVEPIN_PERI_VALUE ,SBCTRL30 ); +writel (SBCTRL1_SAVEPIN_PERI_VALUE ,SBCTRL31 ); +writel (SBCTRL2_SAVEPIN_PERI_VALUE ,SBCTRL32 ); +writel (SBCTRL4_SAVEPIN_PERI_VALUE ,SBCTRL34 ); + +writel (0x0000bc01 ,SBBASE0 );/* boot memory */ +writel (0x0400bc01 ,SBBASE1 );/* sub memory */ +writel (0x0800bf01 ,SBBASE3 );/* peripherals */ + +#if !defined(CONFIG_SPL_BUILD ) +sg_set_pinsel (318 ,5 );/* PORT22 -> XECS0 */ +#endif +sg_set_pinsel (313 ,5 );/* PORT15 -> XECS3 */ +writel (0x00000001 ,SG_LOADPINCTRL ); + +#endif /* CONFIG_XXX_MICRO_SUPPORT_CARD */ +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.cnew file mode 100644 index 0000000..8200959arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c new file +17
-0@@ -0,0 +1,28 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sg-regs.h> + +void sg_init (void ) +{ +u32 tmp; + +/* Set DDR size */ + tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE,
CONFIG_DDR_NUM_CH0);arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c new file +1
-0+ tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE,
CONFIG_DDR_NUM_CH1); +#ifCONFIG_SDRAM0_BASE+CONFIG_SDRAM0_SIZE<CONFIG_SDRAM1_BASEarch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c new file +5
-0+ tmp |=SG_MEMCONF_SPARSEMEM ; +#endif +writel (tmp,SG_MEMCONF ); + +/* Must enable in-port before deasserting reset signals of cores */
arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c new file +4
-0+ tmp =readl (SG_IECTRL ); + tmp |=0x1 ; +writel (tmp,SG_IECTRL ); +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.cnew file mode 100644 index 0000000..e0e586barch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c new file +10
-0@@ -0,0 +1,10 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +int umc_init (void ) +{ +return 0 ; +}(quoted diff) +0
-0b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile new file mode 100644 index 0000000..b385e19
arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile new file +8
-0@@ -0,0 +1,10 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o +obj-y += boot-mode.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ + sbc_init.o sg_init.o pll_init.o clkrst_init.opinctrl.o +obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile new file +1
-0+ umc_init.o(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.cnew file mode 100644 index 0000000..69b172earch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c new file +1
-0@@ -0,0 +1 @@ +#include "../ph1-ld4/bcu_init.c" (quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.cnew file mode 100644 index 0000000..15dc289arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c new file +16
-0@@ -0,0 +1,16 @@ +/* +* Copyright (C) 2012-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/arch/board.h> + +int checkboard (void ) +{ +puts ("Board: PH1-sLD8 Board\n" ); + +return check_support_card (); +}diff --git
a/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.cb/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.cnew file mode 100644 index 0000000..287b33c ---/dev/null
+++b/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.carch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c new file +1
-0@@ -0,0 +1 @@ +#include "../ph1-ld4/board_postclk_init.c" (quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.cnew file mode 100644 index 0000000..d359b56arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c new file +1
-0@@ -0,0 +1 @@ +#include "../ph1-pro4/boot-mode.c" (quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.cnew file mode 100644 index 0000000..18965a9arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c new file +25
-0@@ -0,0 +1,29 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sc-regs.h> + +void clkrst_init (void ) +{ +u32 tmp; + +/* deassert reset */ + tmp =readl (SC_RSTCTRL ); + tmp |=SC_RSTCTRL_NRST_ETHER |SC_RSTCTRL_NRST_UMC1 + |SC_RSTCTRL_NRST_UMC0 |SC_RSTCTRL_NRST_NAND ; +writel (tmp,SC_RSTCTRL ); +readl (SC_RSTCTRL );/* dummy read */ + +/* privide clocks */ + tmp =readl (SC_CLKCTRL ); + tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO |
SC_CLKCTRL_CLK_UMCarch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c new file +1
-0+ | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC |
SC_CLKCTRL_CLK_PERI;arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c new file +3
-0+writel (tmp,SC_CLKCTRL ); +readl (SC_CLKCTRL );/* dummy read */ +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.cnew file mode 100644 index 0000000..2b6403farch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c new file +36
-0@@ -0,0 +1,57 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sg-regs.h> + +void pin_init (void ) +{ +/* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL +sg_set_pinsel (70 ,3 );/* HDDOUT0 -> TXD0 */ +sg_set_pinsel (71 ,3 );/* HSDOUT1 -> RXD0 */ + +sg_set_pinsel (114 ,0 );/* TXD1 -> TXD1 */ +sg_set_pinsel (115 ,0 );/* RXD1 -> RXD1 */ + +sg_set_pinsel (112 ,1 );/* SBO1 -> TXD2 */ +sg_set_pinsel (113 ,1 );/* SBI1 -> RXD2 */ + +sg_set_pinsel (110 ,1 );/* SBO0 -> TXD3 */ +sg_set_pinsel (111 ,1 );/* SBI0 -> RXD3 */ +#endif + +#ifdef CONFIG_NAND_DENALI +sg_set_pinsel (15 ,0 );/* XNFRE_GB -> XNFRE_GB */ +sg_set_pinsel (16 ,0 );/* XNFWE_GB -> XNFWE_GB */ +sg_set_pinsel (17 ,0 );/* XFALE_GB -> NFALE_GB */ +sg_set_pinsel (18 ,0 );/* XFCLE_GB -> NFCLE_GB */ +sg_set_pinsel (19 ,0 );/* XNFWP_GB -> XFNWP_GB */ +sg_set_pinsel (20 ,0 );/* XNFCE0_GB -> XNFCE0_GB */ +sg_set_pinsel (21 ,0 );/* NANDRYBY0_GB -> NANDRYBY0_GB */
arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c new file +2
-0+sg_set_pinsel (22 ,0 );/* XFNCE1_GB -> XFNCE1_GB */ +sg_set_pinsel (23 ,0 );/* NANDRYBY1_GB ->
NANDRYBY1_GB*/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c new file +16
-0+sg_set_pinsel (24 ,0 );/* NFD0_GB -> NFD0_GB */ +sg_set_pinsel (25 ,0 );/* NFD1_GB -> NFD1_GB */ +sg_set_pinsel (26 ,0 );/* NFD2_GB -> NFD2_GB */ +sg_set_pinsel (27 ,0 );/* NFD3_GB -> NFD3_GB */ +sg_set_pinsel (28 ,0 );/* NFD4_GB -> NFD4_GB */ +sg_set_pinsel (29 ,0 );/* NFD5_GB -> NFD5_GB */ +sg_set_pinsel (30 ,0 );/* NFD6_GB -> NFD6_GB */ +sg_set_pinsel (31 ,0 );/* NFD7_GB -> NFD7_GB */ +#endif + +#ifdef CONFIG_USB_EHCI_UNIPHIER +sg_set_pinsel (41 ,0 );/* USB0VBUS -> USB0VBUS */ +sg_set_pinsel (42 ,0 );/* USB0OD -> USB0OD */ +sg_set_pinsel (43 ,0 );/* USB1VBUS -> USB1VBUS */ +sg_set_pinsel (44 ,0 );/* USB1OD -> USB1OD */ +/* sg_set_pinsel(114, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */
arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c new file +3
-0+/* sg_set_pinsel(115, 4); */ /* RXD1 -> USB2OD */ +#endif +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.cnew file mode 100644 index 0000000..76c5116arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c new file +65
-0@@ -0,0 +1,201 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sc-regs.h> +#include <asm/arch/sg-regs.h> + +void dpll_init (void ) +{ +u32 tmp; +/* +* Set DPLL SSC parameters for DPLLCTRL3 +* [23] DIVN_TEST 1'b1 +* [22:16] DIVN 7'h50 +* [10] FREFSEL_TEST 1'b1 +* [9:8] FREFSEL 2'h2 +* [4] ICPD_TEST 1'b1 +* [3:0] ICPD 4'hB +*/ + tmp =readl (SC_DPLLCTRL3 ); + tmp &= ~0x00ff0717 ; + tmp |=0x00d0061b ; +writel (tmp,SC_DPLLCTRL3 ); + +/* +* Set DPLL SSC parameters for DPLLCTRL - SSC +* <-1%> <-2%> +* [29:20] SSC_UPCNT 10'd132 (0x084) 10'd132 (0x084) +* [14:0] SSC_dK 15'd6335(0x18bf) 15'd12710(0x31a6) +*/ + tmp =readl (SC_DPLLCTRL ); + tmp &= ~0x3ff07fff ; +#if defined(CONFIG_DPLL_SSC_RATE_1PER ) + tmp |=0x084018bf ; +#else + tmp |=0x084031a6 ; +#endif /* defined(CONFIG_DPLL_SSC_RATE_1PER) */ +writel (tmp,SC_DPLLCTRL ); + +/* +* Set DPLL SSC parameters for DPLLCTRL2 +* [31:29] SSC_STEP 3' d0 (0x0) +* [27] SSC_REG_REF 1' b1 (0x1) +* [26:20] SSC_M 7' d79 (0x4f) +* [19:0] SSC_K 20'd964689(0xeb851) +*/ + tmp =readl (SC_DPLLCTRL2 ); + tmp &= ~0xefffffff ; + tmp |=0x0cfeb851 ; +writel (tmp,SC_DPLLCTRL2 ); +} + +void upll_init (void ) +{ +u32 tmp, clk_mode_upll, clk_mode_axosel; + + tmp =readl (SG_PINMON0 ); + clk_mode_upll = tmp &SG_PINMON0_CLK_MODE_UPLLSRC_MASK ; + clk_mode_axosel = tmp &SG_PINMON0_CLK_MODE_AXOSEL_MASK ; + +/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c new file +6
-0+ tmp =readl (SC_UPLLCTRL ); + tmp &= ~0x18000000 ; +writel (tmp,SC_UPLLCTRL ); + +if (clk_mode_upll ==SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT ) { + if (clk_mode_axosel ==
SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U||arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c new file +1
-0+ clk_mode_axosel ==
SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c new file +66
-0+/* AXO: 25MHz */ + tmp &= ~0x07ffffff ; + tmp |=0x0228f5c0 ; + }else { +/* AXO: default 24.576MHz */ + tmp &= ~0x07ffffff ; + tmp |=0x02328000 ; + } + } + +writel (tmp,SC_UPLLCTRL ); + +/* set 1 to K_LD(UPLLCTRL.bit[27]) */ + tmp |=0x08000000 ; +writel (tmp,SC_UPLLCTRL ); + +/* wait 10 usec */ +udelay (10 ); + +/* set 1 to SNRT(UPLLCTRL.bit[28]) */ + tmp |=0x10000000 ; +writel (tmp,SC_UPLLCTRL ); +} + +void vpll_init (void ) +{ +u32 tmp, clk_mode_axosel; + + tmp =readl (SG_PINMON0 ); + clk_mode_axosel = tmp &SG_PINMON0_CLK_MODE_AXOSEL_MASK ; + +/* set 1 to VPLA27WP and VPLA27WP */ + tmp =readl (SC_VPLL27ACTRL ); + tmp |=0x00000001 ; +writel (tmp,SC_VPLL27ACTRL ); + tmp =readl (SC_VPLL27BCTRL ); + tmp |=0x00000001 ; +writel (tmp,SC_VPLL27BCTRL ); + +/* Set 0 to VPLA_K_LD and VPLB_K_LD */ + tmp =readl (SC_VPLL27ACTRL3 ); + tmp &= ~0x10000000 ; +writel (tmp,SC_VPLL27ACTRL3 ); + tmp =readl (SC_VPLL27BCTRL3 ); + tmp &= ~0x10000000 ; +writel (tmp,SC_VPLL27BCTRL3 ); + +/* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp =readl (SC_VPLL27ACTRL2 ); + tmp &= ~0x10000000 ; +writel (tmp,SC_VPLL27ACTRL2 ); + tmp =readl (SC_VPLL27BCTRL2 ); + tmp &= ~0x10000000 ; +writel (tmp,SC_VPLL27BCTRL2 ); + +/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ + tmp =readl (SC_VPLL27ACTRL2 ); + tmp &= ~0x0000007f ; + tmp |=0x00000020 ; +writel (tmp,SC_VPLL27ACTRL2 ); + tmp =readl (SC_VPLL27BCTRL2 ); + tmp &= ~0x0000007f ; + tmp |=0x00000020 ; +writel (tmp,SC_VPLL27BCTRL2 ); + + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U||
arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c new file +1
-0+ clk_mode_axosel ==
SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c new file +62
-0+/* AXO: 25MHz */ + tmp =readl (SC_VPLL27ACTRL3 ); + tmp &= ~0x000fffff ; + tmp |=0x00066664 ; +writel (tmp,SC_VPLL27ACTRL3 ); + tmp =readl (SC_VPLL27BCTRL3 ); + tmp &= ~0x000fffff ; + tmp |=0x00066664 ; +writel (tmp,SC_VPLL27BCTRL3 ); + }else { +/* AXO: default 24.576MHz */ + tmp =readl (SC_VPLL27ACTRL3 ); + tmp &= ~0x000fffff ; + tmp |=0x000f5800 ; +writel (tmp,SC_VPLL27ACTRL3 ); + tmp =readl (SC_VPLL27BCTRL3 ); + tmp &= ~0x000fffff ; + tmp |=0x000f5800 ; +writel (tmp,SC_VPLL27BCTRL3 ); + } + +/* Set 1 to VPLA_K_LD and VPLB_K_LD */ + tmp =readl (SC_VPLL27ACTRL3 ); + tmp |=0x10000000 ; +writel (tmp,SC_VPLL27ACTRL3 ); + tmp =readl (SC_VPLL27BCTRL3 ); + tmp |=0x10000000 ; +writel (tmp,SC_VPLL27BCTRL3 ); + +/* wait 10 usec */ +udelay (10 ); + +/* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp =readl (SC_VPLL27ACTRL2 ); + tmp |=0x10000000 ; +writel (tmp,SC_VPLL27ACTRL2 ); + tmp =readl (SC_VPLL27BCTRL2 ); + tmp |=0x10000000 ; +writel (tmp,SC_VPLL27BCTRL2 ); + +/* set 0 to VPLA27WP and VPLA27WP */ + tmp =readl (SC_VPLL27ACTRL ); + tmp &= ~0x00000001 ; +writel (tmp,SC_VPLL27ACTRL ); + tmp =readl (SC_VPLL27BCTRL ); + tmp |= ~0x00000001 ; +writel (tmp,SC_VPLL27BCTRL ); +} + +void pll_init (void ) +{ +dpll_init (); +upll_init (); +vpll_init (); + +/* +* Wait 500 usec until dpll get stable +* We wait 10 usec in upll_init() and vpll_init() +* so 20 usec can be saved here. +*/ +udelay (480 ); +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.cnew file mode 100644 index 0000000..9b8c485arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c new file +1
-0@@ -0,0 +1 @@ +#include "../ph1-ld4/pll_spectrum.c" (quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.cnew file mode 100644 index 0000000..af44deearch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c new file +51
-0@@ -0,0 +1,51 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sbc-regs.h> +#include <asm/arch/sg-regs.h> + +void sbc_init (void ) +{ +#if !defined(CONFIG_SPL_BUILD ) +/* XECS0 : dummy */ +writel (SBCTRL0_SAVEPIN_MEM_VALUE ,SBCTRL00 ); +writel (SBCTRL1_SAVEPIN_MEM_VALUE ,SBCTRL01 ); +writel (SBCTRL2_SAVEPIN_MEM_VALUE ,SBCTRL02 ); +writel (SBCTRL4_SAVEPIN_MEM_VALUE ,SBCTRL04 ); +#endif +/* XECS1 : boot memory (always boot swap = on) */ +writel (SBCTRL0_SAVEPIN_MEM_VALUE ,SBCTRL10 ); +writel (SBCTRL1_SAVEPIN_MEM_VALUE ,SBCTRL11 ); +writel (SBCTRL2_SAVEPIN_MEM_VALUE ,SBCTRL12 ); +writel (SBCTRL4_SAVEPIN_MEM_VALUE ,SBCTRL14 ); + +/* XECS4 : sub memory */ +writel (SBCTRL0_SAVEPIN_MEM_VALUE ,SBCTRL40 ); +writel (SBCTRL1_SAVEPIN_MEM_VALUE ,SBCTRL41 ); +writel (SBCTRL2_SAVEPIN_MEM_VALUE ,SBCTRL42 ); +writel (SBCTRL4_SAVEPIN_MEM_VALUE ,SBCTRL44 ); + +/* XECS5 : peripherals */ +writel (SBCTRL0_SAVEPIN_PERI_VALUE ,SBCTRL50 ); +writel (SBCTRL1_SAVEPIN_PERI_VALUE ,SBCTRL51 ); +writel (SBCTRL2_SAVEPIN_PERI_VALUE ,SBCTRL52 ); +writel (SBCTRL4_SAVEPIN_PERI_VALUE ,SBCTRL54 ); + +/* base address regsiters */ +writel (0x0000bc01 ,SBBASE0 );/* boot memory */ +writel (0x0900bfff ,SBBASE1 );/* dummy */ +writel (0x0400bc01 ,SBBASE4 );/* sub memory */ +writel (0x0800bf01 ,SBBASE5 );/* peripherals */ + +sg_set_pinsel (134 ,16 );/* XIRQ6 -> XECS4 */ +sg_set_pinsel (135 ,16 );/* XIRQ7 -> XECS5 */ + +/* dummy read to assure write process */ +readl (SG_PINCTRL (33 )); +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.cnew file mode 100644 index 0000000..a808289arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c new file +1
-0@@ -0,0 +1 @@ +#include "../ph1-ld4/sg_init.c" (quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.cnew file mode 100644 index 0000000..e0e586barch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c new file +10
-0@@ -0,0 +1,10 @@ +/* +* Copyright (C) 2011-2014 Panasonic Corporation +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +int umc_init (void ) +{ +return 0 ; +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/reset.cnew file mode 100644 index 0000000..b0dc967arch/arm/cpu/armv7/uniphier/reset.c new file +29
-0@@ -0,0 +1,29 @@ +/* +* Copyright (C) 2012-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sc-regs.h> +#include <asm/arch/board.h> + +void reset_cpu (unsigned long ignored) +{ +u32 tmp; + +uniphier_board_reset (); + +writel (5 ,SC_IRQTIMSET );/* default value */ + + tmp =readl (SC_SLFRSTSEL ); + tmp &= ~0x3 ;/* mask [1:0] */ + tmp |=0x0 ;/* XRST reboot */ +writel (tmp,SC_SLFRSTSEL ); + + tmp =readl (SC_SLFRSTCTL ); + tmp |=0x1 ; +writel (tmp,SC_SLFRSTCTL ); +}(quoted diff) +0
-0
b/arch/arm/cpu/armv7/uniphier/smp.Snew file mode 100644 index 0000000..25ba981arch/arm/cpu/armv7/uniphier/smp.S new file +16
-0@@ -0,0 +1,54 @@ +/* + * Copyright (C) 2013 Panasonic Corporation + * Author: Masahiro Yamada <[email protected]> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/linkage.h> +#include <asm/system.h> +#include <asm/arch/led.h> +#include <asm/arch/sbc-regs.h> + +/* Entry point of U-Boot main program for the secondary CPU */ +LENTRY(secondary_entry) + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (SystemContrl Register)
arch/arm/cpu/armv7/uniphier/smp.S new file +1
-0+ bic r0, r0, #(CR_C | CR_M) @ MMU and Dcachedisable
arch/arm/cpu/armv7/uniphier/smp.S new file +10
-0+ mcr p15, 0, r0, c1, c0, 0 + mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs + mcr p15, 0, r0, c7, c5, 0 @ invalidate icache + dsb + led_write(C,0,,) + ldr r1, =ROM_BOOT_ROMRSV2 + mov r0, #0 + str r0, [r1] +0: wfe + ldr r4, [r1] @ r4: entry point forsecondary CPUs
arch/arm/cpu/armv7/uniphier/smp.S new file +4
-0+ cmp r4, #0 + beq 0b + led_write(C, P, U, 1) + bx r4 @ secondary CPUs jump tolinux +ENDPROC(secondary_entry)
arch/arm/cpu/armv7/uniphier/smp.S new file +13
-0+ +ENTRY(wakeup_secondary) + ldr r1, =ROM_BOOT_ROMRSV2 +0: ldr r0, [r1] + cmp r0, #0 + bne 0b + + /* set entry address and send event to the secondary CPU */ + ldr r0, =secondary_entry + str r0, [r1] + ldr r0, [r1] @ make sure store is complete + mov r0, #0x100 +0: subs r0, r0, #1 @ I don't know the reason,but without this wait
arch/arm/cpu/armv7/uniphier/smp.S new file +1
-0+ bne 0b @ fails to wake up thesecondary CPU
arch/arm/cpu/armv7/uniphier/smp.S new file +8
-0+ sev + + /* wait until the secondary CPU reach to secondary_entry */ +0: ldr r0, [r1] + cmp r0, #0 + bne 0b + bx lr +ENDPROC(wakeup_secondary)(quoted diff) +0
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b/arch/arm/cpu/armv7/uniphier/spl.cnew file mode 100644 index 0000000..40d28adarch/arm/cpu/armv7/uniphier/spl.c new file +17
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b/arch/arm/cpu/armv7/uniphier/support_card.cnew file mode 100644 index 0000000..40d4940arch/arm/cpu/armv7/uniphier/support_card.c new file +15
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0x000D0034) +#definePFC_MICRO_SUPPORT_CARD_REVISION\arch/arm/cpu/armv7/uniphier/support_card.c new file +1
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0x000D00E0) +/*
+ * 0: reset deassert, 1: reset
+ *
+ * bit[0]: LAN, I2C, LED
+ * bit[1]: UART
+ */arch/arm/cpu/armv7/uniphier/support_card.c new file +16
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&
0xf);arch/arm/cpu/armv7/uniphier/support_card.c new file +8
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0x00401300) +#defineDCC_MICRO_SUPPORT_CARD_RESET_UART\arch/arm/cpu/armv7/uniphier/support_card.c new file +1
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0x00401304) +#defineDCC_MICRO_SUPPORT_CARD_RESET_I2C\arch/arm/cpu/armv7/uniphier/support_card.c new file +1
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0x00401308) +#defineDCC_MICRO_SUPPORT_CARD_REVISION\arch/arm/cpu/armv7/uniphier/support_card.c new file +1
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0x005000E0) +arch/arm/cpu/armv7/uniphier/support_card.c new file +3
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*/
arch/arm/cpu/armv7/uniphier/support_card.c new file +7
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*/
arch/arm/cpu/armv7/uniphier/support_card.c new file +25
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reset state
arch/arm/cpu/armv7/uniphier/support_card.c new file +2
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pll_init()arch/arm/cpu/armv7/uniphier/support_card.c new file +44
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MAP_NOCACHE); +arch/arm/cpu/armv7/uniphier/support_card.c new file +37
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i;
arch/arm/cpu/armv7/uniphier/support_card.c new file +7
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b/arch/arm/cpu/armv7/uniphier/timer.cnew file mode 100644 index 0000000..6edc084arch/arm/cpu/armv7/uniphier/timer.c new file +36
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GTIMER_CTRL); +arch/arm/cpu/armv7/uniphier/timer.c new file +2
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b/arch/arm/include/asm/arch-uniphier/arm-mpcore.hnew file mode 100644 index 0000000..cf7cd46arch/arm/include/asm/arch-uniphier/arm-mpcore.h new file +46
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b/arch/arm/include/asm/arch-uniphier/bcu-regs.hnew file mode 100644 index 0000000..5501b36arch/arm/include/asm/arch-uniphier/bcu-regs.h new file +21
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* 4) +#define BCIPPCCHR0 (BCIPPCCHR(0))
arch/arm/include/asm/arch-uniphier/bcu-regs.h new file +7
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b/arch/arm/include/asm/arch-uniphier/board.hnew file mode 100644 index 0000000..e6ba4e4arch/arm/include/asm/arch-uniphier/board.h new file +35
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b/arch/arm/include/asm/arch-uniphier/boot-device.hnew file mode 100644 index 0000000..6987f57arch/arm/include/asm/arch-uniphier/boot-device.h new file +20
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b/arch/arm/include/asm/arch-uniphier/led.hnew file mode 100644 index 0000000..21277daarch/arm/include/asm/arch-uniphier/led.h new file +71
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C3) +.macro
raw_led_writedataarch/arm/include/asm/arch-uniphier/led.h new file +29
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b/arch/arm/include/asm/arch-uniphier/sbc-regs.hnew file mode 100644 index 0000000..397d5b4arch/arm/include/asm/arch-uniphier/sbc-regs.h new file +107
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b/arch/arm/include/asm/arch-uniphier/sc-regs.hnew file mode 100644 index 0000000..4d4dfdfarch/arm/include/asm/arch-uniphier/sc-regs.h new file +33
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0x1274) +#defineSC_VPLL27ACTRL3(SC_BASE_ADDR
|0x1278) +arch/arm/include/asm/arch-uniphier/sc-regs.h new file +2
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0x1294) +#defineSC_VPLL27BCTRL3(SC_BASE_ADDR
|0x1298) +arch/arm/include/asm/arch-uniphier/sc-regs.h new file +23
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b/arch/arm/include/asm/arch-uniphier/sg-regs.hnew file mode 100644 index 0000000..4136774arch/arm/include/asm/arch-uniphier/sg-regs.h new file +19
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SG_REVISION_TYPE_SHIFT) +#defineSG_REVISION_MODEL_SHIFT8 +#defineSG_REVISION_MODEL_MASK(0x3<<SG_REVISION_MODEL_SHIFT) +#defineSG_REVISION_REV_SHIFT0 +#defineSG_REVISION_REV_MASK(0x1f<<SG_REVISION_REV_SHIFT) +
+/* Memory Configuration */ +#defineSG_MEMCONF(SG_CTRL_BASE|0x0400) +arch/arm/include/asm/arch-uniphier/sg-regs.h new file +20
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0x1000) +arch/arm/include/asm/arch-uniphier/sg-regs.h new file +2
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* 8) +#elif
defined(CONFIG_PH1_LD4)||defined(CONFIG_PH1_SLD8)
+# defineSG_PINCTRL(n)(SG_PINCTRL_BASE+ (n)
* 4) +#endifarch/arm/include/asm/arch-uniphier/sg-regs.h new file +8
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(
SG_PINSELBITS) / 32)) +#defineSG_PINSEL_MASK(n)
(~(((1 << (SG_PINSELBITS)) - 1) << \arch/arm/include/asm/arch-uniphier/sg-regs.h new file +1
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(
SG_PINSELBITS) % 32))) +#define SG_PINSEL_MODE(n,
mode) ((mode) << ((n) * (SG_PINSELBITS) % 32)) +arch/arm/include/asm/arch-uniphier/sg-regs.h new file +117
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b/arch/arm/include/asm/arch-uniphier/ssc-regs.hnew file mode 100644 index 0000000..ae49956arch/arm/include/asm/arch-uniphier/ssc-regs.h new file +62
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Quoted 3 lines
(
SSC_NUM_ENTRIES)) +#defineSSC_RANGE_OP_MAX_SIZE(0x00400000
- (SSC_LINE_SIZE)) +
+#endif /*ARCH_SSC_REGS_H*/
Amicalement,
Signature · 1 line
Albert.
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PATCH 3/6 arm: uniphier: add UniPhier SoC suppurt code
Hi Albert,
First, I don't like full-quoting as Wolfgang also mentioned before:
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/52214/focus=52252
Since this patch is very long, I might miss some of your comments.
If I did not overlook, my comments are below:
Quoted 9 lines · On Wed, 20 Aug 2014 11:31:26 +0200 Albert ARIBAUD <[email protected]>…
Hi Masahiro,
Quoted 1 line · Masahiro Yamada
Subject: [PATCH 3/6] arm: uniphier: add UniPhier SoC suppurt code
Typo in subject -- since you're going to do a v2, please fix this too, thanks!
Oops, thanks for pointing this out.
Will fix in v2.
I am still holding v2 back because of the patch dependency.
Quoted 9 lines
Quoted 9 lines
arch/arm/cpu/armv7/uniphier/board_late_init.c new file +9
-0+} + +int board_late_init (void ) +{ +puts ("MODE: " ); + +switch (spl_boot_device ()) { +case BOOT_DEVICE_NAND : +printf ("NAND Boot\n" );
Quoted 8 lines
arch/arm/cpu/armv7/uniphier/board_late_init.c line 32
Quoted 5 lines
arch/arm/cpu/armv7/uniphier/board_late_init.c new file +5
-0+setenv ("bootmode" ,"nandboot" ); +nand_denali_wp_disable (); +break ; +default : +printf ("Unsupported Boot Mode\n" );Please add the mode value (decimal, hex or binary as you prefer, as long as the reader can understand the format) to the output.
BOOT_DEVICE_* is defined by enum in arch/arm/include/spl.h.
I don't see the necessity to display the meaningless value.
Quoted 6 lines
Quoted 6 lines
+
SSC_RANGE_OP_MAX_SIZE: size;(quoted diff) +1
-0+ __uniphier_cache_maint_range(start, chunk_size,operation); +
arch/arm/cpu/armv7/uniphier/cache_uniphier.c new file +2
-0+ start += chunk_size; + size -= chunk_size;
Quoted 8 lines
arch/arm/cpu/armv7/uniphier/cache_uniphier.c line 92
Quoted 4 lines
arch/arm/cpu/armv7/uniphier/cache_uniphier.c new file +4
-0+ } + +writel (SSCOPE_CM_SYNC ,SSCOPE );/* drain internal buffers */ +readl (SSCOPE );/* need a read back to confirm */ Does the readback contain some status showing whether the drain is in progress vs. complete? If it does, then shouldn't the line above be a loop waiting for completion?
Not really.
I am not familiar enough with this cache block to tell you its detail but the hardware manual clearly says to read back SSCOPE register so I am following it.
Quoted 28 lines
Quoted 28 lines
arch/arm/cpu/armv7/uniphier/cpu_info.c new file +4
-0+ +int print_cpuinfo (void ) +{ + u32 revision, type, model, rev, required_model = 1,
required_rev= 1; +(quoted diff) +2
-0+ revision = readl(SG_REVISION); + type = (revision & SG_REVISION_TYPE_MASK) >>
SG_REVISION_TYPE_SHIFT;(quoted diff) +1
-0+ model = (revision & SG_REVISION_MODEL_MASK) >>
SG_REVISION_MODEL_SHIFT;(quoted diff) +1
-0+ rev = (revision & SG_REVISION_REV_MASK) >>
SG_REVISION_REV_SHIFT; +arch/arm/cpu/armv7/uniphier/cpu_info.c new file +16
-0+puts ("CPU: " ); + +switch (type) { +case 0x25 : +puts ("PH1-sLD3 (MN2WS0220)" ); + required_model =2 ; +break ; +case 0x26 : +puts ("PH1-LD4 (MN2WS0250)" ); + required_rev =2 ; +break ; +case 0x28 : +puts ("PH1-Pro4 (MN2WS0230)" ); +break ; +case 0x29 : +puts ("PH1-sLD8 (MN2WS0270)" );
Quoted 8 lines
arch/arm/cpu/armv7/uniphier/cpu_info.c line 41
Quoted 5 lines
arch/arm/cpu/armv7/uniphier/cpu_info.c new file +5
-0+break ; +default : +printf ("Unknown Processor ID (0x%x)\n" , revision); +return -1 ; + }Maybe use symbolic constants rather tha magic numbers in switch cases above.
Do you want me to do like this?
#define PH1_SLD3_ID 0x25
#define PH1_LD4_ID 0x26
#define PH1_PRO4_ID 0x28
#define PH1_SLD8_ID 0x29
switch (type) {
case PH1_SLD3_ID:
puts("PH1-sLD3 (MN2WS0220)");
required_model = 2;
break;
case PH1_LD4_ID:
puts("PH1-LD4 (MN2WS0250)");
required_rev = 2;
break;
case PH1_PRO4_ID:
puts("PH1-Pro4 (MN2WS0230)");
break;
case PH1_SLD8_ID:
puts("PH1-sLD8 (MN2WS0270)");
break;
default:
printf("Unknown Processor ID (0x%x)\n", revision);
return -1;
}I am not sure if we should be strict to the magic number rule here in this code.
It is true 0x25 is a magic number but
its meaning is apparent enough at a glance.
Quoted 8 lines
Quoted 2 lines
(quoted diff) +1
-0+ TBL_ENTRY(0xffc), TBL_ENTRY(0xffd), TBL_ENTRY(0xffe),
TBL_ENTRY(0xfff), +};This table seems rather predictable -- the value of each entry seems to be computable from the index alone. Is there a shorter way to define it? I mean, here, it is an initialized non-const, bu we could also make it a un-initialized non-const and fill it through a for-loop, could we not?
I wish I could, but it is impossible.
UnPhier SoCs have no dedicated SRAM; it is shared with L2 Cache. To turn on L2 Cache, this page table is necessary.
At the time, no writable memory is available yet.
That is why this table must be computed at the compilation and placed in the .rodata section.
Indeed, this is an unfortunate hardware specification.
Quoted 19 lines
Quoted 19 lines
arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c new file +19
-0+ +int board_postclk_init (void ) +{ +bcu_init (); + +sbc_init (); + +sg_init (); + +pll_init (); + +uniphier_board_init (); + + led_write(B, 1, , ); + +pin_init (); + + led_write(B, 2, , ); +
Quoted 8 lines
arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c line 41
Quoted 5 lines
arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c new file +5
-0+clkrst_init (); + + led_write(B, 3, , ); + +return 0 ;Can you remove the blank lines? Ditto in other places where double spacing occurs.
Assume you mentioned led_write(B, 1, , ).
This is not a function but a macro.
It is impossible to remove the blank arguments.
Best Regards
Masahiro Yamada
PATCH 4/6 arm: uniphier: add UniPhier config headers
In reply to Masahiro YamadaConfiguration headers for Panasonic UniPhier series:
PH1-LD4, PH1-Pro4, PH1-sLD8
---
include/configs/ph1_ld4.h | 64 +++++++++ include/configs/ph1_pro4.h | 66 +++++++++ include/configs/ph1_sld8.h | 64 +++++++++ include/configs/uniphier-common.h | 275 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 469 insertions(+) create mode 100644 include/configs/ph1_ld4.h create mode 100644 include/configs/ph1_pro4.h create mode 100644 include/configs/ph1_sld8.h create mode 100644 include/configs/uniphier-common.h
include/configs/ph1_ld4.h new file +64 -0
@@ -0,0 +1,64 @@ +/* +* Copyright (C) 2012-2014 Panasonic Corporation +* Author: Masahiro Yamada <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __PH1_XXX_H +#define __PH1_XXX_H + +/* +* Support Card Select +* +* CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC. +* CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card. +* CPLD is re-programmed for ARIMA board compatibility. +* No define - No support card. +*/ + +#if 0 +#define CONFIG_PFC_MICRO_SUPPORT_CARD +#else +#define CONFIG_DCC_MICRO_SUPPORT_CARD +#endif + +/* +* Serial Configuration +* SoC UART : enable CONFIG_UNIPHIER_SERIAL +* On-board UART: enable CONFIG_SYS_NS16550_SERIAL +*/ +#if 0 +#define CONFIG_UNIPHIER_SERIAL +#else +#define CONFIG_SYS_NS16550_SERIAL +#endif + +#define CONFIG_SYS_UNIPHIER_UART_CLK 36864000 + +#define CONFIG_SMC911X + +/*----------------------------------------------------------------------- +* Board Type +*----------------------------------------------------------------------*/ +#define CONFIG_PH1_LD4 + +#define CONFIG_DDR_NUM_CH0 1 +#define CONFIG_DDR_NUM_CH1 1 + +#define CONFIG_DDR_FREQ 1600 + +/* +* Memory Size & Mapping +*/ +/* Physical start address of SDRAM */ +#define CONFIG_SDRAM0_BASE 0x80000000 +#define CONFIG_SDRAM0_SIZE 0x10000000 +#define CONFIG_SDRAM1_BASE 0x90000000 +#define CONFIG_SDRAM1_SIZE 0x10000000 + +#define CONFIG_SPL_TEXT_BASE 0x40000 + +#include "uniphier-common.h" + +#endif /* __PH1_XXX_H */
include/configs/ph1_pro4.h new file +66 -0
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include/configs/ph1_sld8.h new file +64 -0
64 lines not on this page · raw message
include/configs/uniphier-common.h new file +275 -0
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Signature · 1 line
1.9.1
PATCH 5/6 arm: uniphier: add board entries to boards.cfg
In reply to Masahiro YamadaAdd board entries for Panasonic UniPhier family:
PH1-LD4, PH1-Pro4, PH1-sLD8
---
boards.cfg | 3 +++ 1 file changed, 3 insertions(+)
boards.cfg +3 -0
@@ -376,6 +376,9 @@ Active arm armv7 sunxi - sunxi Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII - Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <[email protected]> Active arm armv7 u8500 st-ericsson u8500 u8500_href - - +Active arm armv7 uniphier - <none> ph1_ld4 - Masahiro Yamada <[email protected]> +Active arm armv7 uniphier - <none> ph1_pro4 - Masahiro Yamada <[email protected]> +Active arm armv7 uniphier - <none> ph1_sld8 - Masahiro Yamada <[email protected]> Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <[email protected]> Active arm armv7 zynq xilinx zynq zynq_microzed - Michal Simek <[email protected]>:Jagannadha Sutradharudu Teki <[email protected]> Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek <[email protected]>:Jagannadha Sutradharudu Teki <[email protected]>
Signature · 1 line
1.9.1
PATCH 6/6 git-mailrc: add me as the maintainer of UniPhier SoCs
In reply to Masahiro Yamada---
doc/git-mailrc | 2 ++ 1 file changed, 2 insertions(+)
doc/git-mailrc +2 -0
@@ -26,6 +26,7 @@ alias lukma Lukasz Majewski <[email protected]> alias macpaul Macpaul Lin <[email protected]> alias marex Marek Vasut <[email protected]> alias monstr Michal Simek <[email protected]> +alias masahiro Masahiro Yamada <[email protected]> alias panto Pantelis Antoniou <[email protected]> alias prafulla Prafulla Wadaskar <[email protected]> alias prom Minkyu Kang <[email protected]>
@@ -59,6 +60,7 @@ alias samsung uboot, prom alias tegra uboot, sjg, Tom Warren <[email protected]>, Stephen Warren <[email protected]> alias tegra2 tegra alias ti uboot, trini +alias uniphier uboot, masahiro alias avr32 uboot, abiessmann
Signature · 1 line
1.9.1